1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2003, 2004 Ralf Baechle 7 * Copyright (C) 2004 Maciej W. Rozycki 8 */ 9 #ifndef __ASM_CPU_FEATURES_H 10 #define __ASM_CPU_FEATURES_H 11 12 #include <asm/cpu.h> 13 #include <asm/cpu-info.h> 14 #include <cpu-feature-overrides.h> 15 16 /* 17 * SMP assumption: Options of CPU 0 are a superset of all processors. 18 * This is true for all known MIPS systems. 19 */ 20 #ifndef cpu_has_tlb 21 #define cpu_has_tlb (cpu_data[0].options & MIPS_CPU_TLB) 22 #endif 23 #ifndef cpu_has_tlbinv 24 #define cpu_has_tlbinv (cpu_data[0].options & MIPS_CPU_TLBINV) 25 #endif 26 #ifndef cpu_has_segments 27 #define cpu_has_segments (cpu_data[0].options & MIPS_CPU_SEGMENTS) 28 #endif 29 #ifndef cpu_has_eva 30 #define cpu_has_eva (cpu_data[0].options & MIPS_CPU_EVA) 31 #endif 32 33 /* 34 * For the moment we don't consider R6000 and R8000 so we can assume that 35 * anything that doesn't support R4000-style exceptions and interrupts is 36 * R3000-like. Users should still treat these two macro definitions as 37 * opaque. 38 */ 39 #ifndef cpu_has_3kex 40 #define cpu_has_3kex (!cpu_has_4kex) 41 #endif 42 #ifndef cpu_has_4kex 43 #define cpu_has_4kex (cpu_data[0].options & MIPS_CPU_4KEX) 44 #endif 45 #ifndef cpu_has_3k_cache 46 #define cpu_has_3k_cache (cpu_data[0].options & MIPS_CPU_3K_CACHE) 47 #endif 48 #define cpu_has_6k_cache 0 49 #define cpu_has_8k_cache 0 50 #ifndef cpu_has_4k_cache 51 #define cpu_has_4k_cache (cpu_data[0].options & MIPS_CPU_4K_CACHE) 52 #endif 53 #ifndef cpu_has_tx39_cache 54 #define cpu_has_tx39_cache (cpu_data[0].options & MIPS_CPU_TX39_CACHE) 55 #endif 56 #ifndef cpu_has_octeon_cache 57 #define cpu_has_octeon_cache 0 58 #endif 59 #ifndef cpu_has_fpu 60 #define cpu_has_fpu (current_cpu_data.options & MIPS_CPU_FPU) 61 #define raw_cpu_has_fpu (raw_current_cpu_data.options & MIPS_CPU_FPU) 62 #else 63 #define raw_cpu_has_fpu cpu_has_fpu 64 #endif 65 #ifndef cpu_has_32fpr 66 #define cpu_has_32fpr (cpu_data[0].options & MIPS_CPU_32FPR) 67 #endif 68 #ifndef cpu_has_counter 69 #define cpu_has_counter (cpu_data[0].options & MIPS_CPU_COUNTER) 70 #endif 71 #ifndef cpu_has_watch 72 #define cpu_has_watch (cpu_data[0].options & MIPS_CPU_WATCH) 73 #endif 74 #ifndef cpu_has_divec 75 #define cpu_has_divec (cpu_data[0].options & MIPS_CPU_DIVEC) 76 #endif 77 #ifndef cpu_has_vce 78 #define cpu_has_vce (cpu_data[0].options & MIPS_CPU_VCE) 79 #endif 80 #ifndef cpu_has_cache_cdex_p 81 #define cpu_has_cache_cdex_p (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_P) 82 #endif 83 #ifndef cpu_has_cache_cdex_s 84 #define cpu_has_cache_cdex_s (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_S) 85 #endif 86 #ifndef cpu_has_prefetch 87 #define cpu_has_prefetch (cpu_data[0].options & MIPS_CPU_PREFETCH) 88 #endif 89 #ifndef cpu_has_mcheck 90 #define cpu_has_mcheck (cpu_data[0].options & MIPS_CPU_MCHECK) 91 #endif 92 #ifndef cpu_has_ejtag 93 #define cpu_has_ejtag (cpu_data[0].options & MIPS_CPU_EJTAG) 94 #endif 95 #ifndef cpu_has_llsc 96 #define cpu_has_llsc (cpu_data[0].options & MIPS_CPU_LLSC) 97 #endif 98 #ifndef kernel_uses_llsc 99 #define kernel_uses_llsc cpu_has_llsc 100 #endif 101 #ifndef cpu_has_mips16 102 #define cpu_has_mips16 (cpu_data[0].ases & MIPS_ASE_MIPS16) 103 #endif 104 #ifndef cpu_has_mdmx 105 #define cpu_has_mdmx (cpu_data[0].ases & MIPS_ASE_MDMX) 106 #endif 107 #ifndef cpu_has_mips3d 108 #define cpu_has_mips3d (cpu_data[0].ases & MIPS_ASE_MIPS3D) 109 #endif 110 #ifndef cpu_has_smartmips 111 #define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS) 112 #endif 113 114 #ifndef cpu_has_rixi 115 # ifdef CONFIG_64BIT 116 # define cpu_has_rixi (cpu_data[0].options & MIPS_CPU_RIXI) 117 # else /* CONFIG_32BIT */ 118 # define cpu_has_rixi ((cpu_data[0].options & MIPS_CPU_RIXI) && !cpu_has_64bits) 119 # endif 120 #endif 121 122 #ifndef cpu_has_mmips 123 # ifdef CONFIG_SYS_SUPPORTS_MICROMIPS 124 # define cpu_has_mmips (cpu_data[0].options & MIPS_CPU_MICROMIPS) 125 # else 126 # define cpu_has_mmips 0 127 # endif 128 #endif 129 130 #ifndef cpu_has_vtag_icache 131 #define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG) 132 #endif 133 #ifndef cpu_has_dc_aliases 134 #define cpu_has_dc_aliases (cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES) 135 #endif 136 #ifndef cpu_has_ic_fills_f_dc 137 #define cpu_has_ic_fills_f_dc (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC) 138 #endif 139 #ifndef cpu_has_pindexed_dcache 140 #define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX) 141 #endif 142 #ifndef cpu_has_local_ebase 143 #define cpu_has_local_ebase 1 144 #endif 145 146 /* 147 * I-Cache snoops remote store. This only matters on SMP. Some multiprocessors 148 * such as the R10000 have I-Caches that snoop local stores; the embedded ones 149 * don't. For maintaining I-cache coherency this means we need to flush the 150 * D-cache all the way back to whever the I-cache does refills from, so the 151 * I-cache has a chance to see the new data at all. Then we have to flush the 152 * I-cache also. 153 * Note we may have been rescheduled and may no longer be running on the CPU 154 * that did the store so we can't optimize this into only doing the flush on 155 * the local CPU. 156 */ 157 #ifndef cpu_icache_snoops_remote_store 158 #ifdef CONFIG_SMP 159 #define cpu_icache_snoops_remote_store (cpu_data[0].icache.flags & MIPS_IC_SNOOPS_REMOTE) 160 #else 161 #define cpu_icache_snoops_remote_store 1 162 #endif 163 #endif 164 165 #ifndef cpu_has_mips_2 166 # define cpu_has_mips_2 (cpu_data[0].isa_level & MIPS_CPU_ISA_II) 167 #endif 168 #ifndef cpu_has_mips_3 169 # define cpu_has_mips_3 (cpu_data[0].isa_level & MIPS_CPU_ISA_III) 170 #endif 171 #ifndef cpu_has_mips_4 172 # define cpu_has_mips_4 (cpu_data[0].isa_level & MIPS_CPU_ISA_IV) 173 #endif 174 #ifndef cpu_has_mips_5 175 # define cpu_has_mips_5 (cpu_data[0].isa_level & MIPS_CPU_ISA_V) 176 #endif 177 #ifndef cpu_has_mips32r1 178 # define cpu_has_mips32r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1) 179 #endif 180 #ifndef cpu_has_mips32r2 181 # define cpu_has_mips32r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2) 182 #endif 183 #ifndef cpu_has_mips64r1 184 # define cpu_has_mips64r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1) 185 #endif 186 #ifndef cpu_has_mips64r2 187 # define cpu_has_mips64r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2) 188 #endif 189 190 /* 191 * Shortcuts ... 192 */ 193 #define cpu_has_mips_2_3_4_5 (cpu_has_mips_2 | cpu_has_mips_3_4_5) 194 #define cpu_has_mips_3_4_5 (cpu_has_mips_3 | cpu_has_mips_4_5) 195 #define cpu_has_mips_4_5 (cpu_has_mips_4 | cpu_has_mips_5) 196 197 #define cpu_has_mips_2_3_4_5_r (cpu_has_mips_2 | cpu_has_mips_3_4_5_r) 198 #define cpu_has_mips_3_4_5_r (cpu_has_mips_3 | cpu_has_mips_4_5_r) 199 #define cpu_has_mips_4_5_r (cpu_has_mips_4 | cpu_has_mips_5_r) 200 #define cpu_has_mips_5_r (cpu_has_mips_5 | cpu_has_mips_r) 201 202 #define cpu_has_mips_4_5_r2 (cpu_has_mips_4_5 | cpu_has_mips_r2) 203 204 #define cpu_has_mips32 (cpu_has_mips32r1 | cpu_has_mips32r2) 205 #define cpu_has_mips64 (cpu_has_mips64r1 | cpu_has_mips64r2) 206 #define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1) 207 #define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2) 208 #define cpu_has_mips_r (cpu_has_mips32r1 | cpu_has_mips32r2 | \ 209 cpu_has_mips64r1 | cpu_has_mips64r2) 210 211 #ifndef cpu_has_mips_r2_exec_hazard 212 #define cpu_has_mips_r2_exec_hazard cpu_has_mips_r2 213 #endif 214 215 /* 216 * MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other 217 * pre-MIPS32/MIPS64 processors have CLO, CLZ. The IDT RC64574 is 64-bit and 218 * has CLO and CLZ but not DCLO nor DCLZ. For 64-bit kernels 219 * cpu_has_clo_clz also indicates the availability of DCLO and DCLZ. 220 */ 221 #ifndef cpu_has_clo_clz 222 #define cpu_has_clo_clz cpu_has_mips_r 223 #endif 224 225 #ifndef cpu_has_dsp 226 #define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP) 227 #endif 228 229 #ifndef cpu_has_dsp2 230 #define cpu_has_dsp2 (cpu_data[0].ases & MIPS_ASE_DSP2P) 231 #endif 232 233 #ifndef cpu_has_mipsmt 234 #define cpu_has_mipsmt (cpu_data[0].ases & MIPS_ASE_MIPSMT) 235 #endif 236 237 #ifndef cpu_has_userlocal 238 #define cpu_has_userlocal (cpu_data[0].options & MIPS_CPU_ULRI) 239 #endif 240 241 #ifdef CONFIG_32BIT 242 # ifndef cpu_has_nofpuex 243 # define cpu_has_nofpuex (cpu_data[0].options & MIPS_CPU_NOFPUEX) 244 # endif 245 # ifndef cpu_has_64bits 246 # define cpu_has_64bits (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT) 247 # endif 248 # ifndef cpu_has_64bit_zero_reg 249 # define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT) 250 # endif 251 # ifndef cpu_has_64bit_gp_regs 252 # define cpu_has_64bit_gp_regs 0 253 # endif 254 # ifndef cpu_has_64bit_addresses 255 # define cpu_has_64bit_addresses 0 256 # endif 257 # ifndef cpu_vmbits 258 # define cpu_vmbits 31 259 # endif 260 #endif 261 262 #ifdef CONFIG_64BIT 263 # ifndef cpu_has_nofpuex 264 # define cpu_has_nofpuex 0 265 # endif 266 # ifndef cpu_has_64bits 267 # define cpu_has_64bits 1 268 # endif 269 # ifndef cpu_has_64bit_zero_reg 270 # define cpu_has_64bit_zero_reg 1 271 # endif 272 # ifndef cpu_has_64bit_gp_regs 273 # define cpu_has_64bit_gp_regs 1 274 # endif 275 # ifndef cpu_has_64bit_addresses 276 # define cpu_has_64bit_addresses 1 277 # endif 278 # ifndef cpu_vmbits 279 # define cpu_vmbits cpu_data[0].vmbits 280 # define __NEED_VMBITS_PROBE 281 # endif 282 #endif 283 284 #if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint) 285 # define cpu_has_vint (cpu_data[0].options & MIPS_CPU_VINT) 286 #elif !defined(cpu_has_vint) 287 # define cpu_has_vint 0 288 #endif 289 290 #if defined(CONFIG_CPU_MIPSR2_IRQ_EI) && !defined(cpu_has_veic) 291 # define cpu_has_veic (cpu_data[0].options & MIPS_CPU_VEIC) 292 #elif !defined(cpu_has_veic) 293 # define cpu_has_veic 0 294 #endif 295 296 #ifndef cpu_has_inclusive_pcaches 297 #define cpu_has_inclusive_pcaches (cpu_data[0].options & MIPS_CPU_INCLUSIVE_CACHES) 298 #endif 299 300 #ifndef cpu_dcache_line_size 301 #define cpu_dcache_line_size() cpu_data[0].dcache.linesz 302 #endif 303 #ifndef cpu_icache_line_size 304 #define cpu_icache_line_size() cpu_data[0].icache.linesz 305 #endif 306 #ifndef cpu_scache_line_size 307 #define cpu_scache_line_size() cpu_data[0].scache.linesz 308 #endif 309 310 #ifndef cpu_hwrena_impl_bits 311 #define cpu_hwrena_impl_bits 0 312 #endif 313 314 #ifndef cpu_has_perf_cntr_intr_bit 315 #define cpu_has_perf_cntr_intr_bit (cpu_data[0].options & MIPS_CPU_PCI) 316 #endif 317 318 #ifndef cpu_has_vz 319 #define cpu_has_vz (cpu_data[0].ases & MIPS_ASE_VZ) 320 #endif 321 322 #if defined(CONFIG_CPU_HAS_MSA) && !defined(cpu_has_msa) 323 # define cpu_has_msa (cpu_data[0].ases & MIPS_ASE_MSA) 324 #elif !defined(cpu_has_msa) 325 # define cpu_has_msa 0 326 #endif 327 328 #endif /* __ASM_CPU_FEATURES_H */ 329