1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1996, 1997, 1998, 2001 by Ralf Baechle 7 */ 8 #ifndef _ASM_BRANCH_H 9 #define _ASM_BRANCH_H 10 11 #include <asm/ptrace.h> 12 #include <asm/inst.h> 13 14 extern int __isa_exception_epc(struct pt_regs *regs); 15 extern int __compute_return_epc(struct pt_regs *regs); 16 extern int __compute_return_epc_for_insn(struct pt_regs *regs, 17 union mips_instruction insn); 18 extern int __microMIPS_compute_return_epc(struct pt_regs *regs); 19 20 21 static inline int delay_slot(struct pt_regs *regs) 22 { 23 return regs->cp0_cause & CAUSEF_BD; 24 } 25 26 static inline unsigned long exception_epc(struct pt_regs *regs) 27 { 28 if (likely(!delay_slot(regs))) 29 return regs->cp0_epc; 30 31 if (get_isa16_mode(regs->cp0_epc)) 32 return __isa_exception_epc(regs); 33 34 return regs->cp0_epc + 4; 35 } 36 37 #define BRANCH_LIKELY_TAKEN 0x0001 38 39 static inline int compute_return_epc(struct pt_regs *regs) 40 { 41 if (get_isa16_mode(regs->cp0_epc)) { 42 if (cpu_has_mmips) 43 return __microMIPS_compute_return_epc(regs); 44 return regs->cp0_epc; 45 } 46 47 if (!delay_slot(regs)) { 48 regs->cp0_epc += 4; 49 return 0; 50 } 51 52 return __compute_return_epc(regs); 53 } 54 55 #endif /* _ASM_BRANCH_H */ 56