1 /* 2 * Atomic operations that C can't guarantee us. Useful for 3 * resource counting etc.. 4 * 5 * But use these as seldom as possible since they are much more slower 6 * than regular operations. 7 * 8 * This file is subject to the terms and conditions of the GNU General Public 9 * License. See the file "COPYING" in the main directory of this archive 10 * for more details. 11 * 12 * Copyright (C) 1996, 97, 99, 2000, 03, 04, 06 by Ralf Baechle 13 */ 14 #ifndef _ASM_ATOMIC_H 15 #define _ASM_ATOMIC_H 16 17 #include <linux/irqflags.h> 18 #include <linux/types.h> 19 #include <asm/barrier.h> 20 #include <asm/compiler.h> 21 #include <asm/cpu-features.h> 22 #include <asm/cmpxchg.h> 23 #include <asm/war.h> 24 25 /* 26 * Using a branch-likely instruction to check the result of an sc instruction 27 * works around a bug present in R10000 CPUs prior to revision 3.0 that could 28 * cause ll-sc sequences to execute non-atomically. 29 */ 30 #if R10000_LLSC_WAR 31 # define __scbeqz "beqzl" 32 #else 33 # define __scbeqz "beqz" 34 #endif 35 36 #define ATOMIC_INIT(i) { (i) } 37 38 /* 39 * atomic_read - read atomic variable 40 * @v: pointer of type atomic_t 41 * 42 * Atomically reads the value of @v. 43 */ 44 #define atomic_read(v) READ_ONCE((v)->counter) 45 46 /* 47 * atomic_set - set atomic variable 48 * @v: pointer of type atomic_t 49 * @i: required value 50 * 51 * Atomically sets the value of @v to @i. 52 */ 53 #define atomic_set(v, i) WRITE_ONCE((v)->counter, (i)) 54 55 #define ATOMIC_OP(op, c_op, asm_op) \ 56 static __inline__ void atomic_##op(int i, atomic_t * v) \ 57 { \ 58 if (kernel_uses_llsc) { \ 59 int temp; \ 60 \ 61 __asm__ __volatile__( \ 62 " .set "MIPS_ISA_LEVEL" \n" \ 63 "1: ll %0, %1 # atomic_" #op " \n" \ 64 " " #asm_op " %0, %2 \n" \ 65 " sc %0, %1 \n" \ 66 "\t" __scbeqz " %0, 1b \n" \ 67 " .set mips0 \n" \ 68 : "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (v->counter) \ 69 : "Ir" (i)); \ 70 } else { \ 71 unsigned long flags; \ 72 \ 73 raw_local_irq_save(flags); \ 74 v->counter c_op i; \ 75 raw_local_irq_restore(flags); \ 76 } \ 77 } 78 79 #define ATOMIC_OP_RETURN(op, c_op, asm_op) \ 80 static __inline__ int atomic_##op##_return_relaxed(int i, atomic_t * v) \ 81 { \ 82 int result; \ 83 \ 84 if (kernel_uses_llsc) { \ 85 int temp; \ 86 \ 87 __asm__ __volatile__( \ 88 " .set "MIPS_ISA_LEVEL" \n" \ 89 "1: ll %1, %2 # atomic_" #op "_return \n" \ 90 " " #asm_op " %0, %1, %3 \n" \ 91 " sc %0, %2 \n" \ 92 "\t" __scbeqz " %0, 1b \n" \ 93 " " #asm_op " %0, %1, %3 \n" \ 94 " .set mips0 \n" \ 95 : "=&r" (result), "=&r" (temp), \ 96 "+" GCC_OFF_SMALL_ASM() (v->counter) \ 97 : "Ir" (i)); \ 98 } else { \ 99 unsigned long flags; \ 100 \ 101 raw_local_irq_save(flags); \ 102 result = v->counter; \ 103 result c_op i; \ 104 v->counter = result; \ 105 raw_local_irq_restore(flags); \ 106 } \ 107 \ 108 return result; \ 109 } 110 111 #define ATOMIC_FETCH_OP(op, c_op, asm_op) \ 112 static __inline__ int atomic_fetch_##op##_relaxed(int i, atomic_t * v) \ 113 { \ 114 int result; \ 115 \ 116 if (kernel_uses_llsc) { \ 117 int temp; \ 118 \ 119 __asm__ __volatile__( \ 120 " .set "MIPS_ISA_LEVEL" \n" \ 121 "1: ll %1, %2 # atomic_fetch_" #op " \n" \ 122 " " #asm_op " %0, %1, %3 \n" \ 123 " sc %0, %2 \n" \ 124 "\t" __scbeqz " %0, 1b \n" \ 125 " move %0, %1 \n" \ 126 " .set mips0 \n" \ 127 : "=&r" (result), "=&r" (temp), \ 128 "+" GCC_OFF_SMALL_ASM() (v->counter) \ 129 : "Ir" (i)); \ 130 } else { \ 131 unsigned long flags; \ 132 \ 133 raw_local_irq_save(flags); \ 134 result = v->counter; \ 135 v->counter c_op i; \ 136 raw_local_irq_restore(flags); \ 137 } \ 138 \ 139 return result; \ 140 } 141 142 #define ATOMIC_OPS(op, c_op, asm_op) \ 143 ATOMIC_OP(op, c_op, asm_op) \ 144 ATOMIC_OP_RETURN(op, c_op, asm_op) \ 145 ATOMIC_FETCH_OP(op, c_op, asm_op) 146 147 ATOMIC_OPS(add, +=, addu) 148 ATOMIC_OPS(sub, -=, subu) 149 150 #define atomic_add_return_relaxed atomic_add_return_relaxed 151 #define atomic_sub_return_relaxed atomic_sub_return_relaxed 152 #define atomic_fetch_add_relaxed atomic_fetch_add_relaxed 153 #define atomic_fetch_sub_relaxed atomic_fetch_sub_relaxed 154 155 #undef ATOMIC_OPS 156 #define ATOMIC_OPS(op, c_op, asm_op) \ 157 ATOMIC_OP(op, c_op, asm_op) \ 158 ATOMIC_FETCH_OP(op, c_op, asm_op) 159 160 ATOMIC_OPS(and, &=, and) 161 ATOMIC_OPS(or, |=, or) 162 ATOMIC_OPS(xor, ^=, xor) 163 164 #define atomic_fetch_and_relaxed atomic_fetch_and_relaxed 165 #define atomic_fetch_or_relaxed atomic_fetch_or_relaxed 166 #define atomic_fetch_xor_relaxed atomic_fetch_xor_relaxed 167 168 #undef ATOMIC_OPS 169 #undef ATOMIC_FETCH_OP 170 #undef ATOMIC_OP_RETURN 171 #undef ATOMIC_OP 172 173 /* 174 * atomic_sub_if_positive - conditionally subtract integer from atomic variable 175 * @i: integer value to subtract 176 * @v: pointer of type atomic_t 177 * 178 * Atomically test @v and subtract @i if @v is greater or equal than @i. 179 * The function returns the old value of @v minus @i. 180 */ 181 static __inline__ int atomic_sub_if_positive(int i, atomic_t * v) 182 { 183 int result; 184 185 smp_mb__before_llsc(); 186 187 if (kernel_uses_llsc) { 188 int temp; 189 190 __asm__ __volatile__( 191 " .set "MIPS_ISA_LEVEL" \n" 192 "1: ll %1, %2 # atomic_sub_if_positive\n" 193 " subu %0, %1, %3 \n" 194 " move %1, %0 \n" 195 " bltz %0, 1f \n" 196 " sc %1, %2 \n" 197 "\t" __scbeqz " %1, 1b \n" 198 "1: \n" 199 " .set mips0 \n" 200 : "=&r" (result), "=&r" (temp), 201 "+" GCC_OFF_SMALL_ASM() (v->counter) 202 : "Ir" (i)); 203 } else { 204 unsigned long flags; 205 206 raw_local_irq_save(flags); 207 result = v->counter; 208 result -= i; 209 if (result >= 0) 210 v->counter = result; 211 raw_local_irq_restore(flags); 212 } 213 214 smp_llsc_mb(); 215 216 return result; 217 } 218 219 #define atomic_cmpxchg(v, o, n) (cmpxchg(&((v)->counter), (o), (n))) 220 #define atomic_xchg(v, new) (xchg(&((v)->counter), (new))) 221 222 /* 223 * atomic_dec_if_positive - decrement by 1 if old value positive 224 * @v: pointer of type atomic_t 225 */ 226 #define atomic_dec_if_positive(v) atomic_sub_if_positive(1, v) 227 228 #ifdef CONFIG_64BIT 229 230 #define ATOMIC64_INIT(i) { (i) } 231 232 /* 233 * atomic64_read - read atomic variable 234 * @v: pointer of type atomic64_t 235 * 236 */ 237 #define atomic64_read(v) READ_ONCE((v)->counter) 238 239 /* 240 * atomic64_set - set atomic variable 241 * @v: pointer of type atomic64_t 242 * @i: required value 243 */ 244 #define atomic64_set(v, i) WRITE_ONCE((v)->counter, (i)) 245 246 #define ATOMIC64_OP(op, c_op, asm_op) \ 247 static __inline__ void atomic64_##op(long i, atomic64_t * v) \ 248 { \ 249 if (kernel_uses_llsc) { \ 250 long temp; \ 251 \ 252 __asm__ __volatile__( \ 253 " .set "MIPS_ISA_LEVEL" \n" \ 254 "1: lld %0, %1 # atomic64_" #op " \n" \ 255 " " #asm_op " %0, %2 \n" \ 256 " scd %0, %1 \n" \ 257 "\t" __scbeqz " %0, 1b \n" \ 258 " .set mips0 \n" \ 259 : "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (v->counter) \ 260 : "Ir" (i)); \ 261 } else { \ 262 unsigned long flags; \ 263 \ 264 raw_local_irq_save(flags); \ 265 v->counter c_op i; \ 266 raw_local_irq_restore(flags); \ 267 } \ 268 } 269 270 #define ATOMIC64_OP_RETURN(op, c_op, asm_op) \ 271 static __inline__ long atomic64_##op##_return_relaxed(long i, atomic64_t * v) \ 272 { \ 273 long result; \ 274 \ 275 if (kernel_uses_llsc) { \ 276 long temp; \ 277 \ 278 __asm__ __volatile__( \ 279 " .set "MIPS_ISA_LEVEL" \n" \ 280 "1: lld %1, %2 # atomic64_" #op "_return\n" \ 281 " " #asm_op " %0, %1, %3 \n" \ 282 " scd %0, %2 \n" \ 283 "\t" __scbeqz " %0, 1b \n" \ 284 " " #asm_op " %0, %1, %3 \n" \ 285 " .set mips0 \n" \ 286 : "=&r" (result), "=&r" (temp), \ 287 "+" GCC_OFF_SMALL_ASM() (v->counter) \ 288 : "Ir" (i)); \ 289 } else { \ 290 unsigned long flags; \ 291 \ 292 raw_local_irq_save(flags); \ 293 result = v->counter; \ 294 result c_op i; \ 295 v->counter = result; \ 296 raw_local_irq_restore(flags); \ 297 } \ 298 \ 299 return result; \ 300 } 301 302 #define ATOMIC64_FETCH_OP(op, c_op, asm_op) \ 303 static __inline__ long atomic64_fetch_##op##_relaxed(long i, atomic64_t * v) \ 304 { \ 305 long result; \ 306 \ 307 if (kernel_uses_llsc && R10000_LLSC_WAR) { \ 308 long temp; \ 309 \ 310 __asm__ __volatile__( \ 311 " .set "MIPS_ISA_LEVEL" \n" \ 312 "1: lld %1, %2 # atomic64_fetch_" #op "\n" \ 313 " " #asm_op " %0, %1, %3 \n" \ 314 " scd %0, %2 \n" \ 315 "\t" __scbeqz " %0, 1b \n" \ 316 " move %0, %1 \n" \ 317 " .set mips0 \n" \ 318 : "=&r" (result), "=&r" (temp), \ 319 "+" GCC_OFF_SMALL_ASM() (v->counter) \ 320 : "Ir" (i)); \ 321 } else { \ 322 unsigned long flags; \ 323 \ 324 raw_local_irq_save(flags); \ 325 result = v->counter; \ 326 v->counter c_op i; \ 327 raw_local_irq_restore(flags); \ 328 } \ 329 \ 330 return result; \ 331 } 332 333 #define ATOMIC64_OPS(op, c_op, asm_op) \ 334 ATOMIC64_OP(op, c_op, asm_op) \ 335 ATOMIC64_OP_RETURN(op, c_op, asm_op) \ 336 ATOMIC64_FETCH_OP(op, c_op, asm_op) 337 338 ATOMIC64_OPS(add, +=, daddu) 339 ATOMIC64_OPS(sub, -=, dsubu) 340 341 #define atomic64_add_return_relaxed atomic64_add_return_relaxed 342 #define atomic64_sub_return_relaxed atomic64_sub_return_relaxed 343 #define atomic64_fetch_add_relaxed atomic64_fetch_add_relaxed 344 #define atomic64_fetch_sub_relaxed atomic64_fetch_sub_relaxed 345 346 #undef ATOMIC64_OPS 347 #define ATOMIC64_OPS(op, c_op, asm_op) \ 348 ATOMIC64_OP(op, c_op, asm_op) \ 349 ATOMIC64_FETCH_OP(op, c_op, asm_op) 350 351 ATOMIC64_OPS(and, &=, and) 352 ATOMIC64_OPS(or, |=, or) 353 ATOMIC64_OPS(xor, ^=, xor) 354 355 #define atomic64_fetch_and_relaxed atomic64_fetch_and_relaxed 356 #define atomic64_fetch_or_relaxed atomic64_fetch_or_relaxed 357 #define atomic64_fetch_xor_relaxed atomic64_fetch_xor_relaxed 358 359 #undef ATOMIC64_OPS 360 #undef ATOMIC64_FETCH_OP 361 #undef ATOMIC64_OP_RETURN 362 #undef ATOMIC64_OP 363 364 /* 365 * atomic64_sub_if_positive - conditionally subtract integer from atomic 366 * variable 367 * @i: integer value to subtract 368 * @v: pointer of type atomic64_t 369 * 370 * Atomically test @v and subtract @i if @v is greater or equal than @i. 371 * The function returns the old value of @v minus @i. 372 */ 373 static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v) 374 { 375 long result; 376 377 smp_mb__before_llsc(); 378 379 if (kernel_uses_llsc) { 380 long temp; 381 382 __asm__ __volatile__( 383 " .set "MIPS_ISA_LEVEL" \n" 384 "1: lld %1, %2 # atomic64_sub_if_positive\n" 385 " dsubu %0, %1, %3 \n" 386 " move %1, %0 \n" 387 " bltz %0, 1f \n" 388 " scd %1, %2 \n" 389 "\t" __scbeqz " %1, 1b \n" 390 "1: \n" 391 " .set mips0 \n" 392 : "=&r" (result), "=&r" (temp), 393 "+" GCC_OFF_SMALL_ASM() (v->counter) 394 : "Ir" (i)); 395 } else { 396 unsigned long flags; 397 398 raw_local_irq_save(flags); 399 result = v->counter; 400 result -= i; 401 if (result >= 0) 402 v->counter = result; 403 raw_local_irq_restore(flags); 404 } 405 406 smp_llsc_mb(); 407 408 return result; 409 } 410 411 #define atomic64_cmpxchg(v, o, n) \ 412 ((__typeof__((v)->counter))cmpxchg(&((v)->counter), (o), (n))) 413 #define atomic64_xchg(v, new) (xchg(&((v)->counter), (new))) 414 415 /* 416 * atomic64_dec_if_positive - decrement by 1 if old value positive 417 * @v: pointer of type atomic64_t 418 */ 419 #define atomic64_dec_if_positive(v) atomic64_sub_if_positive(1, v) 420 421 #endif /* CONFIG_64BIT */ 422 423 #endif /* _ASM_ATOMIC_H */ 424