1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2003 Ralf Baechle 7 */ 8 #ifndef _ASM_ASMMACRO_H 9 #define _ASM_ASMMACRO_H 10 11 #include <asm/hazards.h> 12 #include <asm/asm-offsets.h> 13 #include <asm/msa.h> 14 15 #ifdef CONFIG_32BIT 16 #include <asm/asmmacro-32.h> 17 #endif 18 #ifdef CONFIG_64BIT 19 #include <asm/asmmacro-64.h> 20 #endif 21 22 /* preprocessor replaces the fp in ".set fp=64" with $30 otherwise */ 23 #undef fp 24 25 /* 26 * Helper macros for generating raw instruction encodings. 27 */ 28 #ifdef CONFIG_CPU_MICROMIPS 29 .macro insn32_if_mm enc 30 .insn 31 .hword ((\enc) >> 16) 32 .hword ((\enc) & 0xffff) 33 .endm 34 35 .macro insn_if_mips enc 36 .endm 37 #else 38 .macro insn32_if_mm enc 39 .endm 40 41 .macro insn_if_mips enc 42 .insn 43 .word (\enc) 44 .endm 45 #endif 46 47 #ifdef CONFIG_CPU_HAS_DIEI 48 .macro local_irq_enable reg=t0 49 ei 50 irq_enable_hazard 51 .endm 52 53 .macro local_irq_disable reg=t0 54 di 55 irq_disable_hazard 56 .endm 57 #else /* !CONFIG_CPU_MIPSR2 && !CONFIG_CPU_MIPSR5 && !CONFIG_CPU_MIPSR6 */ 58 .macro local_irq_enable reg=t0 59 mfc0 \reg, CP0_STATUS 60 ori \reg, \reg, 1 61 mtc0 \reg, CP0_STATUS 62 irq_enable_hazard 63 .endm 64 65 .macro local_irq_disable reg=t0 66 #ifdef CONFIG_PREEMPTION 67 lw \reg, TI_PRE_COUNT($28) 68 addi \reg, \reg, 1 69 sw \reg, TI_PRE_COUNT($28) 70 #endif 71 mfc0 \reg, CP0_STATUS 72 ori \reg, \reg, 1 73 xori \reg, \reg, 1 74 mtc0 \reg, CP0_STATUS 75 irq_disable_hazard 76 #ifdef CONFIG_PREEMPTION 77 lw \reg, TI_PRE_COUNT($28) 78 addi \reg, \reg, -1 79 sw \reg, TI_PRE_COUNT($28) 80 #endif 81 .endm 82 #endif /* !CONFIG_CPU_MIPSR2 && !CONFIG_CPU_MIPSR5 && !CONFIG_CPU_MIPSR6 */ 83 84 .macro fpu_save_16even thread tmp=t0 85 .set push 86 .set hardfloat 87 cfc1 \tmp, fcr31 88 sdc1 $f0, THREAD_FPR0(\thread) 89 sdc1 $f2, THREAD_FPR2(\thread) 90 sdc1 $f4, THREAD_FPR4(\thread) 91 sdc1 $f6, THREAD_FPR6(\thread) 92 sdc1 $f8, THREAD_FPR8(\thread) 93 sdc1 $f10, THREAD_FPR10(\thread) 94 sdc1 $f12, THREAD_FPR12(\thread) 95 sdc1 $f14, THREAD_FPR14(\thread) 96 sdc1 $f16, THREAD_FPR16(\thread) 97 sdc1 $f18, THREAD_FPR18(\thread) 98 sdc1 $f20, THREAD_FPR20(\thread) 99 sdc1 $f22, THREAD_FPR22(\thread) 100 sdc1 $f24, THREAD_FPR24(\thread) 101 sdc1 $f26, THREAD_FPR26(\thread) 102 sdc1 $f28, THREAD_FPR28(\thread) 103 sdc1 $f30, THREAD_FPR30(\thread) 104 sw \tmp, THREAD_FCR31(\thread) 105 .set pop 106 .endm 107 108 .macro fpu_save_16odd thread 109 .set push 110 .set mips64r2 111 .set fp=64 112 .set hardfloat 113 sdc1 $f1, THREAD_FPR1(\thread) 114 sdc1 $f3, THREAD_FPR3(\thread) 115 sdc1 $f5, THREAD_FPR5(\thread) 116 sdc1 $f7, THREAD_FPR7(\thread) 117 sdc1 $f9, THREAD_FPR9(\thread) 118 sdc1 $f11, THREAD_FPR11(\thread) 119 sdc1 $f13, THREAD_FPR13(\thread) 120 sdc1 $f15, THREAD_FPR15(\thread) 121 sdc1 $f17, THREAD_FPR17(\thread) 122 sdc1 $f19, THREAD_FPR19(\thread) 123 sdc1 $f21, THREAD_FPR21(\thread) 124 sdc1 $f23, THREAD_FPR23(\thread) 125 sdc1 $f25, THREAD_FPR25(\thread) 126 sdc1 $f27, THREAD_FPR27(\thread) 127 sdc1 $f29, THREAD_FPR29(\thread) 128 sdc1 $f31, THREAD_FPR31(\thread) 129 .set pop 130 .endm 131 132 .macro fpu_save_double thread status tmp 133 #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPSR2) || \ 134 defined(CONFIG_CPU_MIPSR5) || defined(CONFIG_CPU_MIPSR6) 135 sll \tmp, \status, 5 136 bgez \tmp, 10f 137 fpu_save_16odd \thread 138 10: 139 #endif 140 fpu_save_16even \thread \tmp 141 .endm 142 143 .macro fpu_restore_16even thread tmp=t0 144 .set push 145 .set hardfloat 146 lw \tmp, THREAD_FCR31(\thread) 147 ldc1 $f0, THREAD_FPR0(\thread) 148 ldc1 $f2, THREAD_FPR2(\thread) 149 ldc1 $f4, THREAD_FPR4(\thread) 150 ldc1 $f6, THREAD_FPR6(\thread) 151 ldc1 $f8, THREAD_FPR8(\thread) 152 ldc1 $f10, THREAD_FPR10(\thread) 153 ldc1 $f12, THREAD_FPR12(\thread) 154 ldc1 $f14, THREAD_FPR14(\thread) 155 ldc1 $f16, THREAD_FPR16(\thread) 156 ldc1 $f18, THREAD_FPR18(\thread) 157 ldc1 $f20, THREAD_FPR20(\thread) 158 ldc1 $f22, THREAD_FPR22(\thread) 159 ldc1 $f24, THREAD_FPR24(\thread) 160 ldc1 $f26, THREAD_FPR26(\thread) 161 ldc1 $f28, THREAD_FPR28(\thread) 162 ldc1 $f30, THREAD_FPR30(\thread) 163 ctc1 \tmp, fcr31 164 .set pop 165 .endm 166 167 .macro fpu_restore_16odd thread 168 .set push 169 .set mips64r2 170 .set fp=64 171 .set hardfloat 172 ldc1 $f1, THREAD_FPR1(\thread) 173 ldc1 $f3, THREAD_FPR3(\thread) 174 ldc1 $f5, THREAD_FPR5(\thread) 175 ldc1 $f7, THREAD_FPR7(\thread) 176 ldc1 $f9, THREAD_FPR9(\thread) 177 ldc1 $f11, THREAD_FPR11(\thread) 178 ldc1 $f13, THREAD_FPR13(\thread) 179 ldc1 $f15, THREAD_FPR15(\thread) 180 ldc1 $f17, THREAD_FPR17(\thread) 181 ldc1 $f19, THREAD_FPR19(\thread) 182 ldc1 $f21, THREAD_FPR21(\thread) 183 ldc1 $f23, THREAD_FPR23(\thread) 184 ldc1 $f25, THREAD_FPR25(\thread) 185 ldc1 $f27, THREAD_FPR27(\thread) 186 ldc1 $f29, THREAD_FPR29(\thread) 187 ldc1 $f31, THREAD_FPR31(\thread) 188 .set pop 189 .endm 190 191 .macro fpu_restore_double thread status tmp 192 #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPSR2) || \ 193 defined(CONFIG_CPU_MIPSR5) || defined(CONFIG_CPU_MIPSR6) 194 sll \tmp, \status, 5 195 bgez \tmp, 10f # 16 register mode? 196 197 fpu_restore_16odd \thread 198 10: 199 #endif 200 fpu_restore_16even \thread \tmp 201 .endm 202 203 #if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR5) || \ 204 defined(CONFIG_CPU_MIPSR6) 205 .macro _EXT rd, rs, p, s 206 ext \rd, \rs, \p, \s 207 .endm 208 #else /* !CONFIG_CPU_MIPSR2 && !CONFIG_CPU_MIPSR5 && !CONFIG_CPU_MIPSR6 */ 209 .macro _EXT rd, rs, p, s 210 srl \rd, \rs, \p 211 andi \rd, \rd, (1 << \s) - 1 212 .endm 213 #endif /* !CONFIG_CPU_MIPSR2 && !CONFIG_CPU_MIPSR5 && !CONFIG_CPU_MIPSR6 */ 214 215 /* 216 * Temporary until all gas have MT ASE support 217 */ 218 .macro DMT reg=0 219 .word 0x41600bc1 | (\reg << 16) 220 .endm 221 222 .macro EMT reg=0 223 .word 0x41600be1 | (\reg << 16) 224 .endm 225 226 .macro DVPE reg=0 227 .word 0x41600001 | (\reg << 16) 228 .endm 229 230 .macro EVPE reg=0 231 .word 0x41600021 | (\reg << 16) 232 .endm 233 234 .macro MFTR rt=0, rd=0, u=0, sel=0 235 .word 0x41000000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel) 236 .endm 237 238 .macro MTTR rt=0, rd=0, u=0, sel=0 239 .word 0x41800000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel) 240 .endm 241 242 #ifdef TOOLCHAIN_SUPPORTS_MSA 243 .macro _cfcmsa rd, cs 244 .set push 245 .set mips32r2 246 .set fp=64 247 .set msa 248 cfcmsa \rd, $\cs 249 .set pop 250 .endm 251 252 .macro _ctcmsa cd, rs 253 .set push 254 .set mips32r2 255 .set fp=64 256 .set msa 257 ctcmsa $\cd, \rs 258 .set pop 259 .endm 260 261 .macro ld_b wd, off, base 262 .set push 263 .set mips32r2 264 .set fp=64 265 .set msa 266 ld.b $w\wd, \off(\base) 267 .set pop 268 .endm 269 270 .macro ld_h wd, off, base 271 .set push 272 .set mips32r2 273 .set fp=64 274 .set msa 275 ld.h $w\wd, \off(\base) 276 .set pop 277 .endm 278 279 .macro ld_w wd, off, base 280 .set push 281 .set mips32r2 282 .set fp=64 283 .set msa 284 ld.w $w\wd, \off(\base) 285 .set pop 286 .endm 287 288 .macro ld_d wd, off, base 289 .set push 290 .set mips32r2 291 .set fp=64 292 .set msa 293 ld.d $w\wd, \off(\base) 294 .set pop 295 .endm 296 297 .macro st_b wd, off, base 298 .set push 299 .set mips32r2 300 .set fp=64 301 .set msa 302 st.b $w\wd, \off(\base) 303 .set pop 304 .endm 305 306 .macro st_h wd, off, base 307 .set push 308 .set mips32r2 309 .set fp=64 310 .set msa 311 st.h $w\wd, \off(\base) 312 .set pop 313 .endm 314 315 .macro st_w wd, off, base 316 .set push 317 .set mips32r2 318 .set fp=64 319 .set msa 320 st.w $w\wd, \off(\base) 321 .set pop 322 .endm 323 324 .macro st_d wd, off, base 325 .set push 326 .set mips32r2 327 .set fp=64 328 .set msa 329 st.d $w\wd, \off(\base) 330 .set pop 331 .endm 332 333 .macro copy_s_w ws, n 334 .set push 335 .set mips32r2 336 .set fp=64 337 .set msa 338 copy_s.w $1, $w\ws[\n] 339 .set pop 340 .endm 341 342 .macro copy_s_d ws, n 343 .set push 344 .set mips64r2 345 .set fp=64 346 .set msa 347 copy_s.d $1, $w\ws[\n] 348 .set pop 349 .endm 350 351 .macro insert_w wd, n 352 .set push 353 .set mips32r2 354 .set fp=64 355 .set msa 356 insert.w $w\wd[\n], $1 357 .set pop 358 .endm 359 360 .macro insert_d wd, n 361 .set push 362 .set mips64r2 363 .set fp=64 364 .set msa 365 insert.d $w\wd[\n], $1 366 .set pop 367 .endm 368 #else 369 370 /* 371 * Temporary until all toolchains in use include MSA support. 372 */ 373 .macro _cfcmsa rd, cs 374 .set push 375 .set noat 376 .set hardfloat 377 insn_if_mips 0x787e0059 | (\cs << 11) 378 insn32_if_mm 0x587e0056 | (\cs << 11) 379 move \rd, $1 380 .set pop 381 .endm 382 383 .macro _ctcmsa cd, rs 384 .set push 385 .set noat 386 .set hardfloat 387 move $1, \rs 388 insn_if_mips 0x783e0819 | (\cd << 6) 389 insn32_if_mm 0x583e0816 | (\cd << 6) 390 .set pop 391 .endm 392 393 .macro ld_b wd, off, base 394 .set push 395 .set noat 396 .set hardfloat 397 PTR_ADDU $1, \base, \off 398 insn_if_mips 0x78000820 | (\wd << 6) 399 insn32_if_mm 0x58000807 | (\wd << 6) 400 .set pop 401 .endm 402 403 .macro ld_h wd, off, base 404 .set push 405 .set noat 406 .set hardfloat 407 PTR_ADDU $1, \base, \off 408 insn_if_mips 0x78000821 | (\wd << 6) 409 insn32_if_mm 0x58000817 | (\wd << 6) 410 .set pop 411 .endm 412 413 .macro ld_w wd, off, base 414 .set push 415 .set noat 416 .set hardfloat 417 PTR_ADDU $1, \base, \off 418 insn_if_mips 0x78000822 | (\wd << 6) 419 insn32_if_mm 0x58000827 | (\wd << 6) 420 .set pop 421 .endm 422 423 .macro ld_d wd, off, base 424 .set push 425 .set noat 426 .set hardfloat 427 PTR_ADDU $1, \base, \off 428 insn_if_mips 0x78000823 | (\wd << 6) 429 insn32_if_mm 0x58000837 | (\wd << 6) 430 .set pop 431 .endm 432 433 .macro st_b wd, off, base 434 .set push 435 .set noat 436 .set hardfloat 437 PTR_ADDU $1, \base, \off 438 insn_if_mips 0x78000824 | (\wd << 6) 439 insn32_if_mm 0x5800080f | (\wd << 6) 440 .set pop 441 .endm 442 443 .macro st_h wd, off, base 444 .set push 445 .set noat 446 .set hardfloat 447 PTR_ADDU $1, \base, \off 448 insn_if_mips 0x78000825 | (\wd << 6) 449 insn32_if_mm 0x5800081f | (\wd << 6) 450 .set pop 451 .endm 452 453 .macro st_w wd, off, base 454 .set push 455 .set noat 456 .set hardfloat 457 PTR_ADDU $1, \base, \off 458 insn_if_mips 0x78000826 | (\wd << 6) 459 insn32_if_mm 0x5800082f | (\wd << 6) 460 .set pop 461 .endm 462 463 .macro st_d wd, off, base 464 .set push 465 .set noat 466 .set hardfloat 467 PTR_ADDU $1, \base, \off 468 insn_if_mips 0x78000827 | (\wd << 6) 469 insn32_if_mm 0x5800083f | (\wd << 6) 470 .set pop 471 .endm 472 473 .macro copy_s_w ws, n 474 .set push 475 .set noat 476 .set hardfloat 477 insn_if_mips 0x78b00059 | (\n << 16) | (\ws << 11) 478 insn32_if_mm 0x58b00056 | (\n << 16) | (\ws << 11) 479 .set pop 480 .endm 481 482 .macro copy_s_d ws, n 483 .set push 484 .set noat 485 .set hardfloat 486 insn_if_mips 0x78b80059 | (\n << 16) | (\ws << 11) 487 insn32_if_mm 0x58b80056 | (\n << 16) | (\ws << 11) 488 .set pop 489 .endm 490 491 .macro insert_w wd, n 492 .set push 493 .set noat 494 .set hardfloat 495 insn_if_mips 0x79300819 | (\n << 16) | (\wd << 6) 496 insn32_if_mm 0x59300816 | (\n << 16) | (\wd << 6) 497 .set pop 498 .endm 499 500 .macro insert_d wd, n 501 .set push 502 .set noat 503 .set hardfloat 504 insn_if_mips 0x79380819 | (\n << 16) | (\wd << 6) 505 insn32_if_mm 0x59380816 | (\n << 16) | (\wd << 6) 506 .set pop 507 .endm 508 #endif 509 510 #ifdef TOOLCHAIN_SUPPORTS_MSA 511 #define FPR_BASE_OFFS THREAD_FPR0 512 #define FPR_BASE $1 513 #else 514 #define FPR_BASE_OFFS 0 515 #define FPR_BASE \thread 516 #endif 517 518 .macro msa_save_all thread 519 .set push 520 .set noat 521 #ifdef TOOLCHAIN_SUPPORTS_MSA 522 PTR_ADDU FPR_BASE, \thread, FPR_BASE_OFFS 523 #endif 524 st_d 0, THREAD_FPR0 - FPR_BASE_OFFS, FPR_BASE 525 st_d 1, THREAD_FPR1 - FPR_BASE_OFFS, FPR_BASE 526 st_d 2, THREAD_FPR2 - FPR_BASE_OFFS, FPR_BASE 527 st_d 3, THREAD_FPR3 - FPR_BASE_OFFS, FPR_BASE 528 st_d 4, THREAD_FPR4 - FPR_BASE_OFFS, FPR_BASE 529 st_d 5, THREAD_FPR5 - FPR_BASE_OFFS, FPR_BASE 530 st_d 6, THREAD_FPR6 - FPR_BASE_OFFS, FPR_BASE 531 st_d 7, THREAD_FPR7 - FPR_BASE_OFFS, FPR_BASE 532 st_d 8, THREAD_FPR8 - FPR_BASE_OFFS, FPR_BASE 533 st_d 9, THREAD_FPR9 - FPR_BASE_OFFS, FPR_BASE 534 st_d 10, THREAD_FPR10 - FPR_BASE_OFFS, FPR_BASE 535 st_d 11, THREAD_FPR11 - FPR_BASE_OFFS, FPR_BASE 536 st_d 12, THREAD_FPR12 - FPR_BASE_OFFS, FPR_BASE 537 st_d 13, THREAD_FPR13 - FPR_BASE_OFFS, FPR_BASE 538 st_d 14, THREAD_FPR14 - FPR_BASE_OFFS, FPR_BASE 539 st_d 15, THREAD_FPR15 - FPR_BASE_OFFS, FPR_BASE 540 st_d 16, THREAD_FPR16 - FPR_BASE_OFFS, FPR_BASE 541 st_d 17, THREAD_FPR17 - FPR_BASE_OFFS, FPR_BASE 542 st_d 18, THREAD_FPR18 - FPR_BASE_OFFS, FPR_BASE 543 st_d 19, THREAD_FPR19 - FPR_BASE_OFFS, FPR_BASE 544 st_d 20, THREAD_FPR20 - FPR_BASE_OFFS, FPR_BASE 545 st_d 21, THREAD_FPR21 - FPR_BASE_OFFS, FPR_BASE 546 st_d 22, THREAD_FPR22 - FPR_BASE_OFFS, FPR_BASE 547 st_d 23, THREAD_FPR23 - FPR_BASE_OFFS, FPR_BASE 548 st_d 24, THREAD_FPR24 - FPR_BASE_OFFS, FPR_BASE 549 st_d 25, THREAD_FPR25 - FPR_BASE_OFFS, FPR_BASE 550 st_d 26, THREAD_FPR26 - FPR_BASE_OFFS, FPR_BASE 551 st_d 27, THREAD_FPR27 - FPR_BASE_OFFS, FPR_BASE 552 st_d 28, THREAD_FPR28 - FPR_BASE_OFFS, FPR_BASE 553 st_d 29, THREAD_FPR29 - FPR_BASE_OFFS, FPR_BASE 554 st_d 30, THREAD_FPR30 - FPR_BASE_OFFS, FPR_BASE 555 st_d 31, THREAD_FPR31 - FPR_BASE_OFFS, FPR_BASE 556 .set hardfloat 557 _cfcmsa $1, MSA_CSR 558 sw $1, THREAD_MSA_CSR(\thread) 559 .set pop 560 .endm 561 562 .macro msa_restore_all thread 563 .set push 564 .set noat 565 .set hardfloat 566 lw $1, THREAD_MSA_CSR(\thread) 567 _ctcmsa MSA_CSR, $1 568 #ifdef TOOLCHAIN_SUPPORTS_MSA 569 PTR_ADDU FPR_BASE, \thread, FPR_BASE_OFFS 570 #endif 571 ld_d 0, THREAD_FPR0 - FPR_BASE_OFFS, FPR_BASE 572 ld_d 1, THREAD_FPR1 - FPR_BASE_OFFS, FPR_BASE 573 ld_d 2, THREAD_FPR2 - FPR_BASE_OFFS, FPR_BASE 574 ld_d 3, THREAD_FPR3 - FPR_BASE_OFFS, FPR_BASE 575 ld_d 4, THREAD_FPR4 - FPR_BASE_OFFS, FPR_BASE 576 ld_d 5, THREAD_FPR5 - FPR_BASE_OFFS, FPR_BASE 577 ld_d 6, THREAD_FPR6 - FPR_BASE_OFFS, FPR_BASE 578 ld_d 7, THREAD_FPR7 - FPR_BASE_OFFS, FPR_BASE 579 ld_d 8, THREAD_FPR8 - FPR_BASE_OFFS, FPR_BASE 580 ld_d 9, THREAD_FPR9 - FPR_BASE_OFFS, FPR_BASE 581 ld_d 10, THREAD_FPR10 - FPR_BASE_OFFS, FPR_BASE 582 ld_d 11, THREAD_FPR11 - FPR_BASE_OFFS, FPR_BASE 583 ld_d 12, THREAD_FPR12 - FPR_BASE_OFFS, FPR_BASE 584 ld_d 13, THREAD_FPR13 - FPR_BASE_OFFS, FPR_BASE 585 ld_d 14, THREAD_FPR14 - FPR_BASE_OFFS, FPR_BASE 586 ld_d 15, THREAD_FPR15 - FPR_BASE_OFFS, FPR_BASE 587 ld_d 16, THREAD_FPR16 - FPR_BASE_OFFS, FPR_BASE 588 ld_d 17, THREAD_FPR17 - FPR_BASE_OFFS, FPR_BASE 589 ld_d 18, THREAD_FPR18 - FPR_BASE_OFFS, FPR_BASE 590 ld_d 19, THREAD_FPR19 - FPR_BASE_OFFS, FPR_BASE 591 ld_d 20, THREAD_FPR20 - FPR_BASE_OFFS, FPR_BASE 592 ld_d 21, THREAD_FPR21 - FPR_BASE_OFFS, FPR_BASE 593 ld_d 22, THREAD_FPR22 - FPR_BASE_OFFS, FPR_BASE 594 ld_d 23, THREAD_FPR23 - FPR_BASE_OFFS, FPR_BASE 595 ld_d 24, THREAD_FPR24 - FPR_BASE_OFFS, FPR_BASE 596 ld_d 25, THREAD_FPR25 - FPR_BASE_OFFS, FPR_BASE 597 ld_d 26, THREAD_FPR26 - FPR_BASE_OFFS, FPR_BASE 598 ld_d 27, THREAD_FPR27 - FPR_BASE_OFFS, FPR_BASE 599 ld_d 28, THREAD_FPR28 - FPR_BASE_OFFS, FPR_BASE 600 ld_d 29, THREAD_FPR29 - FPR_BASE_OFFS, FPR_BASE 601 ld_d 30, THREAD_FPR30 - FPR_BASE_OFFS, FPR_BASE 602 ld_d 31, THREAD_FPR31 - FPR_BASE_OFFS, FPR_BASE 603 .set pop 604 .endm 605 606 #undef FPR_BASE_OFFS 607 #undef FPR_BASE 608 609 .macro msa_init_upper wd 610 #ifdef CONFIG_64BIT 611 insert_d \wd, 1 612 #else 613 insert_w \wd, 2 614 insert_w \wd, 3 615 #endif 616 .endm 617 618 .macro msa_init_all_upper 619 .set push 620 .set noat 621 .set hardfloat 622 not $1, zero 623 msa_init_upper 0 624 msa_init_upper 1 625 msa_init_upper 2 626 msa_init_upper 3 627 msa_init_upper 4 628 msa_init_upper 5 629 msa_init_upper 6 630 msa_init_upper 7 631 msa_init_upper 8 632 msa_init_upper 9 633 msa_init_upper 10 634 msa_init_upper 11 635 msa_init_upper 12 636 msa_init_upper 13 637 msa_init_upper 14 638 msa_init_upper 15 639 msa_init_upper 16 640 msa_init_upper 17 641 msa_init_upper 18 642 msa_init_upper 19 643 msa_init_upper 20 644 msa_init_upper 21 645 msa_init_upper 22 646 msa_init_upper 23 647 msa_init_upper 24 648 msa_init_upper 25 649 msa_init_upper 26 650 msa_init_upper 27 651 msa_init_upper 28 652 msa_init_upper 29 653 msa_init_upper 30 654 msa_init_upper 31 655 .set pop 656 .endm 657 658 #endif /* _ASM_ASMMACRO_H */ 659