1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2003 Ralf Baechle 7 */ 8 #ifndef _ASM_ASMMACRO_H 9 #define _ASM_ASMMACRO_H 10 11 #include <asm/hazards.h> 12 13 #ifdef CONFIG_32BIT 14 #include <asm/asmmacro-32.h> 15 #endif 16 #ifdef CONFIG_64BIT 17 #include <asm/asmmacro-64.h> 18 #endif 19 #ifdef CONFIG_MIPS_MT_SMTC 20 #include <asm/mipsmtregs.h> 21 #endif 22 23 #ifdef CONFIG_MIPS_MT_SMTC 24 .macro local_irq_enable reg=t0 25 mfc0 \reg, CP0_TCSTATUS 26 ori \reg, \reg, TCSTATUS_IXMT 27 xori \reg, \reg, TCSTATUS_IXMT 28 mtc0 \reg, CP0_TCSTATUS 29 _ehb 30 .endm 31 32 .macro local_irq_disable reg=t0 33 mfc0 \reg, CP0_TCSTATUS 34 ori \reg, \reg, TCSTATUS_IXMT 35 mtc0 \reg, CP0_TCSTATUS 36 _ehb 37 .endm 38 #elif defined(CONFIG_CPU_MIPSR2) 39 .macro local_irq_enable reg=t0 40 ei 41 irq_enable_hazard 42 .endm 43 44 .macro local_irq_disable reg=t0 45 di 46 irq_disable_hazard 47 .endm 48 #else 49 .macro local_irq_enable reg=t0 50 mfc0 \reg, CP0_STATUS 51 ori \reg, \reg, 1 52 mtc0 \reg, CP0_STATUS 53 irq_enable_hazard 54 .endm 55 56 .macro local_irq_disable reg=t0 57 mfc0 \reg, CP0_STATUS 58 ori \reg, \reg, 1 59 xori \reg, \reg, 1 60 mtc0 \reg, CP0_STATUS 61 irq_disable_hazard 62 .endm 63 #endif /* CONFIG_MIPS_MT_SMTC */ 64 65 .macro fpu_save_16even thread tmp=t0 66 cfc1 \tmp, fcr31 67 sdc1 $f0, THREAD_FPR0(\thread) 68 sdc1 $f2, THREAD_FPR2(\thread) 69 sdc1 $f4, THREAD_FPR4(\thread) 70 sdc1 $f6, THREAD_FPR6(\thread) 71 sdc1 $f8, THREAD_FPR8(\thread) 72 sdc1 $f10, THREAD_FPR10(\thread) 73 sdc1 $f12, THREAD_FPR12(\thread) 74 sdc1 $f14, THREAD_FPR14(\thread) 75 sdc1 $f16, THREAD_FPR16(\thread) 76 sdc1 $f18, THREAD_FPR18(\thread) 77 sdc1 $f20, THREAD_FPR20(\thread) 78 sdc1 $f22, THREAD_FPR22(\thread) 79 sdc1 $f24, THREAD_FPR24(\thread) 80 sdc1 $f26, THREAD_FPR26(\thread) 81 sdc1 $f28, THREAD_FPR28(\thread) 82 sdc1 $f30, THREAD_FPR30(\thread) 83 sw \tmp, THREAD_FCR31(\thread) 84 .endm 85 86 .macro fpu_save_16odd thread 87 .set push 88 .set mips64r2 89 sdc1 $f1, THREAD_FPR1(\thread) 90 sdc1 $f3, THREAD_FPR3(\thread) 91 sdc1 $f5, THREAD_FPR5(\thread) 92 sdc1 $f7, THREAD_FPR7(\thread) 93 sdc1 $f9, THREAD_FPR9(\thread) 94 sdc1 $f11, THREAD_FPR11(\thread) 95 sdc1 $f13, THREAD_FPR13(\thread) 96 sdc1 $f15, THREAD_FPR15(\thread) 97 sdc1 $f17, THREAD_FPR17(\thread) 98 sdc1 $f19, THREAD_FPR19(\thread) 99 sdc1 $f21, THREAD_FPR21(\thread) 100 sdc1 $f23, THREAD_FPR23(\thread) 101 sdc1 $f25, THREAD_FPR25(\thread) 102 sdc1 $f27, THREAD_FPR27(\thread) 103 sdc1 $f29, THREAD_FPR29(\thread) 104 sdc1 $f31, THREAD_FPR31(\thread) 105 .set pop 106 .endm 107 108 .macro fpu_save_double thread status tmp 109 #if defined(CONFIG_MIPS64) || defined(CONFIG_CPU_MIPS32_R2) 110 sll \tmp, \status, 5 111 bgez \tmp, 10f 112 fpu_save_16odd \thread 113 10: 114 #endif 115 fpu_save_16even \thread \tmp 116 .endm 117 118 .macro fpu_restore_16even thread tmp=t0 119 lw \tmp, THREAD_FCR31(\thread) 120 ldc1 $f0, THREAD_FPR0(\thread) 121 ldc1 $f2, THREAD_FPR2(\thread) 122 ldc1 $f4, THREAD_FPR4(\thread) 123 ldc1 $f6, THREAD_FPR6(\thread) 124 ldc1 $f8, THREAD_FPR8(\thread) 125 ldc1 $f10, THREAD_FPR10(\thread) 126 ldc1 $f12, THREAD_FPR12(\thread) 127 ldc1 $f14, THREAD_FPR14(\thread) 128 ldc1 $f16, THREAD_FPR16(\thread) 129 ldc1 $f18, THREAD_FPR18(\thread) 130 ldc1 $f20, THREAD_FPR20(\thread) 131 ldc1 $f22, THREAD_FPR22(\thread) 132 ldc1 $f24, THREAD_FPR24(\thread) 133 ldc1 $f26, THREAD_FPR26(\thread) 134 ldc1 $f28, THREAD_FPR28(\thread) 135 ldc1 $f30, THREAD_FPR30(\thread) 136 ctc1 \tmp, fcr31 137 .endm 138 139 .macro fpu_restore_16odd thread 140 .set push 141 .set mips64r2 142 ldc1 $f1, THREAD_FPR1(\thread) 143 ldc1 $f3, THREAD_FPR3(\thread) 144 ldc1 $f5, THREAD_FPR5(\thread) 145 ldc1 $f7, THREAD_FPR7(\thread) 146 ldc1 $f9, THREAD_FPR9(\thread) 147 ldc1 $f11, THREAD_FPR11(\thread) 148 ldc1 $f13, THREAD_FPR13(\thread) 149 ldc1 $f15, THREAD_FPR15(\thread) 150 ldc1 $f17, THREAD_FPR17(\thread) 151 ldc1 $f19, THREAD_FPR19(\thread) 152 ldc1 $f21, THREAD_FPR21(\thread) 153 ldc1 $f23, THREAD_FPR23(\thread) 154 ldc1 $f25, THREAD_FPR25(\thread) 155 ldc1 $f27, THREAD_FPR27(\thread) 156 ldc1 $f29, THREAD_FPR29(\thread) 157 ldc1 $f31, THREAD_FPR31(\thread) 158 .set pop 159 .endm 160 161 .macro fpu_restore_double thread status tmp 162 #if defined(CONFIG_MIPS64) || defined(CONFIG_CPU_MIPS32_R2) 163 sll \tmp, \status, 5 164 bgez \tmp, 10f # 16 register mode? 165 166 fpu_restore_16odd \thread 167 10: 168 #endif 169 fpu_restore_16even \thread \tmp 170 .endm 171 172 /* 173 * Temporary until all gas have MT ASE support 174 */ 175 .macro DMT reg=0 176 .word 0x41600bc1 | (\reg << 16) 177 .endm 178 179 .macro EMT reg=0 180 .word 0x41600be1 | (\reg << 16) 181 .endm 182 183 .macro DVPE reg=0 184 .word 0x41600001 | (\reg << 16) 185 .endm 186 187 .macro EVPE reg=0 188 .word 0x41600021 | (\reg << 16) 189 .endm 190 191 .macro MFTR rt=0, rd=0, u=0, sel=0 192 .word 0x41000000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel) 193 .endm 194 195 .macro MTTR rt=0, rd=0, u=0, sel=0 196 .word 0x41800000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel) 197 .endm 198 199 #endif /* _ASM_ASMMACRO_H */ 200