1 /* 2 * System-specific setup, especially interrupts. 3 * 4 * This file is subject to the terms and conditions of the GNU General Public 5 * License. See the file "COPYING" in the main directory of this archive 6 * for more details. 7 * 8 * Copyright (C) 1998 Harald Koerfgen 9 * Copyright (C) 2000, 2001, 2002, 2003, 2005, 2020 Maciej W. Rozycki 10 */ 11 #include <linux/console.h> 12 #include <linux/export.h> 13 #include <linux/init.h> 14 #include <linux/interrupt.h> 15 #include <linux/ioport.h> 16 #include <linux/irq.h> 17 #include <linux/irqnr.h> 18 #include <linux/memblock.h> 19 #include <linux/param.h> 20 #include <linux/percpu-defs.h> 21 #include <linux/sched.h> 22 #include <linux/spinlock.h> 23 #include <linux/types.h> 24 #include <linux/pm.h> 25 26 #include <asm/addrspace.h> 27 #include <asm/bootinfo.h> 28 #include <asm/cpu.h> 29 #include <asm/cpu-features.h> 30 #include <asm/cpu-type.h> 31 #include <asm/irq.h> 32 #include <asm/irq_cpu.h> 33 #include <asm/mipsregs.h> 34 #include <asm/page.h> 35 #include <asm/reboot.h> 36 #include <asm/sections.h> 37 #include <asm/time.h> 38 #include <asm/traps.h> 39 #include <asm/wbflush.h> 40 41 #include <asm/dec/interrupts.h> 42 #include <asm/dec/ioasic.h> 43 #include <asm/dec/ioasic_addrs.h> 44 #include <asm/dec/ioasic_ints.h> 45 #include <asm/dec/kn01.h> 46 #include <asm/dec/kn02.h> 47 #include <asm/dec/kn02ba.h> 48 #include <asm/dec/kn02ca.h> 49 #include <asm/dec/kn03.h> 50 #include <asm/dec/kn230.h> 51 #include <asm/dec/system.h> 52 53 54 extern void dec_machine_restart(char *command); 55 extern void dec_machine_halt(void); 56 extern void dec_machine_power_off(void); 57 extern irqreturn_t dec_intr_halt(int irq, void *dev_id); 58 59 unsigned long dec_kn_slot_base, dec_kn_slot_size; 60 61 EXPORT_SYMBOL(dec_kn_slot_base); 62 EXPORT_SYMBOL(dec_kn_slot_size); 63 64 int dec_tc_bus; 65 66 DEFINE_SPINLOCK(ioasic_ssr_lock); 67 EXPORT_SYMBOL(ioasic_ssr_lock); 68 69 volatile u32 *ioasic_base; 70 71 EXPORT_SYMBOL(ioasic_base); 72 73 /* 74 * IRQ routing and priority tables. Priorities are set as follows: 75 * 76 * KN01 KN230 KN02 KN02-BA KN02-CA KN03 77 * 78 * MEMORY CPU CPU CPU ASIC CPU CPU 79 * RTC CPU CPU CPU ASIC CPU CPU 80 * DMA - - - ASIC ASIC ASIC 81 * SERIAL0 CPU CPU CSR ASIC ASIC ASIC 82 * SERIAL1 - - - ASIC - ASIC 83 * SCSI CPU CPU CSR ASIC ASIC ASIC 84 * ETHERNET CPU * CSR ASIC ASIC ASIC 85 * other - - - ASIC - - 86 * TC2 - - CSR CPU ASIC ASIC 87 * TC1 - - CSR CPU ASIC ASIC 88 * TC0 - - CSR CPU ASIC ASIC 89 * other - CPU - CPU ASIC ASIC 90 * other - - - - CPU CPU 91 * 92 * * -- shared with SCSI 93 */ 94 95 int dec_interrupt[DEC_NR_INTS] = { 96 [0 ... DEC_NR_INTS - 1] = -1 97 }; 98 99 EXPORT_SYMBOL(dec_interrupt); 100 101 int_ptr cpu_mask_nr_tbl[DEC_MAX_CPU_INTS][2] = { 102 { { .i = ~0 }, { .p = dec_intr_unimplemented } }, 103 }; 104 int_ptr asic_mask_nr_tbl[DEC_MAX_ASIC_INTS][2] = { 105 { { .i = ~0 }, { .p = asic_intr_unimplemented } }, 106 }; 107 int cpu_fpu_mask = DEC_CPU_IRQ_MASK(DEC_CPU_INR_FPU); 108 int *fpu_kstat_irq; 109 110 static irq_handler_t busirq_handler; 111 static unsigned int busirq_flags = IRQF_NO_THREAD; 112 113 /* 114 * Bus error (DBE/IBE exceptions and bus interrupts) handling setup. 115 */ 116 static void __init dec_be_init(void) 117 { 118 switch (mips_machtype) { 119 case MACH_DS23100: /* DS2100/DS3100 Pmin/Pmax */ 120 mips_set_be_handler(dec_kn01_be_handler); 121 busirq_handler = dec_kn01_be_interrupt; 122 busirq_flags |= IRQF_SHARED; 123 dec_kn01_be_init(); 124 break; 125 case MACH_DS5000_1XX: /* DS5000/1xx 3min */ 126 case MACH_DS5000_XX: /* DS5000/xx Maxine */ 127 mips_set_be_handler(dec_kn02xa_be_handler); 128 busirq_handler = dec_kn02xa_be_interrupt; 129 dec_kn02xa_be_init(); 130 break; 131 case MACH_DS5000_200: /* DS5000/200 3max */ 132 case MACH_DS5000_2X0: /* DS5000/240 3max+ */ 133 case MACH_DS5900: /* DS5900 bigmax */ 134 mips_set_be_handler(dec_ecc_be_handler); 135 busirq_handler = dec_ecc_be_interrupt; 136 dec_ecc_be_init(); 137 break; 138 } 139 } 140 141 void __init plat_mem_setup(void) 142 { 143 board_be_init = dec_be_init; 144 145 wbflush_setup(); 146 147 _machine_restart = dec_machine_restart; 148 _machine_halt = dec_machine_halt; 149 pm_power_off = dec_machine_power_off; 150 151 ioport_resource.start = ~0UL; 152 ioport_resource.end = 0UL; 153 154 /* Stay away from the firmware working memory area for now. */ 155 memblock_reserve(PHYS_OFFSET, __pa_symbol(&_text) - PHYS_OFFSET); 156 } 157 158 /* 159 * Machine-specific initialisation for KN01, aka DS2100 (aka Pmin) 160 * or DS3100 (aka Pmax). 161 */ 162 static int kn01_interrupt[DEC_NR_INTS] __initdata = { 163 [DEC_IRQ_CASCADE] = -1, 164 [DEC_IRQ_AB_RECV] = -1, 165 [DEC_IRQ_AB_XMIT] = -1, 166 [DEC_IRQ_DZ11] = DEC_CPU_IRQ_NR(KN01_CPU_INR_DZ11), 167 [DEC_IRQ_ASC] = -1, 168 [DEC_IRQ_FLOPPY] = -1, 169 [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU), 170 [DEC_IRQ_HALT] = -1, 171 [DEC_IRQ_ISDN] = -1, 172 [DEC_IRQ_LANCE] = DEC_CPU_IRQ_NR(KN01_CPU_INR_LANCE), 173 [DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN01_CPU_INR_BUS), 174 [DEC_IRQ_PSU] = -1, 175 [DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN01_CPU_INR_RTC), 176 [DEC_IRQ_SCC0] = -1, 177 [DEC_IRQ_SCC1] = -1, 178 [DEC_IRQ_SII] = DEC_CPU_IRQ_NR(KN01_CPU_INR_SII), 179 [DEC_IRQ_TC0] = -1, 180 [DEC_IRQ_TC1] = -1, 181 [DEC_IRQ_TC2] = -1, 182 [DEC_IRQ_TIMER] = -1, 183 [DEC_IRQ_VIDEO] = DEC_CPU_IRQ_NR(KN01_CPU_INR_VIDEO), 184 [DEC_IRQ_ASC_MERR] = -1, 185 [DEC_IRQ_ASC_ERR] = -1, 186 [DEC_IRQ_ASC_DMA] = -1, 187 [DEC_IRQ_FLOPPY_ERR] = -1, 188 [DEC_IRQ_ISDN_ERR] = -1, 189 [DEC_IRQ_ISDN_RXDMA] = -1, 190 [DEC_IRQ_ISDN_TXDMA] = -1, 191 [DEC_IRQ_LANCE_MERR] = -1, 192 [DEC_IRQ_SCC0A_RXERR] = -1, 193 [DEC_IRQ_SCC0A_RXDMA] = -1, 194 [DEC_IRQ_SCC0A_TXERR] = -1, 195 [DEC_IRQ_SCC0A_TXDMA] = -1, 196 [DEC_IRQ_AB_RXERR] = -1, 197 [DEC_IRQ_AB_RXDMA] = -1, 198 [DEC_IRQ_AB_TXERR] = -1, 199 [DEC_IRQ_AB_TXDMA] = -1, 200 [DEC_IRQ_SCC1A_RXERR] = -1, 201 [DEC_IRQ_SCC1A_RXDMA] = -1, 202 [DEC_IRQ_SCC1A_TXERR] = -1, 203 [DEC_IRQ_SCC1A_TXDMA] = -1, 204 }; 205 206 static int_ptr kn01_cpu_mask_nr_tbl[][2] __initdata = { 207 { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_BUS) }, 208 { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_BUS) } }, 209 { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_RTC) }, 210 { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_RTC) } }, 211 { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_DZ11) }, 212 { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_DZ11) } }, 213 { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_SII) }, 214 { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_SII) } }, 215 { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_LANCE) }, 216 { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_LANCE) } }, 217 { { .i = DEC_CPU_IRQ_ALL }, 218 { .p = cpu_all_int } }, 219 }; 220 221 static void __init dec_init_kn01(void) 222 { 223 /* IRQ routing. */ 224 memcpy(&dec_interrupt, &kn01_interrupt, 225 sizeof(kn01_interrupt)); 226 227 /* CPU IRQ priorities. */ 228 memcpy(&cpu_mask_nr_tbl, &kn01_cpu_mask_nr_tbl, 229 sizeof(kn01_cpu_mask_nr_tbl)); 230 231 mips_cpu_irq_init(); 232 233 } /* dec_init_kn01 */ 234 235 236 /* 237 * Machine-specific initialisation for KN230, aka DS5100, aka MIPSmate. 238 */ 239 static int kn230_interrupt[DEC_NR_INTS] __initdata = { 240 [DEC_IRQ_CASCADE] = -1, 241 [DEC_IRQ_AB_RECV] = -1, 242 [DEC_IRQ_AB_XMIT] = -1, 243 [DEC_IRQ_DZ11] = DEC_CPU_IRQ_NR(KN230_CPU_INR_DZ11), 244 [DEC_IRQ_ASC] = -1, 245 [DEC_IRQ_FLOPPY] = -1, 246 [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU), 247 [DEC_IRQ_HALT] = DEC_CPU_IRQ_NR(KN230_CPU_INR_HALT), 248 [DEC_IRQ_ISDN] = -1, 249 [DEC_IRQ_LANCE] = DEC_CPU_IRQ_NR(KN230_CPU_INR_LANCE), 250 [DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN230_CPU_INR_BUS), 251 [DEC_IRQ_PSU] = -1, 252 [DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN230_CPU_INR_RTC), 253 [DEC_IRQ_SCC0] = -1, 254 [DEC_IRQ_SCC1] = -1, 255 [DEC_IRQ_SII] = DEC_CPU_IRQ_NR(KN230_CPU_INR_SII), 256 [DEC_IRQ_TC0] = -1, 257 [DEC_IRQ_TC1] = -1, 258 [DEC_IRQ_TC2] = -1, 259 [DEC_IRQ_TIMER] = -1, 260 [DEC_IRQ_VIDEO] = -1, 261 [DEC_IRQ_ASC_MERR] = -1, 262 [DEC_IRQ_ASC_ERR] = -1, 263 [DEC_IRQ_ASC_DMA] = -1, 264 [DEC_IRQ_FLOPPY_ERR] = -1, 265 [DEC_IRQ_ISDN_ERR] = -1, 266 [DEC_IRQ_ISDN_RXDMA] = -1, 267 [DEC_IRQ_ISDN_TXDMA] = -1, 268 [DEC_IRQ_LANCE_MERR] = -1, 269 [DEC_IRQ_SCC0A_RXERR] = -1, 270 [DEC_IRQ_SCC0A_RXDMA] = -1, 271 [DEC_IRQ_SCC0A_TXERR] = -1, 272 [DEC_IRQ_SCC0A_TXDMA] = -1, 273 [DEC_IRQ_AB_RXERR] = -1, 274 [DEC_IRQ_AB_RXDMA] = -1, 275 [DEC_IRQ_AB_TXERR] = -1, 276 [DEC_IRQ_AB_TXDMA] = -1, 277 [DEC_IRQ_SCC1A_RXERR] = -1, 278 [DEC_IRQ_SCC1A_RXDMA] = -1, 279 [DEC_IRQ_SCC1A_TXERR] = -1, 280 [DEC_IRQ_SCC1A_TXDMA] = -1, 281 }; 282 283 static int_ptr kn230_cpu_mask_nr_tbl[][2] __initdata = { 284 { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_BUS) }, 285 { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_BUS) } }, 286 { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_RTC) }, 287 { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_RTC) } }, 288 { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_DZ11) }, 289 { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_DZ11) } }, 290 { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_SII) }, 291 { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_SII) } }, 292 { { .i = DEC_CPU_IRQ_ALL }, 293 { .p = cpu_all_int } }, 294 }; 295 296 static void __init dec_init_kn230(void) 297 { 298 /* IRQ routing. */ 299 memcpy(&dec_interrupt, &kn230_interrupt, 300 sizeof(kn230_interrupt)); 301 302 /* CPU IRQ priorities. */ 303 memcpy(&cpu_mask_nr_tbl, &kn230_cpu_mask_nr_tbl, 304 sizeof(kn230_cpu_mask_nr_tbl)); 305 306 mips_cpu_irq_init(); 307 308 } /* dec_init_kn230 */ 309 310 311 /* 312 * Machine-specific initialisation for KN02, aka DS5000/200, aka 3max. 313 */ 314 static int kn02_interrupt[DEC_NR_INTS] __initdata = { 315 [DEC_IRQ_CASCADE] = DEC_CPU_IRQ_NR(KN02_CPU_INR_CASCADE), 316 [DEC_IRQ_AB_RECV] = -1, 317 [DEC_IRQ_AB_XMIT] = -1, 318 [DEC_IRQ_DZ11] = KN02_IRQ_NR(KN02_CSR_INR_DZ11), 319 [DEC_IRQ_ASC] = KN02_IRQ_NR(KN02_CSR_INR_ASC), 320 [DEC_IRQ_FLOPPY] = -1, 321 [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU), 322 [DEC_IRQ_HALT] = -1, 323 [DEC_IRQ_ISDN] = -1, 324 [DEC_IRQ_LANCE] = KN02_IRQ_NR(KN02_CSR_INR_LANCE), 325 [DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN02_CPU_INR_BUS), 326 [DEC_IRQ_PSU] = -1, 327 [DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN02_CPU_INR_RTC), 328 [DEC_IRQ_SCC0] = -1, 329 [DEC_IRQ_SCC1] = -1, 330 [DEC_IRQ_SII] = -1, 331 [DEC_IRQ_TC0] = KN02_IRQ_NR(KN02_CSR_INR_TC0), 332 [DEC_IRQ_TC1] = KN02_IRQ_NR(KN02_CSR_INR_TC1), 333 [DEC_IRQ_TC2] = KN02_IRQ_NR(KN02_CSR_INR_TC2), 334 [DEC_IRQ_TIMER] = -1, 335 [DEC_IRQ_VIDEO] = -1, 336 [DEC_IRQ_ASC_MERR] = -1, 337 [DEC_IRQ_ASC_ERR] = -1, 338 [DEC_IRQ_ASC_DMA] = -1, 339 [DEC_IRQ_FLOPPY_ERR] = -1, 340 [DEC_IRQ_ISDN_ERR] = -1, 341 [DEC_IRQ_ISDN_RXDMA] = -1, 342 [DEC_IRQ_ISDN_TXDMA] = -1, 343 [DEC_IRQ_LANCE_MERR] = -1, 344 [DEC_IRQ_SCC0A_RXERR] = -1, 345 [DEC_IRQ_SCC0A_RXDMA] = -1, 346 [DEC_IRQ_SCC0A_TXERR] = -1, 347 [DEC_IRQ_SCC0A_TXDMA] = -1, 348 [DEC_IRQ_AB_RXERR] = -1, 349 [DEC_IRQ_AB_RXDMA] = -1, 350 [DEC_IRQ_AB_TXERR] = -1, 351 [DEC_IRQ_AB_TXDMA] = -1, 352 [DEC_IRQ_SCC1A_RXERR] = -1, 353 [DEC_IRQ_SCC1A_RXDMA] = -1, 354 [DEC_IRQ_SCC1A_TXERR] = -1, 355 [DEC_IRQ_SCC1A_TXDMA] = -1, 356 }; 357 358 static int_ptr kn02_cpu_mask_nr_tbl[][2] __initdata = { 359 { { .i = DEC_CPU_IRQ_MASK(KN02_CPU_INR_BUS) }, 360 { .i = DEC_CPU_IRQ_NR(KN02_CPU_INR_BUS) } }, 361 { { .i = DEC_CPU_IRQ_MASK(KN02_CPU_INR_RTC) }, 362 { .i = DEC_CPU_IRQ_NR(KN02_CPU_INR_RTC) } }, 363 { { .i = DEC_CPU_IRQ_MASK(KN02_CPU_INR_CASCADE) }, 364 { .p = kn02_io_int } }, 365 { { .i = DEC_CPU_IRQ_ALL }, 366 { .p = cpu_all_int } }, 367 }; 368 369 static int_ptr kn02_asic_mask_nr_tbl[][2] __initdata = { 370 { { .i = KN02_IRQ_MASK(KN02_CSR_INR_DZ11) }, 371 { .i = KN02_IRQ_NR(KN02_CSR_INR_DZ11) } }, 372 { { .i = KN02_IRQ_MASK(KN02_CSR_INR_ASC) }, 373 { .i = KN02_IRQ_NR(KN02_CSR_INR_ASC) } }, 374 { { .i = KN02_IRQ_MASK(KN02_CSR_INR_LANCE) }, 375 { .i = KN02_IRQ_NR(KN02_CSR_INR_LANCE) } }, 376 { { .i = KN02_IRQ_MASK(KN02_CSR_INR_TC2) }, 377 { .i = KN02_IRQ_NR(KN02_CSR_INR_TC2) } }, 378 { { .i = KN02_IRQ_MASK(KN02_CSR_INR_TC1) }, 379 { .i = KN02_IRQ_NR(KN02_CSR_INR_TC1) } }, 380 { { .i = KN02_IRQ_MASK(KN02_CSR_INR_TC0) }, 381 { .i = KN02_IRQ_NR(KN02_CSR_INR_TC0) } }, 382 { { .i = KN02_IRQ_ALL }, 383 { .p = kn02_all_int } }, 384 }; 385 386 static void __init dec_init_kn02(void) 387 { 388 /* IRQ routing. */ 389 memcpy(&dec_interrupt, &kn02_interrupt, 390 sizeof(kn02_interrupt)); 391 392 /* CPU IRQ priorities. */ 393 memcpy(&cpu_mask_nr_tbl, &kn02_cpu_mask_nr_tbl, 394 sizeof(kn02_cpu_mask_nr_tbl)); 395 396 /* KN02 CSR IRQ priorities. */ 397 memcpy(&asic_mask_nr_tbl, &kn02_asic_mask_nr_tbl, 398 sizeof(kn02_asic_mask_nr_tbl)); 399 400 mips_cpu_irq_init(); 401 init_kn02_irqs(KN02_IRQ_BASE); 402 403 } /* dec_init_kn02 */ 404 405 406 /* 407 * Machine-specific initialisation for KN02-BA, aka DS5000/1xx 408 * (xx = 20, 25, 33), aka 3min. Also applies to KN04(-BA), aka 409 * DS5000/150, aka 4min. 410 */ 411 static int kn02ba_interrupt[DEC_NR_INTS] __initdata = { 412 [DEC_IRQ_CASCADE] = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_CASCADE), 413 [DEC_IRQ_AB_RECV] = -1, 414 [DEC_IRQ_AB_XMIT] = -1, 415 [DEC_IRQ_DZ11] = -1, 416 [DEC_IRQ_ASC] = IO_IRQ_NR(KN02BA_IO_INR_ASC), 417 [DEC_IRQ_FLOPPY] = -1, 418 [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU), 419 [DEC_IRQ_HALT] = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_HALT), 420 [DEC_IRQ_ISDN] = -1, 421 [DEC_IRQ_LANCE] = IO_IRQ_NR(KN02BA_IO_INR_LANCE), 422 [DEC_IRQ_BUS] = IO_IRQ_NR(KN02BA_IO_INR_BUS), 423 [DEC_IRQ_PSU] = IO_IRQ_NR(KN02BA_IO_INR_PSU), 424 [DEC_IRQ_RTC] = IO_IRQ_NR(KN02BA_IO_INR_RTC), 425 [DEC_IRQ_SCC0] = IO_IRQ_NR(KN02BA_IO_INR_SCC0), 426 [DEC_IRQ_SCC1] = IO_IRQ_NR(KN02BA_IO_INR_SCC1), 427 [DEC_IRQ_SII] = -1, 428 [DEC_IRQ_TC0] = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC0), 429 [DEC_IRQ_TC1] = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC1), 430 [DEC_IRQ_TC2] = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC2), 431 [DEC_IRQ_TIMER] = -1, 432 [DEC_IRQ_VIDEO] = -1, 433 [DEC_IRQ_ASC_MERR] = IO_IRQ_NR(IO_INR_ASC_MERR), 434 [DEC_IRQ_ASC_ERR] = IO_IRQ_NR(IO_INR_ASC_ERR), 435 [DEC_IRQ_ASC_DMA] = IO_IRQ_NR(IO_INR_ASC_DMA), 436 [DEC_IRQ_FLOPPY_ERR] = -1, 437 [DEC_IRQ_ISDN_ERR] = -1, 438 [DEC_IRQ_ISDN_RXDMA] = -1, 439 [DEC_IRQ_ISDN_TXDMA] = -1, 440 [DEC_IRQ_LANCE_MERR] = IO_IRQ_NR(IO_INR_LANCE_MERR), 441 [DEC_IRQ_SCC0A_RXERR] = IO_IRQ_NR(IO_INR_SCC0A_RXERR), 442 [DEC_IRQ_SCC0A_RXDMA] = IO_IRQ_NR(IO_INR_SCC0A_RXDMA), 443 [DEC_IRQ_SCC0A_TXERR] = IO_IRQ_NR(IO_INR_SCC0A_TXERR), 444 [DEC_IRQ_SCC0A_TXDMA] = IO_IRQ_NR(IO_INR_SCC0A_TXDMA), 445 [DEC_IRQ_AB_RXERR] = -1, 446 [DEC_IRQ_AB_RXDMA] = -1, 447 [DEC_IRQ_AB_TXERR] = -1, 448 [DEC_IRQ_AB_TXDMA] = -1, 449 [DEC_IRQ_SCC1A_RXERR] = IO_IRQ_NR(IO_INR_SCC1A_RXERR), 450 [DEC_IRQ_SCC1A_RXDMA] = IO_IRQ_NR(IO_INR_SCC1A_RXDMA), 451 [DEC_IRQ_SCC1A_TXERR] = IO_IRQ_NR(IO_INR_SCC1A_TXERR), 452 [DEC_IRQ_SCC1A_TXDMA] = IO_IRQ_NR(IO_INR_SCC1A_TXDMA), 453 }; 454 455 static int_ptr kn02ba_cpu_mask_nr_tbl[][2] __initdata = { 456 { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_CASCADE) }, 457 { .p = kn02xa_io_int } }, 458 { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC2) }, 459 { .i = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC2) } }, 460 { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC1) }, 461 { .i = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC1) } }, 462 { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC0) }, 463 { .i = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC0) } }, 464 { { .i = DEC_CPU_IRQ_ALL }, 465 { .p = cpu_all_int } }, 466 }; 467 468 static int_ptr kn02ba_asic_mask_nr_tbl[][2] __initdata = { 469 { { .i = IO_IRQ_MASK(KN02BA_IO_INR_BUS) }, 470 { .i = IO_IRQ_NR(KN02BA_IO_INR_BUS) } }, 471 { { .i = IO_IRQ_MASK(KN02BA_IO_INR_RTC) }, 472 { .i = IO_IRQ_NR(KN02BA_IO_INR_RTC) } }, 473 { { .i = IO_IRQ_DMA }, 474 { .p = asic_dma_int } }, 475 { { .i = IO_IRQ_MASK(KN02BA_IO_INR_SCC0) }, 476 { .i = IO_IRQ_NR(KN02BA_IO_INR_SCC0) } }, 477 { { .i = IO_IRQ_MASK(KN02BA_IO_INR_SCC1) }, 478 { .i = IO_IRQ_NR(KN02BA_IO_INR_SCC1) } }, 479 { { .i = IO_IRQ_MASK(KN02BA_IO_INR_ASC) }, 480 { .i = IO_IRQ_NR(KN02BA_IO_INR_ASC) } }, 481 { { .i = IO_IRQ_MASK(KN02BA_IO_INR_LANCE) }, 482 { .i = IO_IRQ_NR(KN02BA_IO_INR_LANCE) } }, 483 { { .i = IO_IRQ_ALL }, 484 { .p = asic_all_int } }, 485 }; 486 487 static void __init dec_init_kn02ba(void) 488 { 489 /* IRQ routing. */ 490 memcpy(&dec_interrupt, &kn02ba_interrupt, 491 sizeof(kn02ba_interrupt)); 492 493 /* CPU IRQ priorities. */ 494 memcpy(&cpu_mask_nr_tbl, &kn02ba_cpu_mask_nr_tbl, 495 sizeof(kn02ba_cpu_mask_nr_tbl)); 496 497 /* I/O ASIC IRQ priorities. */ 498 memcpy(&asic_mask_nr_tbl, &kn02ba_asic_mask_nr_tbl, 499 sizeof(kn02ba_asic_mask_nr_tbl)); 500 501 mips_cpu_irq_init(); 502 init_ioasic_irqs(IO_IRQ_BASE); 503 504 } /* dec_init_kn02ba */ 505 506 507 /* 508 * Machine-specific initialisation for KN02-CA, aka DS5000/xx, 509 * (xx = 20, 25, 33), aka MAXine. Also applies to KN04(-CA), aka 510 * DS5000/50, aka 4MAXine. 511 */ 512 static int kn02ca_interrupt[DEC_NR_INTS] __initdata = { 513 [DEC_IRQ_CASCADE] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_CASCADE), 514 [DEC_IRQ_AB_RECV] = IO_IRQ_NR(KN02CA_IO_INR_AB_RECV), 515 [DEC_IRQ_AB_XMIT] = IO_IRQ_NR(KN02CA_IO_INR_AB_XMIT), 516 [DEC_IRQ_DZ11] = -1, 517 [DEC_IRQ_ASC] = IO_IRQ_NR(KN02CA_IO_INR_ASC), 518 [DEC_IRQ_FLOPPY] = IO_IRQ_NR(KN02CA_IO_INR_FLOPPY), 519 [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU), 520 [DEC_IRQ_HALT] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_HALT), 521 [DEC_IRQ_ISDN] = IO_IRQ_NR(KN02CA_IO_INR_ISDN), 522 [DEC_IRQ_LANCE] = IO_IRQ_NR(KN02CA_IO_INR_LANCE), 523 [DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_BUS), 524 [DEC_IRQ_PSU] = -1, 525 [DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_RTC), 526 [DEC_IRQ_SCC0] = IO_IRQ_NR(KN02CA_IO_INR_SCC0), 527 [DEC_IRQ_SCC1] = -1, 528 [DEC_IRQ_SII] = -1, 529 [DEC_IRQ_TC0] = IO_IRQ_NR(KN02CA_IO_INR_TC0), 530 [DEC_IRQ_TC1] = IO_IRQ_NR(KN02CA_IO_INR_TC1), 531 [DEC_IRQ_TC2] = -1, 532 [DEC_IRQ_TIMER] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_TIMER), 533 [DEC_IRQ_VIDEO] = IO_IRQ_NR(KN02CA_IO_INR_VIDEO), 534 [DEC_IRQ_ASC_MERR] = IO_IRQ_NR(IO_INR_ASC_MERR), 535 [DEC_IRQ_ASC_ERR] = IO_IRQ_NR(IO_INR_ASC_ERR), 536 [DEC_IRQ_ASC_DMA] = IO_IRQ_NR(IO_INR_ASC_DMA), 537 [DEC_IRQ_FLOPPY_ERR] = IO_IRQ_NR(IO_INR_FLOPPY_ERR), 538 [DEC_IRQ_ISDN_ERR] = IO_IRQ_NR(IO_INR_ISDN_ERR), 539 [DEC_IRQ_ISDN_RXDMA] = IO_IRQ_NR(IO_INR_ISDN_RXDMA), 540 [DEC_IRQ_ISDN_TXDMA] = IO_IRQ_NR(IO_INR_ISDN_TXDMA), 541 [DEC_IRQ_LANCE_MERR] = IO_IRQ_NR(IO_INR_LANCE_MERR), 542 [DEC_IRQ_SCC0A_RXERR] = IO_IRQ_NR(IO_INR_SCC0A_RXERR), 543 [DEC_IRQ_SCC0A_RXDMA] = IO_IRQ_NR(IO_INR_SCC0A_RXDMA), 544 [DEC_IRQ_SCC0A_TXERR] = IO_IRQ_NR(IO_INR_SCC0A_TXERR), 545 [DEC_IRQ_SCC0A_TXDMA] = IO_IRQ_NR(IO_INR_SCC0A_TXDMA), 546 [DEC_IRQ_AB_RXERR] = IO_IRQ_NR(IO_INR_AB_RXERR), 547 [DEC_IRQ_AB_RXDMA] = IO_IRQ_NR(IO_INR_AB_RXDMA), 548 [DEC_IRQ_AB_TXERR] = IO_IRQ_NR(IO_INR_AB_TXERR), 549 [DEC_IRQ_AB_TXDMA] = IO_IRQ_NR(IO_INR_AB_TXDMA), 550 [DEC_IRQ_SCC1A_RXERR] = -1, 551 [DEC_IRQ_SCC1A_RXDMA] = -1, 552 [DEC_IRQ_SCC1A_TXERR] = -1, 553 [DEC_IRQ_SCC1A_TXDMA] = -1, 554 }; 555 556 static int_ptr kn02ca_cpu_mask_nr_tbl[][2] __initdata = { 557 { { .i = DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_BUS) }, 558 { .i = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_BUS) } }, 559 { { .i = DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_RTC) }, 560 { .i = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_RTC) } }, 561 { { .i = DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_CASCADE) }, 562 { .p = kn02xa_io_int } }, 563 { { .i = DEC_CPU_IRQ_ALL }, 564 { .p = cpu_all_int } }, 565 }; 566 567 static int_ptr kn02ca_asic_mask_nr_tbl[][2] __initdata = { 568 { { .i = IO_IRQ_DMA }, 569 { .p = asic_dma_int } }, 570 { { .i = IO_IRQ_MASK(KN02CA_IO_INR_SCC0) }, 571 { .i = IO_IRQ_NR(KN02CA_IO_INR_SCC0) } }, 572 { { .i = IO_IRQ_MASK(KN02CA_IO_INR_ASC) }, 573 { .i = IO_IRQ_NR(KN02CA_IO_INR_ASC) } }, 574 { { .i = IO_IRQ_MASK(KN02CA_IO_INR_LANCE) }, 575 { .i = IO_IRQ_NR(KN02CA_IO_INR_LANCE) } }, 576 { { .i = IO_IRQ_MASK(KN02CA_IO_INR_TC1) }, 577 { .i = IO_IRQ_NR(KN02CA_IO_INR_TC1) } }, 578 { { .i = IO_IRQ_MASK(KN02CA_IO_INR_TC0) }, 579 { .i = IO_IRQ_NR(KN02CA_IO_INR_TC0) } }, 580 { { .i = IO_IRQ_ALL }, 581 { .p = asic_all_int } }, 582 }; 583 584 static void __init dec_init_kn02ca(void) 585 { 586 /* IRQ routing. */ 587 memcpy(&dec_interrupt, &kn02ca_interrupt, 588 sizeof(kn02ca_interrupt)); 589 590 /* CPU IRQ priorities. */ 591 memcpy(&cpu_mask_nr_tbl, &kn02ca_cpu_mask_nr_tbl, 592 sizeof(kn02ca_cpu_mask_nr_tbl)); 593 594 /* I/O ASIC IRQ priorities. */ 595 memcpy(&asic_mask_nr_tbl, &kn02ca_asic_mask_nr_tbl, 596 sizeof(kn02ca_asic_mask_nr_tbl)); 597 598 mips_cpu_irq_init(); 599 init_ioasic_irqs(IO_IRQ_BASE); 600 601 } /* dec_init_kn02ca */ 602 603 604 /* 605 * Machine-specific initialisation for KN03, aka DS5000/240, 606 * aka 3max+ and DS5900, aka BIGmax. Also applies to KN05, aka 607 * DS5000/260, aka 4max+ and DS5900/260. 608 */ 609 static int kn03_interrupt[DEC_NR_INTS] __initdata = { 610 [DEC_IRQ_CASCADE] = DEC_CPU_IRQ_NR(KN03_CPU_INR_CASCADE), 611 [DEC_IRQ_AB_RECV] = -1, 612 [DEC_IRQ_AB_XMIT] = -1, 613 [DEC_IRQ_DZ11] = -1, 614 [DEC_IRQ_ASC] = IO_IRQ_NR(KN03_IO_INR_ASC), 615 [DEC_IRQ_FLOPPY] = -1, 616 [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU), 617 [DEC_IRQ_HALT] = DEC_CPU_IRQ_NR(KN03_CPU_INR_HALT), 618 [DEC_IRQ_ISDN] = -1, 619 [DEC_IRQ_LANCE] = IO_IRQ_NR(KN03_IO_INR_LANCE), 620 [DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN03_CPU_INR_BUS), 621 [DEC_IRQ_PSU] = IO_IRQ_NR(KN03_IO_INR_PSU), 622 [DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN03_CPU_INR_RTC), 623 [DEC_IRQ_SCC0] = IO_IRQ_NR(KN03_IO_INR_SCC0), 624 [DEC_IRQ_SCC1] = IO_IRQ_NR(KN03_IO_INR_SCC1), 625 [DEC_IRQ_SII] = -1, 626 [DEC_IRQ_TC0] = IO_IRQ_NR(KN03_IO_INR_TC0), 627 [DEC_IRQ_TC1] = IO_IRQ_NR(KN03_IO_INR_TC1), 628 [DEC_IRQ_TC2] = IO_IRQ_NR(KN03_IO_INR_TC2), 629 [DEC_IRQ_TIMER] = -1, 630 [DEC_IRQ_VIDEO] = -1, 631 [DEC_IRQ_ASC_MERR] = IO_IRQ_NR(IO_INR_ASC_MERR), 632 [DEC_IRQ_ASC_ERR] = IO_IRQ_NR(IO_INR_ASC_ERR), 633 [DEC_IRQ_ASC_DMA] = IO_IRQ_NR(IO_INR_ASC_DMA), 634 [DEC_IRQ_FLOPPY_ERR] = -1, 635 [DEC_IRQ_ISDN_ERR] = -1, 636 [DEC_IRQ_ISDN_RXDMA] = -1, 637 [DEC_IRQ_ISDN_TXDMA] = -1, 638 [DEC_IRQ_LANCE_MERR] = IO_IRQ_NR(IO_INR_LANCE_MERR), 639 [DEC_IRQ_SCC0A_RXERR] = IO_IRQ_NR(IO_INR_SCC0A_RXERR), 640 [DEC_IRQ_SCC0A_RXDMA] = IO_IRQ_NR(IO_INR_SCC0A_RXDMA), 641 [DEC_IRQ_SCC0A_TXERR] = IO_IRQ_NR(IO_INR_SCC0A_TXERR), 642 [DEC_IRQ_SCC0A_TXDMA] = IO_IRQ_NR(IO_INR_SCC0A_TXDMA), 643 [DEC_IRQ_AB_RXERR] = -1, 644 [DEC_IRQ_AB_RXDMA] = -1, 645 [DEC_IRQ_AB_TXERR] = -1, 646 [DEC_IRQ_AB_TXDMA] = -1, 647 [DEC_IRQ_SCC1A_RXERR] = IO_IRQ_NR(IO_INR_SCC1A_RXERR), 648 [DEC_IRQ_SCC1A_RXDMA] = IO_IRQ_NR(IO_INR_SCC1A_RXDMA), 649 [DEC_IRQ_SCC1A_TXERR] = IO_IRQ_NR(IO_INR_SCC1A_TXERR), 650 [DEC_IRQ_SCC1A_TXDMA] = IO_IRQ_NR(IO_INR_SCC1A_TXDMA), 651 }; 652 653 static int_ptr kn03_cpu_mask_nr_tbl[][2] __initdata = { 654 { { .i = DEC_CPU_IRQ_MASK(KN03_CPU_INR_BUS) }, 655 { .i = DEC_CPU_IRQ_NR(KN03_CPU_INR_BUS) } }, 656 { { .i = DEC_CPU_IRQ_MASK(KN03_CPU_INR_RTC) }, 657 { .i = DEC_CPU_IRQ_NR(KN03_CPU_INR_RTC) } }, 658 { { .i = DEC_CPU_IRQ_MASK(KN03_CPU_INR_CASCADE) }, 659 { .p = kn03_io_int } }, 660 { { .i = DEC_CPU_IRQ_ALL }, 661 { .p = cpu_all_int } }, 662 }; 663 664 static int_ptr kn03_asic_mask_nr_tbl[][2] __initdata = { 665 { { .i = IO_IRQ_DMA }, 666 { .p = asic_dma_int } }, 667 { { .i = IO_IRQ_MASK(KN03_IO_INR_SCC0) }, 668 { .i = IO_IRQ_NR(KN03_IO_INR_SCC0) } }, 669 { { .i = IO_IRQ_MASK(KN03_IO_INR_SCC1) }, 670 { .i = IO_IRQ_NR(KN03_IO_INR_SCC1) } }, 671 { { .i = IO_IRQ_MASK(KN03_IO_INR_ASC) }, 672 { .i = IO_IRQ_NR(KN03_IO_INR_ASC) } }, 673 { { .i = IO_IRQ_MASK(KN03_IO_INR_LANCE) }, 674 { .i = IO_IRQ_NR(KN03_IO_INR_LANCE) } }, 675 { { .i = IO_IRQ_MASK(KN03_IO_INR_TC2) }, 676 { .i = IO_IRQ_NR(KN03_IO_INR_TC2) } }, 677 { { .i = IO_IRQ_MASK(KN03_IO_INR_TC1) }, 678 { .i = IO_IRQ_NR(KN03_IO_INR_TC1) } }, 679 { { .i = IO_IRQ_MASK(KN03_IO_INR_TC0) }, 680 { .i = IO_IRQ_NR(KN03_IO_INR_TC0) } }, 681 { { .i = IO_IRQ_ALL }, 682 { .p = asic_all_int } }, 683 }; 684 685 static void __init dec_init_kn03(void) 686 { 687 /* IRQ routing. */ 688 memcpy(&dec_interrupt, &kn03_interrupt, 689 sizeof(kn03_interrupt)); 690 691 /* CPU IRQ priorities. */ 692 memcpy(&cpu_mask_nr_tbl, &kn03_cpu_mask_nr_tbl, 693 sizeof(kn03_cpu_mask_nr_tbl)); 694 695 /* I/O ASIC IRQ priorities. */ 696 memcpy(&asic_mask_nr_tbl, &kn03_asic_mask_nr_tbl, 697 sizeof(kn03_asic_mask_nr_tbl)); 698 699 mips_cpu_irq_init(); 700 init_ioasic_irqs(IO_IRQ_BASE); 701 702 } /* dec_init_kn03 */ 703 704 705 void __init arch_init_irq(void) 706 { 707 switch (mips_machtype) { 708 case MACH_DS23100: /* DS2100/DS3100 Pmin/Pmax */ 709 dec_init_kn01(); 710 break; 711 case MACH_DS5100: /* DS5100 MIPSmate */ 712 dec_init_kn230(); 713 break; 714 case MACH_DS5000_200: /* DS5000/200 3max */ 715 dec_init_kn02(); 716 break; 717 case MACH_DS5000_1XX: /* DS5000/1xx 3min */ 718 dec_init_kn02ba(); 719 break; 720 case MACH_DS5000_2X0: /* DS5000/240 3max+ */ 721 case MACH_DS5900: /* DS5900 bigmax */ 722 dec_init_kn03(); 723 break; 724 case MACH_DS5000_XX: /* Personal DS5000/xx */ 725 dec_init_kn02ca(); 726 break; 727 case MACH_DS5800: /* DS5800 Isis */ 728 panic("Don't know how to set this up!"); 729 break; 730 case MACH_DS5400: /* DS5400 MIPSfair */ 731 panic("Don't know how to set this up!"); 732 break; 733 case MACH_DS5500: /* DS5500 MIPSfair-2 */ 734 panic("Don't know how to set this up!"); 735 break; 736 } 737 738 /* Free the FPU interrupt if the exception is present. */ 739 if (!cpu_has_nofpuex) { 740 cpu_fpu_mask = 0; 741 dec_interrupt[DEC_IRQ_FPU] = -1; 742 } 743 /* Free the halt interrupt unused on R4k systems. */ 744 if (current_cpu_type() == CPU_R4000SC || 745 current_cpu_type() == CPU_R4400SC) 746 dec_interrupt[DEC_IRQ_HALT] = -1; 747 748 /* Register board interrupts: FPU and cascade. */ 749 if (IS_ENABLED(CONFIG_MIPS_FP_SUPPORT) && 750 dec_interrupt[DEC_IRQ_FPU] >= 0 && cpu_has_fpu) { 751 struct irq_desc *desc_fpu; 752 int irq_fpu; 753 754 irq_fpu = dec_interrupt[DEC_IRQ_FPU]; 755 if (request_irq(irq_fpu, no_action, IRQF_NO_THREAD, "fpu", 756 NULL)) 757 pr_err("Failed to register fpu interrupt\n"); 758 desc_fpu = irq_to_desc(irq_fpu); 759 fpu_kstat_irq = this_cpu_ptr(desc_fpu->kstat_irqs); 760 } 761 if (dec_interrupt[DEC_IRQ_CASCADE] >= 0) { 762 if (request_irq(dec_interrupt[DEC_IRQ_CASCADE], no_action, 763 IRQF_NO_THREAD, "cascade", NULL)) 764 pr_err("Failed to register cascade interrupt\n"); 765 } 766 /* Register the bus error interrupt. */ 767 if (dec_interrupt[DEC_IRQ_BUS] >= 0 && busirq_handler) { 768 if (request_irq(dec_interrupt[DEC_IRQ_BUS], busirq_handler, 769 busirq_flags, "bus error", busirq_handler)) 770 pr_err("Failed to register bus error interrupt\n"); 771 } 772 /* Register the HALT interrupt. */ 773 if (dec_interrupt[DEC_IRQ_HALT] >= 0) { 774 if (request_irq(dec_interrupt[DEC_IRQ_HALT], dec_intr_halt, 775 IRQF_NO_THREAD, "halt", NULL)) 776 pr_err("Failed to register halt interrupt\n"); 777 } 778 } 779 780 asmlinkage unsigned int dec_irq_dispatch(unsigned int irq) 781 { 782 do_IRQ(irq); 783 return 0; 784 } 785