1 /* 2 * System-specific setup, especially interrupts. 3 * 4 * This file is subject to the terms and conditions of the GNU General Public 5 * License. See the file "COPYING" in the main directory of this archive 6 * for more details. 7 * 8 * Copyright (C) 1998 Harald Koerfgen 9 * Copyright (C) 2000, 2001, 2002, 2003, 2005 Maciej W. Rozycki 10 */ 11 #include <linux/console.h> 12 #include <linux/export.h> 13 #include <linux/init.h> 14 #include <linux/interrupt.h> 15 #include <linux/ioport.h> 16 #include <linux/irq.h> 17 #include <linux/irqnr.h> 18 #include <linux/param.h> 19 #include <linux/percpu-defs.h> 20 #include <linux/sched.h> 21 #include <linux/spinlock.h> 22 #include <linux/types.h> 23 #include <linux/pm.h> 24 25 #include <asm/bootinfo.h> 26 #include <asm/cpu.h> 27 #include <asm/cpu-features.h> 28 #include <asm/cpu-type.h> 29 #include <asm/irq.h> 30 #include <asm/irq_cpu.h> 31 #include <asm/mipsregs.h> 32 #include <asm/reboot.h> 33 #include <asm/time.h> 34 #include <asm/traps.h> 35 #include <asm/wbflush.h> 36 37 #include <asm/dec/interrupts.h> 38 #include <asm/dec/ioasic.h> 39 #include <asm/dec/ioasic_addrs.h> 40 #include <asm/dec/ioasic_ints.h> 41 #include <asm/dec/kn01.h> 42 #include <asm/dec/kn02.h> 43 #include <asm/dec/kn02ba.h> 44 #include <asm/dec/kn02ca.h> 45 #include <asm/dec/kn03.h> 46 #include <asm/dec/kn230.h> 47 #include <asm/dec/system.h> 48 49 50 extern void dec_machine_restart(char *command); 51 extern void dec_machine_halt(void); 52 extern void dec_machine_power_off(void); 53 extern irqreturn_t dec_intr_halt(int irq, void *dev_id); 54 55 unsigned long dec_kn_slot_base, dec_kn_slot_size; 56 57 EXPORT_SYMBOL(dec_kn_slot_base); 58 EXPORT_SYMBOL(dec_kn_slot_size); 59 60 int dec_tc_bus; 61 62 DEFINE_SPINLOCK(ioasic_ssr_lock); 63 EXPORT_SYMBOL(ioasic_ssr_lock); 64 65 volatile u32 *ioasic_base; 66 67 EXPORT_SYMBOL(ioasic_base); 68 69 /* 70 * IRQ routing and priority tables. Priorites are set as follows: 71 * 72 * KN01 KN230 KN02 KN02-BA KN02-CA KN03 73 * 74 * MEMORY CPU CPU CPU ASIC CPU CPU 75 * RTC CPU CPU CPU ASIC CPU CPU 76 * DMA - - - ASIC ASIC ASIC 77 * SERIAL0 CPU CPU CSR ASIC ASIC ASIC 78 * SERIAL1 - - - ASIC - ASIC 79 * SCSI CPU CPU CSR ASIC ASIC ASIC 80 * ETHERNET CPU * CSR ASIC ASIC ASIC 81 * other - - - ASIC - - 82 * TC2 - - CSR CPU ASIC ASIC 83 * TC1 - - CSR CPU ASIC ASIC 84 * TC0 - - CSR CPU ASIC ASIC 85 * other - CPU - CPU ASIC ASIC 86 * other - - - - CPU CPU 87 * 88 * * -- shared with SCSI 89 */ 90 91 int dec_interrupt[DEC_NR_INTS] = { 92 [0 ... DEC_NR_INTS - 1] = -1 93 }; 94 95 EXPORT_SYMBOL(dec_interrupt); 96 97 int_ptr cpu_mask_nr_tbl[DEC_MAX_CPU_INTS][2] = { 98 { { .i = ~0 }, { .p = dec_intr_unimplemented } }, 99 }; 100 int_ptr asic_mask_nr_tbl[DEC_MAX_ASIC_INTS][2] = { 101 { { .i = ~0 }, { .p = asic_intr_unimplemented } }, 102 }; 103 int cpu_fpu_mask = DEC_CPU_IRQ_MASK(DEC_CPU_INR_FPU); 104 int *fpu_kstat_irq; 105 106 static irq_handler_t busirq_handler; 107 static unsigned int busirq_flags = IRQF_NO_THREAD; 108 109 /* 110 * Bus error (DBE/IBE exceptions and bus interrupts) handling setup. 111 */ 112 static void __init dec_be_init(void) 113 { 114 switch (mips_machtype) { 115 case MACH_DS23100: /* DS2100/DS3100 Pmin/Pmax */ 116 board_be_handler = dec_kn01_be_handler; 117 busirq_handler = dec_kn01_be_interrupt; 118 busirq_flags |= IRQF_SHARED; 119 dec_kn01_be_init(); 120 break; 121 case MACH_DS5000_1XX: /* DS5000/1xx 3min */ 122 case MACH_DS5000_XX: /* DS5000/xx Maxine */ 123 board_be_handler = dec_kn02xa_be_handler; 124 busirq_handler = dec_kn02xa_be_interrupt; 125 dec_kn02xa_be_init(); 126 break; 127 case MACH_DS5000_200: /* DS5000/200 3max */ 128 case MACH_DS5000_2X0: /* DS5000/240 3max+ */ 129 case MACH_DS5900: /* DS5900 bigmax */ 130 board_be_handler = dec_ecc_be_handler; 131 busirq_handler = dec_ecc_be_interrupt; 132 dec_ecc_be_init(); 133 break; 134 } 135 } 136 137 void __init plat_mem_setup(void) 138 { 139 board_be_init = dec_be_init; 140 141 wbflush_setup(); 142 143 _machine_restart = dec_machine_restart; 144 _machine_halt = dec_machine_halt; 145 pm_power_off = dec_machine_power_off; 146 147 ioport_resource.start = ~0UL; 148 ioport_resource.end = 0UL; 149 } 150 151 /* 152 * Machine-specific initialisation for KN01, aka DS2100 (aka Pmin) 153 * or DS3100 (aka Pmax). 154 */ 155 static int kn01_interrupt[DEC_NR_INTS] __initdata = { 156 [DEC_IRQ_CASCADE] = -1, 157 [DEC_IRQ_AB_RECV] = -1, 158 [DEC_IRQ_AB_XMIT] = -1, 159 [DEC_IRQ_DZ11] = DEC_CPU_IRQ_NR(KN01_CPU_INR_DZ11), 160 [DEC_IRQ_ASC] = -1, 161 [DEC_IRQ_FLOPPY] = -1, 162 [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU), 163 [DEC_IRQ_HALT] = -1, 164 [DEC_IRQ_ISDN] = -1, 165 [DEC_IRQ_LANCE] = DEC_CPU_IRQ_NR(KN01_CPU_INR_LANCE), 166 [DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN01_CPU_INR_BUS), 167 [DEC_IRQ_PSU] = -1, 168 [DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN01_CPU_INR_RTC), 169 [DEC_IRQ_SCC0] = -1, 170 [DEC_IRQ_SCC1] = -1, 171 [DEC_IRQ_SII] = DEC_CPU_IRQ_NR(KN01_CPU_INR_SII), 172 [DEC_IRQ_TC0] = -1, 173 [DEC_IRQ_TC1] = -1, 174 [DEC_IRQ_TC2] = -1, 175 [DEC_IRQ_TIMER] = -1, 176 [DEC_IRQ_VIDEO] = DEC_CPU_IRQ_NR(KN01_CPU_INR_VIDEO), 177 [DEC_IRQ_ASC_MERR] = -1, 178 [DEC_IRQ_ASC_ERR] = -1, 179 [DEC_IRQ_ASC_DMA] = -1, 180 [DEC_IRQ_FLOPPY_ERR] = -1, 181 [DEC_IRQ_ISDN_ERR] = -1, 182 [DEC_IRQ_ISDN_RXDMA] = -1, 183 [DEC_IRQ_ISDN_TXDMA] = -1, 184 [DEC_IRQ_LANCE_MERR] = -1, 185 [DEC_IRQ_SCC0A_RXERR] = -1, 186 [DEC_IRQ_SCC0A_RXDMA] = -1, 187 [DEC_IRQ_SCC0A_TXERR] = -1, 188 [DEC_IRQ_SCC0A_TXDMA] = -1, 189 [DEC_IRQ_AB_RXERR] = -1, 190 [DEC_IRQ_AB_RXDMA] = -1, 191 [DEC_IRQ_AB_TXERR] = -1, 192 [DEC_IRQ_AB_TXDMA] = -1, 193 [DEC_IRQ_SCC1A_RXERR] = -1, 194 [DEC_IRQ_SCC1A_RXDMA] = -1, 195 [DEC_IRQ_SCC1A_TXERR] = -1, 196 [DEC_IRQ_SCC1A_TXDMA] = -1, 197 }; 198 199 static int_ptr kn01_cpu_mask_nr_tbl[][2] __initdata = { 200 { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_BUS) }, 201 { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_BUS) } }, 202 { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_RTC) }, 203 { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_RTC) } }, 204 { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_DZ11) }, 205 { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_DZ11) } }, 206 { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_SII) }, 207 { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_SII) } }, 208 { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_LANCE) }, 209 { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_LANCE) } }, 210 { { .i = DEC_CPU_IRQ_ALL }, 211 { .p = cpu_all_int } }, 212 }; 213 214 static void __init dec_init_kn01(void) 215 { 216 /* IRQ routing. */ 217 memcpy(&dec_interrupt, &kn01_interrupt, 218 sizeof(kn01_interrupt)); 219 220 /* CPU IRQ priorities. */ 221 memcpy(&cpu_mask_nr_tbl, &kn01_cpu_mask_nr_tbl, 222 sizeof(kn01_cpu_mask_nr_tbl)); 223 224 mips_cpu_irq_init(); 225 226 } /* dec_init_kn01 */ 227 228 229 /* 230 * Machine-specific initialisation for KN230, aka DS5100, aka MIPSmate. 231 */ 232 static int kn230_interrupt[DEC_NR_INTS] __initdata = { 233 [DEC_IRQ_CASCADE] = -1, 234 [DEC_IRQ_AB_RECV] = -1, 235 [DEC_IRQ_AB_XMIT] = -1, 236 [DEC_IRQ_DZ11] = DEC_CPU_IRQ_NR(KN230_CPU_INR_DZ11), 237 [DEC_IRQ_ASC] = -1, 238 [DEC_IRQ_FLOPPY] = -1, 239 [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU), 240 [DEC_IRQ_HALT] = DEC_CPU_IRQ_NR(KN230_CPU_INR_HALT), 241 [DEC_IRQ_ISDN] = -1, 242 [DEC_IRQ_LANCE] = DEC_CPU_IRQ_NR(KN230_CPU_INR_LANCE), 243 [DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN230_CPU_INR_BUS), 244 [DEC_IRQ_PSU] = -1, 245 [DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN230_CPU_INR_RTC), 246 [DEC_IRQ_SCC0] = -1, 247 [DEC_IRQ_SCC1] = -1, 248 [DEC_IRQ_SII] = DEC_CPU_IRQ_NR(KN230_CPU_INR_SII), 249 [DEC_IRQ_TC0] = -1, 250 [DEC_IRQ_TC1] = -1, 251 [DEC_IRQ_TC2] = -1, 252 [DEC_IRQ_TIMER] = -1, 253 [DEC_IRQ_VIDEO] = -1, 254 [DEC_IRQ_ASC_MERR] = -1, 255 [DEC_IRQ_ASC_ERR] = -1, 256 [DEC_IRQ_ASC_DMA] = -1, 257 [DEC_IRQ_FLOPPY_ERR] = -1, 258 [DEC_IRQ_ISDN_ERR] = -1, 259 [DEC_IRQ_ISDN_RXDMA] = -1, 260 [DEC_IRQ_ISDN_TXDMA] = -1, 261 [DEC_IRQ_LANCE_MERR] = -1, 262 [DEC_IRQ_SCC0A_RXERR] = -1, 263 [DEC_IRQ_SCC0A_RXDMA] = -1, 264 [DEC_IRQ_SCC0A_TXERR] = -1, 265 [DEC_IRQ_SCC0A_TXDMA] = -1, 266 [DEC_IRQ_AB_RXERR] = -1, 267 [DEC_IRQ_AB_RXDMA] = -1, 268 [DEC_IRQ_AB_TXERR] = -1, 269 [DEC_IRQ_AB_TXDMA] = -1, 270 [DEC_IRQ_SCC1A_RXERR] = -1, 271 [DEC_IRQ_SCC1A_RXDMA] = -1, 272 [DEC_IRQ_SCC1A_TXERR] = -1, 273 [DEC_IRQ_SCC1A_TXDMA] = -1, 274 }; 275 276 static int_ptr kn230_cpu_mask_nr_tbl[][2] __initdata = { 277 { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_BUS) }, 278 { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_BUS) } }, 279 { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_RTC) }, 280 { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_RTC) } }, 281 { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_DZ11) }, 282 { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_DZ11) } }, 283 { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_SII) }, 284 { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_SII) } }, 285 { { .i = DEC_CPU_IRQ_ALL }, 286 { .p = cpu_all_int } }, 287 }; 288 289 static void __init dec_init_kn230(void) 290 { 291 /* IRQ routing. */ 292 memcpy(&dec_interrupt, &kn230_interrupt, 293 sizeof(kn230_interrupt)); 294 295 /* CPU IRQ priorities. */ 296 memcpy(&cpu_mask_nr_tbl, &kn230_cpu_mask_nr_tbl, 297 sizeof(kn230_cpu_mask_nr_tbl)); 298 299 mips_cpu_irq_init(); 300 301 } /* dec_init_kn230 */ 302 303 304 /* 305 * Machine-specific initialisation for KN02, aka DS5000/200, aka 3max. 306 */ 307 static int kn02_interrupt[DEC_NR_INTS] __initdata = { 308 [DEC_IRQ_CASCADE] = DEC_CPU_IRQ_NR(KN02_CPU_INR_CASCADE), 309 [DEC_IRQ_AB_RECV] = -1, 310 [DEC_IRQ_AB_XMIT] = -1, 311 [DEC_IRQ_DZ11] = KN02_IRQ_NR(KN02_CSR_INR_DZ11), 312 [DEC_IRQ_ASC] = KN02_IRQ_NR(KN02_CSR_INR_ASC), 313 [DEC_IRQ_FLOPPY] = -1, 314 [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU), 315 [DEC_IRQ_HALT] = -1, 316 [DEC_IRQ_ISDN] = -1, 317 [DEC_IRQ_LANCE] = KN02_IRQ_NR(KN02_CSR_INR_LANCE), 318 [DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN02_CPU_INR_BUS), 319 [DEC_IRQ_PSU] = -1, 320 [DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN02_CPU_INR_RTC), 321 [DEC_IRQ_SCC0] = -1, 322 [DEC_IRQ_SCC1] = -1, 323 [DEC_IRQ_SII] = -1, 324 [DEC_IRQ_TC0] = KN02_IRQ_NR(KN02_CSR_INR_TC0), 325 [DEC_IRQ_TC1] = KN02_IRQ_NR(KN02_CSR_INR_TC1), 326 [DEC_IRQ_TC2] = KN02_IRQ_NR(KN02_CSR_INR_TC2), 327 [DEC_IRQ_TIMER] = -1, 328 [DEC_IRQ_VIDEO] = -1, 329 [DEC_IRQ_ASC_MERR] = -1, 330 [DEC_IRQ_ASC_ERR] = -1, 331 [DEC_IRQ_ASC_DMA] = -1, 332 [DEC_IRQ_FLOPPY_ERR] = -1, 333 [DEC_IRQ_ISDN_ERR] = -1, 334 [DEC_IRQ_ISDN_RXDMA] = -1, 335 [DEC_IRQ_ISDN_TXDMA] = -1, 336 [DEC_IRQ_LANCE_MERR] = -1, 337 [DEC_IRQ_SCC0A_RXERR] = -1, 338 [DEC_IRQ_SCC0A_RXDMA] = -1, 339 [DEC_IRQ_SCC0A_TXERR] = -1, 340 [DEC_IRQ_SCC0A_TXDMA] = -1, 341 [DEC_IRQ_AB_RXERR] = -1, 342 [DEC_IRQ_AB_RXDMA] = -1, 343 [DEC_IRQ_AB_TXERR] = -1, 344 [DEC_IRQ_AB_TXDMA] = -1, 345 [DEC_IRQ_SCC1A_RXERR] = -1, 346 [DEC_IRQ_SCC1A_RXDMA] = -1, 347 [DEC_IRQ_SCC1A_TXERR] = -1, 348 [DEC_IRQ_SCC1A_TXDMA] = -1, 349 }; 350 351 static int_ptr kn02_cpu_mask_nr_tbl[][2] __initdata = { 352 { { .i = DEC_CPU_IRQ_MASK(KN02_CPU_INR_BUS) }, 353 { .i = DEC_CPU_IRQ_NR(KN02_CPU_INR_BUS) } }, 354 { { .i = DEC_CPU_IRQ_MASK(KN02_CPU_INR_RTC) }, 355 { .i = DEC_CPU_IRQ_NR(KN02_CPU_INR_RTC) } }, 356 { { .i = DEC_CPU_IRQ_MASK(KN02_CPU_INR_CASCADE) }, 357 { .p = kn02_io_int } }, 358 { { .i = DEC_CPU_IRQ_ALL }, 359 { .p = cpu_all_int } }, 360 }; 361 362 static int_ptr kn02_asic_mask_nr_tbl[][2] __initdata = { 363 { { .i = KN02_IRQ_MASK(KN02_CSR_INR_DZ11) }, 364 { .i = KN02_IRQ_NR(KN02_CSR_INR_DZ11) } }, 365 { { .i = KN02_IRQ_MASK(KN02_CSR_INR_ASC) }, 366 { .i = KN02_IRQ_NR(KN02_CSR_INR_ASC) } }, 367 { { .i = KN02_IRQ_MASK(KN02_CSR_INR_LANCE) }, 368 { .i = KN02_IRQ_NR(KN02_CSR_INR_LANCE) } }, 369 { { .i = KN02_IRQ_MASK(KN02_CSR_INR_TC2) }, 370 { .i = KN02_IRQ_NR(KN02_CSR_INR_TC2) } }, 371 { { .i = KN02_IRQ_MASK(KN02_CSR_INR_TC1) }, 372 { .i = KN02_IRQ_NR(KN02_CSR_INR_TC1) } }, 373 { { .i = KN02_IRQ_MASK(KN02_CSR_INR_TC0) }, 374 { .i = KN02_IRQ_NR(KN02_CSR_INR_TC0) } }, 375 { { .i = KN02_IRQ_ALL }, 376 { .p = kn02_all_int } }, 377 }; 378 379 static void __init dec_init_kn02(void) 380 { 381 /* IRQ routing. */ 382 memcpy(&dec_interrupt, &kn02_interrupt, 383 sizeof(kn02_interrupt)); 384 385 /* CPU IRQ priorities. */ 386 memcpy(&cpu_mask_nr_tbl, &kn02_cpu_mask_nr_tbl, 387 sizeof(kn02_cpu_mask_nr_tbl)); 388 389 /* KN02 CSR IRQ priorities. */ 390 memcpy(&asic_mask_nr_tbl, &kn02_asic_mask_nr_tbl, 391 sizeof(kn02_asic_mask_nr_tbl)); 392 393 mips_cpu_irq_init(); 394 init_kn02_irqs(KN02_IRQ_BASE); 395 396 } /* dec_init_kn02 */ 397 398 399 /* 400 * Machine-specific initialisation for KN02-BA, aka DS5000/1xx 401 * (xx = 20, 25, 33), aka 3min. Also applies to KN04(-BA), aka 402 * DS5000/150, aka 4min. 403 */ 404 static int kn02ba_interrupt[DEC_NR_INTS] __initdata = { 405 [DEC_IRQ_CASCADE] = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_CASCADE), 406 [DEC_IRQ_AB_RECV] = -1, 407 [DEC_IRQ_AB_XMIT] = -1, 408 [DEC_IRQ_DZ11] = -1, 409 [DEC_IRQ_ASC] = IO_IRQ_NR(KN02BA_IO_INR_ASC), 410 [DEC_IRQ_FLOPPY] = -1, 411 [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU), 412 [DEC_IRQ_HALT] = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_HALT), 413 [DEC_IRQ_ISDN] = -1, 414 [DEC_IRQ_LANCE] = IO_IRQ_NR(KN02BA_IO_INR_LANCE), 415 [DEC_IRQ_BUS] = IO_IRQ_NR(KN02BA_IO_INR_BUS), 416 [DEC_IRQ_PSU] = IO_IRQ_NR(KN02BA_IO_INR_PSU), 417 [DEC_IRQ_RTC] = IO_IRQ_NR(KN02BA_IO_INR_RTC), 418 [DEC_IRQ_SCC0] = IO_IRQ_NR(KN02BA_IO_INR_SCC0), 419 [DEC_IRQ_SCC1] = IO_IRQ_NR(KN02BA_IO_INR_SCC1), 420 [DEC_IRQ_SII] = -1, 421 [DEC_IRQ_TC0] = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC0), 422 [DEC_IRQ_TC1] = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC1), 423 [DEC_IRQ_TC2] = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC2), 424 [DEC_IRQ_TIMER] = -1, 425 [DEC_IRQ_VIDEO] = -1, 426 [DEC_IRQ_ASC_MERR] = IO_IRQ_NR(IO_INR_ASC_MERR), 427 [DEC_IRQ_ASC_ERR] = IO_IRQ_NR(IO_INR_ASC_ERR), 428 [DEC_IRQ_ASC_DMA] = IO_IRQ_NR(IO_INR_ASC_DMA), 429 [DEC_IRQ_FLOPPY_ERR] = -1, 430 [DEC_IRQ_ISDN_ERR] = -1, 431 [DEC_IRQ_ISDN_RXDMA] = -1, 432 [DEC_IRQ_ISDN_TXDMA] = -1, 433 [DEC_IRQ_LANCE_MERR] = IO_IRQ_NR(IO_INR_LANCE_MERR), 434 [DEC_IRQ_SCC0A_RXERR] = IO_IRQ_NR(IO_INR_SCC0A_RXERR), 435 [DEC_IRQ_SCC0A_RXDMA] = IO_IRQ_NR(IO_INR_SCC0A_RXDMA), 436 [DEC_IRQ_SCC0A_TXERR] = IO_IRQ_NR(IO_INR_SCC0A_TXERR), 437 [DEC_IRQ_SCC0A_TXDMA] = IO_IRQ_NR(IO_INR_SCC0A_TXDMA), 438 [DEC_IRQ_AB_RXERR] = -1, 439 [DEC_IRQ_AB_RXDMA] = -1, 440 [DEC_IRQ_AB_TXERR] = -1, 441 [DEC_IRQ_AB_TXDMA] = -1, 442 [DEC_IRQ_SCC1A_RXERR] = IO_IRQ_NR(IO_INR_SCC1A_RXERR), 443 [DEC_IRQ_SCC1A_RXDMA] = IO_IRQ_NR(IO_INR_SCC1A_RXDMA), 444 [DEC_IRQ_SCC1A_TXERR] = IO_IRQ_NR(IO_INR_SCC1A_TXERR), 445 [DEC_IRQ_SCC1A_TXDMA] = IO_IRQ_NR(IO_INR_SCC1A_TXDMA), 446 }; 447 448 static int_ptr kn02ba_cpu_mask_nr_tbl[][2] __initdata = { 449 { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_CASCADE) }, 450 { .p = kn02xa_io_int } }, 451 { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC2) }, 452 { .i = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC2) } }, 453 { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC1) }, 454 { .i = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC1) } }, 455 { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC0) }, 456 { .i = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC0) } }, 457 { { .i = DEC_CPU_IRQ_ALL }, 458 { .p = cpu_all_int } }, 459 }; 460 461 static int_ptr kn02ba_asic_mask_nr_tbl[][2] __initdata = { 462 { { .i = IO_IRQ_MASK(KN02BA_IO_INR_BUS) }, 463 { .i = IO_IRQ_NR(KN02BA_IO_INR_BUS) } }, 464 { { .i = IO_IRQ_MASK(KN02BA_IO_INR_RTC) }, 465 { .i = IO_IRQ_NR(KN02BA_IO_INR_RTC) } }, 466 { { .i = IO_IRQ_DMA }, 467 { .p = asic_dma_int } }, 468 { { .i = IO_IRQ_MASK(KN02BA_IO_INR_SCC0) }, 469 { .i = IO_IRQ_NR(KN02BA_IO_INR_SCC0) } }, 470 { { .i = IO_IRQ_MASK(KN02BA_IO_INR_SCC1) }, 471 { .i = IO_IRQ_NR(KN02BA_IO_INR_SCC1) } }, 472 { { .i = IO_IRQ_MASK(KN02BA_IO_INR_ASC) }, 473 { .i = IO_IRQ_NR(KN02BA_IO_INR_ASC) } }, 474 { { .i = IO_IRQ_MASK(KN02BA_IO_INR_LANCE) }, 475 { .i = IO_IRQ_NR(KN02BA_IO_INR_LANCE) } }, 476 { { .i = IO_IRQ_ALL }, 477 { .p = asic_all_int } }, 478 }; 479 480 static void __init dec_init_kn02ba(void) 481 { 482 /* IRQ routing. */ 483 memcpy(&dec_interrupt, &kn02ba_interrupt, 484 sizeof(kn02ba_interrupt)); 485 486 /* CPU IRQ priorities. */ 487 memcpy(&cpu_mask_nr_tbl, &kn02ba_cpu_mask_nr_tbl, 488 sizeof(kn02ba_cpu_mask_nr_tbl)); 489 490 /* I/O ASIC IRQ priorities. */ 491 memcpy(&asic_mask_nr_tbl, &kn02ba_asic_mask_nr_tbl, 492 sizeof(kn02ba_asic_mask_nr_tbl)); 493 494 mips_cpu_irq_init(); 495 init_ioasic_irqs(IO_IRQ_BASE); 496 497 } /* dec_init_kn02ba */ 498 499 500 /* 501 * Machine-specific initialisation for KN02-CA, aka DS5000/xx, 502 * (xx = 20, 25, 33), aka MAXine. Also applies to KN04(-CA), aka 503 * DS5000/50, aka 4MAXine. 504 */ 505 static int kn02ca_interrupt[DEC_NR_INTS] __initdata = { 506 [DEC_IRQ_CASCADE] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_CASCADE), 507 [DEC_IRQ_AB_RECV] = IO_IRQ_NR(KN02CA_IO_INR_AB_RECV), 508 [DEC_IRQ_AB_XMIT] = IO_IRQ_NR(KN02CA_IO_INR_AB_XMIT), 509 [DEC_IRQ_DZ11] = -1, 510 [DEC_IRQ_ASC] = IO_IRQ_NR(KN02CA_IO_INR_ASC), 511 [DEC_IRQ_FLOPPY] = IO_IRQ_NR(KN02CA_IO_INR_FLOPPY), 512 [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU), 513 [DEC_IRQ_HALT] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_HALT), 514 [DEC_IRQ_ISDN] = IO_IRQ_NR(KN02CA_IO_INR_ISDN), 515 [DEC_IRQ_LANCE] = IO_IRQ_NR(KN02CA_IO_INR_LANCE), 516 [DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_BUS), 517 [DEC_IRQ_PSU] = -1, 518 [DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_RTC), 519 [DEC_IRQ_SCC0] = IO_IRQ_NR(KN02CA_IO_INR_SCC0), 520 [DEC_IRQ_SCC1] = -1, 521 [DEC_IRQ_SII] = -1, 522 [DEC_IRQ_TC0] = IO_IRQ_NR(KN02CA_IO_INR_TC0), 523 [DEC_IRQ_TC1] = IO_IRQ_NR(KN02CA_IO_INR_TC1), 524 [DEC_IRQ_TC2] = -1, 525 [DEC_IRQ_TIMER] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_TIMER), 526 [DEC_IRQ_VIDEO] = IO_IRQ_NR(KN02CA_IO_INR_VIDEO), 527 [DEC_IRQ_ASC_MERR] = IO_IRQ_NR(IO_INR_ASC_MERR), 528 [DEC_IRQ_ASC_ERR] = IO_IRQ_NR(IO_INR_ASC_ERR), 529 [DEC_IRQ_ASC_DMA] = IO_IRQ_NR(IO_INR_ASC_DMA), 530 [DEC_IRQ_FLOPPY_ERR] = IO_IRQ_NR(IO_INR_FLOPPY_ERR), 531 [DEC_IRQ_ISDN_ERR] = IO_IRQ_NR(IO_INR_ISDN_ERR), 532 [DEC_IRQ_ISDN_RXDMA] = IO_IRQ_NR(IO_INR_ISDN_RXDMA), 533 [DEC_IRQ_ISDN_TXDMA] = IO_IRQ_NR(IO_INR_ISDN_TXDMA), 534 [DEC_IRQ_LANCE_MERR] = IO_IRQ_NR(IO_INR_LANCE_MERR), 535 [DEC_IRQ_SCC0A_RXERR] = IO_IRQ_NR(IO_INR_SCC0A_RXERR), 536 [DEC_IRQ_SCC0A_RXDMA] = IO_IRQ_NR(IO_INR_SCC0A_RXDMA), 537 [DEC_IRQ_SCC0A_TXERR] = IO_IRQ_NR(IO_INR_SCC0A_TXERR), 538 [DEC_IRQ_SCC0A_TXDMA] = IO_IRQ_NR(IO_INR_SCC0A_TXDMA), 539 [DEC_IRQ_AB_RXERR] = IO_IRQ_NR(IO_INR_AB_RXERR), 540 [DEC_IRQ_AB_RXDMA] = IO_IRQ_NR(IO_INR_AB_RXDMA), 541 [DEC_IRQ_AB_TXERR] = IO_IRQ_NR(IO_INR_AB_TXERR), 542 [DEC_IRQ_AB_TXDMA] = IO_IRQ_NR(IO_INR_AB_TXDMA), 543 [DEC_IRQ_SCC1A_RXERR] = -1, 544 [DEC_IRQ_SCC1A_RXDMA] = -1, 545 [DEC_IRQ_SCC1A_TXERR] = -1, 546 [DEC_IRQ_SCC1A_TXDMA] = -1, 547 }; 548 549 static int_ptr kn02ca_cpu_mask_nr_tbl[][2] __initdata = { 550 { { .i = DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_BUS) }, 551 { .i = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_BUS) } }, 552 { { .i = DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_RTC) }, 553 { .i = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_RTC) } }, 554 { { .i = DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_CASCADE) }, 555 { .p = kn02xa_io_int } }, 556 { { .i = DEC_CPU_IRQ_ALL }, 557 { .p = cpu_all_int } }, 558 }; 559 560 static int_ptr kn02ca_asic_mask_nr_tbl[][2] __initdata = { 561 { { .i = IO_IRQ_DMA }, 562 { .p = asic_dma_int } }, 563 { { .i = IO_IRQ_MASK(KN02CA_IO_INR_SCC0) }, 564 { .i = IO_IRQ_NR(KN02CA_IO_INR_SCC0) } }, 565 { { .i = IO_IRQ_MASK(KN02CA_IO_INR_ASC) }, 566 { .i = IO_IRQ_NR(KN02CA_IO_INR_ASC) } }, 567 { { .i = IO_IRQ_MASK(KN02CA_IO_INR_LANCE) }, 568 { .i = IO_IRQ_NR(KN02CA_IO_INR_LANCE) } }, 569 { { .i = IO_IRQ_MASK(KN02CA_IO_INR_TC1) }, 570 { .i = IO_IRQ_NR(KN02CA_IO_INR_TC1) } }, 571 { { .i = IO_IRQ_MASK(KN02CA_IO_INR_TC0) }, 572 { .i = IO_IRQ_NR(KN02CA_IO_INR_TC0) } }, 573 { { .i = IO_IRQ_ALL }, 574 { .p = asic_all_int } }, 575 }; 576 577 static void __init dec_init_kn02ca(void) 578 { 579 /* IRQ routing. */ 580 memcpy(&dec_interrupt, &kn02ca_interrupt, 581 sizeof(kn02ca_interrupt)); 582 583 /* CPU IRQ priorities. */ 584 memcpy(&cpu_mask_nr_tbl, &kn02ca_cpu_mask_nr_tbl, 585 sizeof(kn02ca_cpu_mask_nr_tbl)); 586 587 /* I/O ASIC IRQ priorities. */ 588 memcpy(&asic_mask_nr_tbl, &kn02ca_asic_mask_nr_tbl, 589 sizeof(kn02ca_asic_mask_nr_tbl)); 590 591 mips_cpu_irq_init(); 592 init_ioasic_irqs(IO_IRQ_BASE); 593 594 } /* dec_init_kn02ca */ 595 596 597 /* 598 * Machine-specific initialisation for KN03, aka DS5000/240, 599 * aka 3max+ and DS5900, aka BIGmax. Also applies to KN05, aka 600 * DS5000/260, aka 4max+ and DS5900/260. 601 */ 602 static int kn03_interrupt[DEC_NR_INTS] __initdata = { 603 [DEC_IRQ_CASCADE] = DEC_CPU_IRQ_NR(KN03_CPU_INR_CASCADE), 604 [DEC_IRQ_AB_RECV] = -1, 605 [DEC_IRQ_AB_XMIT] = -1, 606 [DEC_IRQ_DZ11] = -1, 607 [DEC_IRQ_ASC] = IO_IRQ_NR(KN03_IO_INR_ASC), 608 [DEC_IRQ_FLOPPY] = -1, 609 [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU), 610 [DEC_IRQ_HALT] = DEC_CPU_IRQ_NR(KN03_CPU_INR_HALT), 611 [DEC_IRQ_ISDN] = -1, 612 [DEC_IRQ_LANCE] = IO_IRQ_NR(KN03_IO_INR_LANCE), 613 [DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN03_CPU_INR_BUS), 614 [DEC_IRQ_PSU] = IO_IRQ_NR(KN03_IO_INR_PSU), 615 [DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN03_CPU_INR_RTC), 616 [DEC_IRQ_SCC0] = IO_IRQ_NR(KN03_IO_INR_SCC0), 617 [DEC_IRQ_SCC1] = IO_IRQ_NR(KN03_IO_INR_SCC1), 618 [DEC_IRQ_SII] = -1, 619 [DEC_IRQ_TC0] = IO_IRQ_NR(KN03_IO_INR_TC0), 620 [DEC_IRQ_TC1] = IO_IRQ_NR(KN03_IO_INR_TC1), 621 [DEC_IRQ_TC2] = IO_IRQ_NR(KN03_IO_INR_TC2), 622 [DEC_IRQ_TIMER] = -1, 623 [DEC_IRQ_VIDEO] = -1, 624 [DEC_IRQ_ASC_MERR] = IO_IRQ_NR(IO_INR_ASC_MERR), 625 [DEC_IRQ_ASC_ERR] = IO_IRQ_NR(IO_INR_ASC_ERR), 626 [DEC_IRQ_ASC_DMA] = IO_IRQ_NR(IO_INR_ASC_DMA), 627 [DEC_IRQ_FLOPPY_ERR] = -1, 628 [DEC_IRQ_ISDN_ERR] = -1, 629 [DEC_IRQ_ISDN_RXDMA] = -1, 630 [DEC_IRQ_ISDN_TXDMA] = -1, 631 [DEC_IRQ_LANCE_MERR] = IO_IRQ_NR(IO_INR_LANCE_MERR), 632 [DEC_IRQ_SCC0A_RXERR] = IO_IRQ_NR(IO_INR_SCC0A_RXERR), 633 [DEC_IRQ_SCC0A_RXDMA] = IO_IRQ_NR(IO_INR_SCC0A_RXDMA), 634 [DEC_IRQ_SCC0A_TXERR] = IO_IRQ_NR(IO_INR_SCC0A_TXERR), 635 [DEC_IRQ_SCC0A_TXDMA] = IO_IRQ_NR(IO_INR_SCC0A_TXDMA), 636 [DEC_IRQ_AB_RXERR] = -1, 637 [DEC_IRQ_AB_RXDMA] = -1, 638 [DEC_IRQ_AB_TXERR] = -1, 639 [DEC_IRQ_AB_TXDMA] = -1, 640 [DEC_IRQ_SCC1A_RXERR] = IO_IRQ_NR(IO_INR_SCC1A_RXERR), 641 [DEC_IRQ_SCC1A_RXDMA] = IO_IRQ_NR(IO_INR_SCC1A_RXDMA), 642 [DEC_IRQ_SCC1A_TXERR] = IO_IRQ_NR(IO_INR_SCC1A_TXERR), 643 [DEC_IRQ_SCC1A_TXDMA] = IO_IRQ_NR(IO_INR_SCC1A_TXDMA), 644 }; 645 646 static int_ptr kn03_cpu_mask_nr_tbl[][2] __initdata = { 647 { { .i = DEC_CPU_IRQ_MASK(KN03_CPU_INR_BUS) }, 648 { .i = DEC_CPU_IRQ_NR(KN03_CPU_INR_BUS) } }, 649 { { .i = DEC_CPU_IRQ_MASK(KN03_CPU_INR_RTC) }, 650 { .i = DEC_CPU_IRQ_NR(KN03_CPU_INR_RTC) } }, 651 { { .i = DEC_CPU_IRQ_MASK(KN03_CPU_INR_CASCADE) }, 652 { .p = kn03_io_int } }, 653 { { .i = DEC_CPU_IRQ_ALL }, 654 { .p = cpu_all_int } }, 655 }; 656 657 static int_ptr kn03_asic_mask_nr_tbl[][2] __initdata = { 658 { { .i = IO_IRQ_DMA }, 659 { .p = asic_dma_int } }, 660 { { .i = IO_IRQ_MASK(KN03_IO_INR_SCC0) }, 661 { .i = IO_IRQ_NR(KN03_IO_INR_SCC0) } }, 662 { { .i = IO_IRQ_MASK(KN03_IO_INR_SCC1) }, 663 { .i = IO_IRQ_NR(KN03_IO_INR_SCC1) } }, 664 { { .i = IO_IRQ_MASK(KN03_IO_INR_ASC) }, 665 { .i = IO_IRQ_NR(KN03_IO_INR_ASC) } }, 666 { { .i = IO_IRQ_MASK(KN03_IO_INR_LANCE) }, 667 { .i = IO_IRQ_NR(KN03_IO_INR_LANCE) } }, 668 { { .i = IO_IRQ_MASK(KN03_IO_INR_TC2) }, 669 { .i = IO_IRQ_NR(KN03_IO_INR_TC2) } }, 670 { { .i = IO_IRQ_MASK(KN03_IO_INR_TC1) }, 671 { .i = IO_IRQ_NR(KN03_IO_INR_TC1) } }, 672 { { .i = IO_IRQ_MASK(KN03_IO_INR_TC0) }, 673 { .i = IO_IRQ_NR(KN03_IO_INR_TC0) } }, 674 { { .i = IO_IRQ_ALL }, 675 { .p = asic_all_int } }, 676 }; 677 678 static void __init dec_init_kn03(void) 679 { 680 /* IRQ routing. */ 681 memcpy(&dec_interrupt, &kn03_interrupt, 682 sizeof(kn03_interrupt)); 683 684 /* CPU IRQ priorities. */ 685 memcpy(&cpu_mask_nr_tbl, &kn03_cpu_mask_nr_tbl, 686 sizeof(kn03_cpu_mask_nr_tbl)); 687 688 /* I/O ASIC IRQ priorities. */ 689 memcpy(&asic_mask_nr_tbl, &kn03_asic_mask_nr_tbl, 690 sizeof(kn03_asic_mask_nr_tbl)); 691 692 mips_cpu_irq_init(); 693 init_ioasic_irqs(IO_IRQ_BASE); 694 695 } /* dec_init_kn03 */ 696 697 698 void __init arch_init_irq(void) 699 { 700 switch (mips_machtype) { 701 case MACH_DS23100: /* DS2100/DS3100 Pmin/Pmax */ 702 dec_init_kn01(); 703 break; 704 case MACH_DS5100: /* DS5100 MIPSmate */ 705 dec_init_kn230(); 706 break; 707 case MACH_DS5000_200: /* DS5000/200 3max */ 708 dec_init_kn02(); 709 break; 710 case MACH_DS5000_1XX: /* DS5000/1xx 3min */ 711 dec_init_kn02ba(); 712 break; 713 case MACH_DS5000_2X0: /* DS5000/240 3max+ */ 714 case MACH_DS5900: /* DS5900 bigmax */ 715 dec_init_kn03(); 716 break; 717 case MACH_DS5000_XX: /* Personal DS5000/xx */ 718 dec_init_kn02ca(); 719 break; 720 case MACH_DS5800: /* DS5800 Isis */ 721 panic("Don't know how to set this up!"); 722 break; 723 case MACH_DS5400: /* DS5400 MIPSfair */ 724 panic("Don't know how to set this up!"); 725 break; 726 case MACH_DS5500: /* DS5500 MIPSfair-2 */ 727 panic("Don't know how to set this up!"); 728 break; 729 } 730 731 /* Free the FPU interrupt if the exception is present. */ 732 if (!cpu_has_nofpuex) { 733 cpu_fpu_mask = 0; 734 dec_interrupt[DEC_IRQ_FPU] = -1; 735 } 736 /* Free the halt interrupt unused on R4k systems. */ 737 if (current_cpu_type() == CPU_R4000SC || 738 current_cpu_type() == CPU_R4400SC) 739 dec_interrupt[DEC_IRQ_HALT] = -1; 740 741 /* Register board interrupts: FPU and cascade. */ 742 if (dec_interrupt[DEC_IRQ_FPU] >= 0 && cpu_has_fpu) { 743 struct irq_desc *desc_fpu; 744 int irq_fpu; 745 746 irq_fpu = dec_interrupt[DEC_IRQ_FPU]; 747 if (request_irq(irq_fpu, no_action, IRQF_NO_THREAD, "fpu", 748 NULL)) 749 pr_err("Failed to register fpu interrupt\n"); 750 desc_fpu = irq_to_desc(irq_fpu); 751 fpu_kstat_irq = this_cpu_ptr(desc_fpu->kstat_irqs); 752 } 753 if (dec_interrupt[DEC_IRQ_CASCADE] >= 0) { 754 if (request_irq(dec_interrupt[DEC_IRQ_CASCADE], no_action, 755 IRQF_NO_THREAD, "cascade", NULL)) 756 pr_err("Failed to register cascade interrupt\n"); 757 } 758 /* Register the bus error interrupt. */ 759 if (dec_interrupt[DEC_IRQ_BUS] >= 0 && busirq_handler) { 760 if (request_irq(dec_interrupt[DEC_IRQ_BUS], busirq_handler, 761 busirq_flags, "bus error", busirq_handler)) 762 pr_err("Failed to register bus error interrupt\n"); 763 } 764 /* Register the HALT interrupt. */ 765 if (dec_interrupt[DEC_IRQ_HALT] >= 0) { 766 if (request_irq(dec_interrupt[DEC_IRQ_HALT], dec_intr_halt, 767 IRQF_NO_THREAD, "halt", NULL)) 768 pr_err("Failed to register halt interrupt\n"); 769 } 770 } 771 772 asmlinkage unsigned int dec_irq_dispatch(unsigned int irq) 773 { 774 do_IRQ(irq); 775 return 0; 776 } 777