1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2004-2008, 2009, 2010 Cavium Networks 7 */ 8 #include <linux/cpu.h> 9 #include <linux/delay.h> 10 #include <linux/smp.h> 11 #include <linux/interrupt.h> 12 #include <linux/kernel_stat.h> 13 #include <linux/sched.h> 14 #include <linux/sched/hotplug.h> 15 #include <linux/sched/task_stack.h> 16 #include <linux/init.h> 17 #include <linux/export.h> 18 #include <linux/kexec.h> 19 20 #include <asm/mmu_context.h> 21 #include <asm/time.h> 22 #include <asm/setup.h> 23 24 #include <asm/octeon/octeon.h> 25 26 #include "octeon_boot.h" 27 28 volatile unsigned long octeon_processor_boot = 0xff; 29 volatile unsigned long octeon_processor_sp; 30 volatile unsigned long octeon_processor_gp; 31 #ifdef CONFIG_RELOCATABLE 32 volatile unsigned long octeon_processor_relocated_kernel_entry; 33 #endif /* CONFIG_RELOCATABLE */ 34 35 #ifdef CONFIG_HOTPLUG_CPU 36 uint64_t octeon_bootloader_entry_addr; 37 EXPORT_SYMBOL(octeon_bootloader_entry_addr); 38 #endif 39 40 extern void kernel_entry(unsigned long arg1, ...); 41 42 static void octeon_icache_flush(void) 43 { 44 asm volatile ("synci 0($0)\n"); 45 } 46 47 static void (*octeon_message_functions[8])(void) = { 48 scheduler_ipi, 49 generic_smp_call_function_interrupt, 50 octeon_icache_flush, 51 }; 52 53 static irqreturn_t mailbox_interrupt(int irq, void *dev_id) 54 { 55 u64 mbox_clrx = CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()); 56 u64 action; 57 int i; 58 59 /* 60 * Make sure the function array initialization remains 61 * correct. 62 */ 63 BUILD_BUG_ON(SMP_RESCHEDULE_YOURSELF != (1 << 0)); 64 BUILD_BUG_ON(SMP_CALL_FUNCTION != (1 << 1)); 65 BUILD_BUG_ON(SMP_ICACHE_FLUSH != (1 << 2)); 66 67 /* 68 * Load the mailbox register to figure out what we're supposed 69 * to do. 70 */ 71 action = cvmx_read_csr(mbox_clrx); 72 73 if (OCTEON_IS_MODEL(OCTEON_CN68XX)) 74 action &= 0xff; 75 else 76 action &= 0xffff; 77 78 /* Clear the mailbox to clear the interrupt */ 79 cvmx_write_csr(mbox_clrx, action); 80 81 for (i = 0; i < ARRAY_SIZE(octeon_message_functions) && action;) { 82 if (action & 1) { 83 void (*fn)(void) = octeon_message_functions[i]; 84 85 if (fn) 86 fn(); 87 } 88 action >>= 1; 89 i++; 90 } 91 return IRQ_HANDLED; 92 } 93 94 /* 95 * Cause the function described by call_data to be executed on the passed 96 * cpu. When the function has finished, increment the finished field of 97 * call_data. 98 */ 99 void octeon_send_ipi_single(int cpu, unsigned int action) 100 { 101 int coreid = cpu_logical_map(cpu); 102 /* 103 pr_info("SMP: Mailbox send cpu=%d, coreid=%d, action=%u\n", cpu, 104 coreid, action); 105 */ 106 cvmx_write_csr(CVMX_CIU_MBOX_SETX(coreid), action); 107 } 108 109 static inline void octeon_send_ipi_mask(const struct cpumask *mask, 110 unsigned int action) 111 { 112 unsigned int i; 113 114 for_each_cpu(i, mask) 115 octeon_send_ipi_single(i, action); 116 } 117 118 /* 119 * Detect available CPUs, populate cpu_possible_mask 120 */ 121 static void octeon_smp_hotplug_setup(void) 122 { 123 #ifdef CONFIG_HOTPLUG_CPU 124 struct linux_app_boot_info *labi; 125 126 if (!setup_max_cpus) 127 return; 128 129 labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER); 130 if (labi->labi_signature != LABI_SIGNATURE) { 131 pr_info("The bootloader on this board does not support HOTPLUG_CPU."); 132 return; 133 } 134 135 octeon_bootloader_entry_addr = labi->InitTLBStart_addr; 136 #endif 137 } 138 139 static void __init octeon_smp_setup(void) 140 { 141 const int coreid = cvmx_get_core_num(); 142 int cpus; 143 int id; 144 struct cvmx_sysinfo *sysinfo = cvmx_sysinfo_get(); 145 146 #ifdef CONFIG_HOTPLUG_CPU 147 int core_mask = octeon_get_boot_coremask(); 148 unsigned int num_cores = cvmx_octeon_num_cores(); 149 #endif 150 151 /* The present CPUs are initially just the boot cpu (CPU 0). */ 152 for (id = 0; id < NR_CPUS; id++) { 153 set_cpu_possible(id, id == 0); 154 set_cpu_present(id, id == 0); 155 } 156 157 __cpu_number_map[coreid] = 0; 158 __cpu_logical_map[0] = coreid; 159 160 /* The present CPUs get the lowest CPU numbers. */ 161 cpus = 1; 162 for (id = 0; id < NR_CPUS; id++) { 163 if ((id != coreid) && cvmx_coremask_is_core_set(&sysinfo->core_mask, id)) { 164 set_cpu_possible(cpus, true); 165 set_cpu_present(cpus, true); 166 __cpu_number_map[id] = cpus; 167 __cpu_logical_map[cpus] = id; 168 cpus++; 169 } 170 } 171 172 #ifdef CONFIG_HOTPLUG_CPU 173 /* 174 * The possible CPUs are all those present on the chip. We 175 * will assign CPU numbers for possible cores as well. Cores 176 * are always consecutively numberd from 0. 177 */ 178 for (id = 0; setup_max_cpus && octeon_bootloader_entry_addr && 179 id < num_cores && id < NR_CPUS; id++) { 180 if (!(core_mask & (1 << id))) { 181 set_cpu_possible(cpus, true); 182 __cpu_number_map[id] = cpus; 183 __cpu_logical_map[cpus] = id; 184 cpus++; 185 } 186 } 187 #endif 188 189 octeon_smp_hotplug_setup(); 190 } 191 192 193 #ifdef CONFIG_RELOCATABLE 194 int plat_post_relocation(long offset) 195 { 196 unsigned long entry = (unsigned long)kernel_entry; 197 198 /* Send secondaries into relocated kernel */ 199 octeon_processor_relocated_kernel_entry = entry + offset; 200 201 return 0; 202 } 203 #endif /* CONFIG_RELOCATABLE */ 204 205 /* 206 * Firmware CPU startup hook 207 */ 208 static int octeon_boot_secondary(int cpu, struct task_struct *idle) 209 { 210 int count; 211 212 pr_info("SMP: Booting CPU%02d (CoreId %2d)...\n", cpu, 213 cpu_logical_map(cpu)); 214 215 octeon_processor_sp = __KSTK_TOS(idle); 216 octeon_processor_gp = (unsigned long)(task_thread_info(idle)); 217 octeon_processor_boot = cpu_logical_map(cpu); 218 mb(); 219 220 count = 10000; 221 while (octeon_processor_sp && count) { 222 /* Waiting for processor to get the SP and GP */ 223 udelay(1); 224 count--; 225 } 226 if (count == 0) { 227 pr_err("Secondary boot timeout\n"); 228 return -ETIMEDOUT; 229 } 230 231 return 0; 232 } 233 234 /* 235 * After we've done initial boot, this function is called to allow the 236 * board code to clean up state, if needed 237 */ 238 static void octeon_init_secondary(void) 239 { 240 unsigned int sr; 241 242 sr = set_c0_status(ST0_BEV); 243 write_c0_ebase((u32)ebase); 244 write_c0_status(sr); 245 246 octeon_check_cpu_bist(); 247 octeon_init_cvmcount(); 248 249 octeon_irq_setup_secondary(); 250 } 251 252 /* 253 * Callout to firmware before smp_init 254 */ 255 static void __init octeon_prepare_cpus(unsigned int max_cpus) 256 { 257 /* 258 * Only the low order mailbox bits are used for IPIs, leave 259 * the other bits alone. 260 */ 261 cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()), 0xffff); 262 if (request_irq(OCTEON_IRQ_MBOX0, mailbox_interrupt, 263 IRQF_PERCPU | IRQF_NO_THREAD, "SMP-IPI", 264 mailbox_interrupt)) { 265 panic("Cannot request_irq(OCTEON_IRQ_MBOX0)"); 266 } 267 } 268 269 /* 270 * Last chance for the board code to finish SMP initialization before 271 * the CPU is "online". 272 */ 273 static void octeon_smp_finish(void) 274 { 275 octeon_user_io_init(); 276 277 /* to generate the first CPU timer interrupt */ 278 write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ); 279 local_irq_enable(); 280 } 281 282 #ifdef CONFIG_HOTPLUG_CPU 283 284 /* State of each CPU. */ 285 static DEFINE_PER_CPU(int, cpu_state); 286 287 static int octeon_cpu_disable(void) 288 { 289 unsigned int cpu = smp_processor_id(); 290 291 if (!octeon_bootloader_entry_addr) 292 return -ENOTSUPP; 293 294 set_cpu_online(cpu, false); 295 calculate_cpu_foreign_map(); 296 octeon_fixup_irqs(); 297 298 __flush_cache_all(); 299 local_flush_tlb_all(); 300 301 return 0; 302 } 303 304 static void octeon_cpu_die(unsigned int cpu) 305 { 306 int coreid = cpu_logical_map(cpu); 307 uint32_t mask, new_mask; 308 const struct cvmx_bootmem_named_block_desc *block_desc; 309 310 while (per_cpu(cpu_state, cpu) != CPU_DEAD) 311 cpu_relax(); 312 313 /* 314 * This is a bit complicated strategics of getting/settig available 315 * cores mask, copied from bootloader 316 */ 317 318 mask = 1 << coreid; 319 /* LINUX_APP_BOOT_BLOCK is initialized in bootoct binary */ 320 block_desc = cvmx_bootmem_find_named_block(LINUX_APP_BOOT_BLOCK_NAME); 321 322 if (!block_desc) { 323 struct linux_app_boot_info *labi; 324 325 labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER); 326 327 labi->avail_coremask |= mask; 328 new_mask = labi->avail_coremask; 329 } else { /* alternative, already initialized */ 330 uint32_t *p = (uint32_t *)PHYS_TO_XKSEG_CACHED(block_desc->base_addr + 331 AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK); 332 *p |= mask; 333 new_mask = *p; 334 } 335 336 pr_info("Reset core %d. Available Coremask = 0x%x \n", coreid, new_mask); 337 mb(); 338 cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid); 339 cvmx_write_csr(CVMX_CIU_PP_RST, 0); 340 } 341 342 void play_dead(void) 343 { 344 int cpu = cpu_number_map(cvmx_get_core_num()); 345 346 idle_task_exit(); 347 octeon_processor_boot = 0xff; 348 per_cpu(cpu_state, cpu) = CPU_DEAD; 349 350 mb(); 351 352 while (1) /* core will be reset here */ 353 ; 354 } 355 356 static void start_after_reset(void) 357 { 358 kernel_entry(0, 0, 0); /* set a2 = 0 for secondary core */ 359 } 360 361 static int octeon_update_boot_vector(unsigned int cpu) 362 { 363 364 int coreid = cpu_logical_map(cpu); 365 uint32_t avail_coremask; 366 const struct cvmx_bootmem_named_block_desc *block_desc; 367 struct boot_init_vector *boot_vect = 368 (struct boot_init_vector *)PHYS_TO_XKSEG_CACHED(BOOTLOADER_BOOT_VECTOR); 369 370 block_desc = cvmx_bootmem_find_named_block(LINUX_APP_BOOT_BLOCK_NAME); 371 372 if (!block_desc) { 373 struct linux_app_boot_info *labi; 374 375 labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER); 376 377 avail_coremask = labi->avail_coremask; 378 labi->avail_coremask &= ~(1 << coreid); 379 } else { /* alternative, already initialized */ 380 avail_coremask = *(uint32_t *)PHYS_TO_XKSEG_CACHED( 381 block_desc->base_addr + AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK); 382 } 383 384 if (!(avail_coremask & (1 << coreid))) { 385 /* core not available, assume, that caught by simple-executive */ 386 cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid); 387 cvmx_write_csr(CVMX_CIU_PP_RST, 0); 388 } 389 390 boot_vect[coreid].app_start_func_addr = 391 (uint32_t) (unsigned long) start_after_reset; 392 boot_vect[coreid].code_addr = octeon_bootloader_entry_addr; 393 394 mb(); 395 396 cvmx_write_csr(CVMX_CIU_NMI, (1 << coreid) & avail_coremask); 397 398 return 0; 399 } 400 401 static int register_cavium_notifier(void) 402 { 403 return cpuhp_setup_state_nocalls(CPUHP_MIPS_SOC_PREPARE, 404 "mips/cavium:prepare", 405 octeon_update_boot_vector, NULL); 406 } 407 late_initcall(register_cavium_notifier); 408 409 #endif /* CONFIG_HOTPLUG_CPU */ 410 411 static const struct plat_smp_ops octeon_smp_ops = { 412 .send_ipi_single = octeon_send_ipi_single, 413 .send_ipi_mask = octeon_send_ipi_mask, 414 .init_secondary = octeon_init_secondary, 415 .smp_finish = octeon_smp_finish, 416 .boot_secondary = octeon_boot_secondary, 417 .smp_setup = octeon_smp_setup, 418 .prepare_cpus = octeon_prepare_cpus, 419 #ifdef CONFIG_HOTPLUG_CPU 420 .cpu_disable = octeon_cpu_disable, 421 .cpu_die = octeon_cpu_die, 422 #endif 423 #ifdef CONFIG_KEXEC 424 .kexec_nonboot_cpu = kexec_nonboot_cpu_jump, 425 #endif 426 }; 427 428 static irqreturn_t octeon_78xx_reched_interrupt(int irq, void *dev_id) 429 { 430 scheduler_ipi(); 431 return IRQ_HANDLED; 432 } 433 434 static irqreturn_t octeon_78xx_call_function_interrupt(int irq, void *dev_id) 435 { 436 generic_smp_call_function_interrupt(); 437 return IRQ_HANDLED; 438 } 439 440 static irqreturn_t octeon_78xx_icache_flush_interrupt(int irq, void *dev_id) 441 { 442 octeon_icache_flush(); 443 return IRQ_HANDLED; 444 } 445 446 /* 447 * Callout to firmware before smp_init 448 */ 449 static void octeon_78xx_prepare_cpus(unsigned int max_cpus) 450 { 451 if (request_irq(OCTEON_IRQ_MBOX0 + 0, 452 octeon_78xx_reched_interrupt, 453 IRQF_PERCPU | IRQF_NO_THREAD, "Scheduler", 454 octeon_78xx_reched_interrupt)) { 455 panic("Cannot request_irq for SchedulerIPI"); 456 } 457 if (request_irq(OCTEON_IRQ_MBOX0 + 1, 458 octeon_78xx_call_function_interrupt, 459 IRQF_PERCPU | IRQF_NO_THREAD, "SMP-Call", 460 octeon_78xx_call_function_interrupt)) { 461 panic("Cannot request_irq for SMP-Call"); 462 } 463 if (request_irq(OCTEON_IRQ_MBOX0 + 2, 464 octeon_78xx_icache_flush_interrupt, 465 IRQF_PERCPU | IRQF_NO_THREAD, "ICache-Flush", 466 octeon_78xx_icache_flush_interrupt)) { 467 panic("Cannot request_irq for ICache-Flush"); 468 } 469 } 470 471 static void octeon_78xx_send_ipi_single(int cpu, unsigned int action) 472 { 473 int i; 474 475 for (i = 0; i < 8; i++) { 476 if (action & 1) 477 octeon_ciu3_mbox_send(cpu, i); 478 action >>= 1; 479 } 480 } 481 482 static void octeon_78xx_send_ipi_mask(const struct cpumask *mask, 483 unsigned int action) 484 { 485 unsigned int cpu; 486 487 for_each_cpu(cpu, mask) 488 octeon_78xx_send_ipi_single(cpu, action); 489 } 490 491 static const struct plat_smp_ops octeon_78xx_smp_ops = { 492 .send_ipi_single = octeon_78xx_send_ipi_single, 493 .send_ipi_mask = octeon_78xx_send_ipi_mask, 494 .init_secondary = octeon_init_secondary, 495 .smp_finish = octeon_smp_finish, 496 .boot_secondary = octeon_boot_secondary, 497 .smp_setup = octeon_smp_setup, 498 .prepare_cpus = octeon_78xx_prepare_cpus, 499 #ifdef CONFIG_HOTPLUG_CPU 500 .cpu_disable = octeon_cpu_disable, 501 .cpu_die = octeon_cpu_die, 502 #endif 503 #ifdef CONFIG_KEXEC 504 .kexec_nonboot_cpu = kexec_nonboot_cpu_jump, 505 #endif 506 }; 507 508 void __init octeon_setup_smp(void) 509 { 510 const struct plat_smp_ops *ops; 511 512 if (octeon_has_feature(OCTEON_FEATURE_CIU3)) 513 ops = &octeon_78xx_smp_ops; 514 else 515 ops = &octeon_smp_ops; 516 517 register_smp_ops(ops); 518 } 519