1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2004-2008, 2009, 2010 Cavium Networks 7 */ 8 #include <linux/cpu.h> 9 #include <linux/delay.h> 10 #include <linux/smp.h> 11 #include <linux/interrupt.h> 12 #include <linux/kernel_stat.h> 13 #include <linux/sched.h> 14 #include <linux/sched/hotplug.h> 15 #include <linux/sched/task_stack.h> 16 #include <linux/init.h> 17 #include <linux/export.h> 18 19 #include <asm/mmu_context.h> 20 #include <asm/time.h> 21 #include <asm/setup.h> 22 23 #include <asm/octeon/octeon.h> 24 25 #include "octeon_boot.h" 26 27 volatile unsigned long octeon_processor_boot = 0xff; 28 volatile unsigned long octeon_processor_sp; 29 volatile unsigned long octeon_processor_gp; 30 #ifdef CONFIG_RELOCATABLE 31 volatile unsigned long octeon_processor_relocated_kernel_entry; 32 #endif /* CONFIG_RELOCATABLE */ 33 34 #ifdef CONFIG_HOTPLUG_CPU 35 uint64_t octeon_bootloader_entry_addr; 36 EXPORT_SYMBOL(octeon_bootloader_entry_addr); 37 #endif 38 39 extern void kernel_entry(unsigned long arg1, ...); 40 41 static void octeon_icache_flush(void) 42 { 43 asm volatile ("synci 0($0)\n"); 44 } 45 46 static void (*octeon_message_functions[8])(void) = { 47 scheduler_ipi, 48 generic_smp_call_function_interrupt, 49 octeon_icache_flush, 50 }; 51 52 static irqreturn_t mailbox_interrupt(int irq, void *dev_id) 53 { 54 u64 mbox_clrx = CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()); 55 u64 action; 56 int i; 57 58 /* 59 * Make sure the function array initialization remains 60 * correct. 61 */ 62 BUILD_BUG_ON(SMP_RESCHEDULE_YOURSELF != (1 << 0)); 63 BUILD_BUG_ON(SMP_CALL_FUNCTION != (1 << 1)); 64 BUILD_BUG_ON(SMP_ICACHE_FLUSH != (1 << 2)); 65 66 /* 67 * Load the mailbox register to figure out what we're supposed 68 * to do. 69 */ 70 action = cvmx_read_csr(mbox_clrx); 71 72 if (OCTEON_IS_MODEL(OCTEON_CN68XX)) 73 action &= 0xff; 74 else 75 action &= 0xffff; 76 77 /* Clear the mailbox to clear the interrupt */ 78 cvmx_write_csr(mbox_clrx, action); 79 80 for (i = 0; i < ARRAY_SIZE(octeon_message_functions) && action;) { 81 if (action & 1) { 82 void (*fn)(void) = octeon_message_functions[i]; 83 84 if (fn) 85 fn(); 86 } 87 action >>= 1; 88 i++; 89 } 90 return IRQ_HANDLED; 91 } 92 93 /** 94 * Cause the function described by call_data to be executed on the passed 95 * cpu. When the function has finished, increment the finished field of 96 * call_data. 97 */ 98 void octeon_send_ipi_single(int cpu, unsigned int action) 99 { 100 int coreid = cpu_logical_map(cpu); 101 /* 102 pr_info("SMP: Mailbox send cpu=%d, coreid=%d, action=%u\n", cpu, 103 coreid, action); 104 */ 105 cvmx_write_csr(CVMX_CIU_MBOX_SETX(coreid), action); 106 } 107 108 static inline void octeon_send_ipi_mask(const struct cpumask *mask, 109 unsigned int action) 110 { 111 unsigned int i; 112 113 for_each_cpu(i, mask) 114 octeon_send_ipi_single(i, action); 115 } 116 117 /** 118 * Detect available CPUs, populate cpu_possible_mask 119 */ 120 static void octeon_smp_hotplug_setup(void) 121 { 122 #ifdef CONFIG_HOTPLUG_CPU 123 struct linux_app_boot_info *labi; 124 125 if (!setup_max_cpus) 126 return; 127 128 labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER); 129 if (labi->labi_signature != LABI_SIGNATURE) { 130 pr_info("The bootloader on this board does not support HOTPLUG_CPU."); 131 return; 132 } 133 134 octeon_bootloader_entry_addr = labi->InitTLBStart_addr; 135 #endif 136 } 137 138 static void __init octeon_smp_setup(void) 139 { 140 const int coreid = cvmx_get_core_num(); 141 int cpus; 142 int id; 143 struct cvmx_sysinfo *sysinfo = cvmx_sysinfo_get(); 144 145 #ifdef CONFIG_HOTPLUG_CPU 146 int core_mask = octeon_get_boot_coremask(); 147 unsigned int num_cores = cvmx_octeon_num_cores(); 148 #endif 149 150 /* The present CPUs are initially just the boot cpu (CPU 0). */ 151 for (id = 0; id < NR_CPUS; id++) { 152 set_cpu_possible(id, id == 0); 153 set_cpu_present(id, id == 0); 154 } 155 156 __cpu_number_map[coreid] = 0; 157 __cpu_logical_map[0] = coreid; 158 159 /* The present CPUs get the lowest CPU numbers. */ 160 cpus = 1; 161 for (id = 0; id < NR_CPUS; id++) { 162 if ((id != coreid) && cvmx_coremask_is_core_set(&sysinfo->core_mask, id)) { 163 set_cpu_possible(cpus, true); 164 set_cpu_present(cpus, true); 165 __cpu_number_map[id] = cpus; 166 __cpu_logical_map[cpus] = id; 167 cpus++; 168 } 169 } 170 171 #ifdef CONFIG_HOTPLUG_CPU 172 /* 173 * The possible CPUs are all those present on the chip. We 174 * will assign CPU numbers for possible cores as well. Cores 175 * are always consecutively numberd from 0. 176 */ 177 for (id = 0; setup_max_cpus && octeon_bootloader_entry_addr && 178 id < num_cores && id < NR_CPUS; id++) { 179 if (!(core_mask & (1 << id))) { 180 set_cpu_possible(cpus, true); 181 __cpu_number_map[id] = cpus; 182 __cpu_logical_map[cpus] = id; 183 cpus++; 184 } 185 } 186 #endif 187 188 octeon_smp_hotplug_setup(); 189 } 190 191 192 #ifdef CONFIG_RELOCATABLE 193 int plat_post_relocation(long offset) 194 { 195 unsigned long entry = (unsigned long)kernel_entry; 196 197 /* Send secondaries into relocated kernel */ 198 octeon_processor_relocated_kernel_entry = entry + offset; 199 200 return 0; 201 } 202 #endif /* CONFIG_RELOCATABLE */ 203 204 /** 205 * Firmware CPU startup hook 206 * 207 */ 208 static int octeon_boot_secondary(int cpu, struct task_struct *idle) 209 { 210 int count; 211 212 pr_info("SMP: Booting CPU%02d (CoreId %2d)...\n", cpu, 213 cpu_logical_map(cpu)); 214 215 octeon_processor_sp = __KSTK_TOS(idle); 216 octeon_processor_gp = (unsigned long)(task_thread_info(idle)); 217 octeon_processor_boot = cpu_logical_map(cpu); 218 mb(); 219 220 count = 10000; 221 while (octeon_processor_sp && count) { 222 /* Waiting for processor to get the SP and GP */ 223 udelay(1); 224 count--; 225 } 226 if (count == 0) { 227 pr_err("Secondary boot timeout\n"); 228 return -ETIMEDOUT; 229 } 230 231 return 0; 232 } 233 234 /** 235 * After we've done initial boot, this function is called to allow the 236 * board code to clean up state, if needed 237 */ 238 static void octeon_init_secondary(void) 239 { 240 unsigned int sr; 241 242 sr = set_c0_status(ST0_BEV); 243 write_c0_ebase((u32)ebase); 244 write_c0_status(sr); 245 246 octeon_check_cpu_bist(); 247 octeon_init_cvmcount(); 248 249 octeon_irq_setup_secondary(); 250 } 251 252 /** 253 * Callout to firmware before smp_init 254 * 255 */ 256 static void __init octeon_prepare_cpus(unsigned int max_cpus) 257 { 258 /* 259 * Only the low order mailbox bits are used for IPIs, leave 260 * the other bits alone. 261 */ 262 cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()), 0xffff); 263 if (request_irq(OCTEON_IRQ_MBOX0, mailbox_interrupt, 264 IRQF_PERCPU | IRQF_NO_THREAD, "SMP-IPI", 265 mailbox_interrupt)) { 266 panic("Cannot request_irq(OCTEON_IRQ_MBOX0)"); 267 } 268 } 269 270 /** 271 * Last chance for the board code to finish SMP initialization before 272 * the CPU is "online". 273 */ 274 static void octeon_smp_finish(void) 275 { 276 octeon_user_io_init(); 277 278 /* to generate the first CPU timer interrupt */ 279 write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ); 280 local_irq_enable(); 281 } 282 283 #ifdef CONFIG_HOTPLUG_CPU 284 285 /* State of each CPU. */ 286 DEFINE_PER_CPU(int, cpu_state); 287 288 static int octeon_cpu_disable(void) 289 { 290 unsigned int cpu = smp_processor_id(); 291 292 if (cpu == 0) 293 return -EBUSY; 294 295 if (!octeon_bootloader_entry_addr) 296 return -ENOTSUPP; 297 298 set_cpu_online(cpu, false); 299 calculate_cpu_foreign_map(); 300 octeon_fixup_irqs(); 301 302 __flush_cache_all(); 303 local_flush_tlb_all(); 304 305 return 0; 306 } 307 308 static void octeon_cpu_die(unsigned int cpu) 309 { 310 int coreid = cpu_logical_map(cpu); 311 uint32_t mask, new_mask; 312 const struct cvmx_bootmem_named_block_desc *block_desc; 313 314 while (per_cpu(cpu_state, cpu) != CPU_DEAD) 315 cpu_relax(); 316 317 /* 318 * This is a bit complicated strategics of getting/settig available 319 * cores mask, copied from bootloader 320 */ 321 322 mask = 1 << coreid; 323 /* LINUX_APP_BOOT_BLOCK is initialized in bootoct binary */ 324 block_desc = cvmx_bootmem_find_named_block(LINUX_APP_BOOT_BLOCK_NAME); 325 326 if (!block_desc) { 327 struct linux_app_boot_info *labi; 328 329 labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER); 330 331 labi->avail_coremask |= mask; 332 new_mask = labi->avail_coremask; 333 } else { /* alternative, already initialized */ 334 uint32_t *p = (uint32_t *)PHYS_TO_XKSEG_CACHED(block_desc->base_addr + 335 AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK); 336 *p |= mask; 337 new_mask = *p; 338 } 339 340 pr_info("Reset core %d. Available Coremask = 0x%x \n", coreid, new_mask); 341 mb(); 342 cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid); 343 cvmx_write_csr(CVMX_CIU_PP_RST, 0); 344 } 345 346 void play_dead(void) 347 { 348 int cpu = cpu_number_map(cvmx_get_core_num()); 349 350 idle_task_exit(); 351 octeon_processor_boot = 0xff; 352 per_cpu(cpu_state, cpu) = CPU_DEAD; 353 354 mb(); 355 356 while (1) /* core will be reset here */ 357 ; 358 } 359 360 static void start_after_reset(void) 361 { 362 kernel_entry(0, 0, 0); /* set a2 = 0 for secondary core */ 363 } 364 365 static int octeon_update_boot_vector(unsigned int cpu) 366 { 367 368 int coreid = cpu_logical_map(cpu); 369 uint32_t avail_coremask; 370 const struct cvmx_bootmem_named_block_desc *block_desc; 371 struct boot_init_vector *boot_vect = 372 (struct boot_init_vector *)PHYS_TO_XKSEG_CACHED(BOOTLOADER_BOOT_VECTOR); 373 374 block_desc = cvmx_bootmem_find_named_block(LINUX_APP_BOOT_BLOCK_NAME); 375 376 if (!block_desc) { 377 struct linux_app_boot_info *labi; 378 379 labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER); 380 381 avail_coremask = labi->avail_coremask; 382 labi->avail_coremask &= ~(1 << coreid); 383 } else { /* alternative, already initialized */ 384 avail_coremask = *(uint32_t *)PHYS_TO_XKSEG_CACHED( 385 block_desc->base_addr + AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK); 386 } 387 388 if (!(avail_coremask & (1 << coreid))) { 389 /* core not available, assume, that caught by simple-executive */ 390 cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid); 391 cvmx_write_csr(CVMX_CIU_PP_RST, 0); 392 } 393 394 boot_vect[coreid].app_start_func_addr = 395 (uint32_t) (unsigned long) start_after_reset; 396 boot_vect[coreid].code_addr = octeon_bootloader_entry_addr; 397 398 mb(); 399 400 cvmx_write_csr(CVMX_CIU_NMI, (1 << coreid) & avail_coremask); 401 402 return 0; 403 } 404 405 static int register_cavium_notifier(void) 406 { 407 return cpuhp_setup_state_nocalls(CPUHP_MIPS_SOC_PREPARE, 408 "mips/cavium:prepare", 409 octeon_update_boot_vector, NULL); 410 } 411 late_initcall(register_cavium_notifier); 412 413 #endif /* CONFIG_HOTPLUG_CPU */ 414 415 const struct plat_smp_ops octeon_smp_ops = { 416 .send_ipi_single = octeon_send_ipi_single, 417 .send_ipi_mask = octeon_send_ipi_mask, 418 .init_secondary = octeon_init_secondary, 419 .smp_finish = octeon_smp_finish, 420 .boot_secondary = octeon_boot_secondary, 421 .smp_setup = octeon_smp_setup, 422 .prepare_cpus = octeon_prepare_cpus, 423 #ifdef CONFIG_HOTPLUG_CPU 424 .cpu_disable = octeon_cpu_disable, 425 .cpu_die = octeon_cpu_die, 426 #endif 427 }; 428 429 static irqreturn_t octeon_78xx_reched_interrupt(int irq, void *dev_id) 430 { 431 scheduler_ipi(); 432 return IRQ_HANDLED; 433 } 434 435 static irqreturn_t octeon_78xx_call_function_interrupt(int irq, void *dev_id) 436 { 437 generic_smp_call_function_interrupt(); 438 return IRQ_HANDLED; 439 } 440 441 static irqreturn_t octeon_78xx_icache_flush_interrupt(int irq, void *dev_id) 442 { 443 octeon_icache_flush(); 444 return IRQ_HANDLED; 445 } 446 447 /* 448 * Callout to firmware before smp_init 449 */ 450 static void octeon_78xx_prepare_cpus(unsigned int max_cpus) 451 { 452 if (request_irq(OCTEON_IRQ_MBOX0 + 0, 453 octeon_78xx_reched_interrupt, 454 IRQF_PERCPU | IRQF_NO_THREAD, "Scheduler", 455 octeon_78xx_reched_interrupt)) { 456 panic("Cannot request_irq for SchedulerIPI"); 457 } 458 if (request_irq(OCTEON_IRQ_MBOX0 + 1, 459 octeon_78xx_call_function_interrupt, 460 IRQF_PERCPU | IRQF_NO_THREAD, "SMP-Call", 461 octeon_78xx_call_function_interrupt)) { 462 panic("Cannot request_irq for SMP-Call"); 463 } 464 if (request_irq(OCTEON_IRQ_MBOX0 + 2, 465 octeon_78xx_icache_flush_interrupt, 466 IRQF_PERCPU | IRQF_NO_THREAD, "ICache-Flush", 467 octeon_78xx_icache_flush_interrupt)) { 468 panic("Cannot request_irq for ICache-Flush"); 469 } 470 } 471 472 static void octeon_78xx_send_ipi_single(int cpu, unsigned int action) 473 { 474 int i; 475 476 for (i = 0; i < 8; i++) { 477 if (action & 1) 478 octeon_ciu3_mbox_send(cpu, i); 479 action >>= 1; 480 } 481 } 482 483 static void octeon_78xx_send_ipi_mask(const struct cpumask *mask, 484 unsigned int action) 485 { 486 unsigned int cpu; 487 488 for_each_cpu(cpu, mask) 489 octeon_78xx_send_ipi_single(cpu, action); 490 } 491 492 static const struct plat_smp_ops octeon_78xx_smp_ops = { 493 .send_ipi_single = octeon_78xx_send_ipi_single, 494 .send_ipi_mask = octeon_78xx_send_ipi_mask, 495 .init_secondary = octeon_init_secondary, 496 .smp_finish = octeon_smp_finish, 497 .boot_secondary = octeon_boot_secondary, 498 .smp_setup = octeon_smp_setup, 499 .prepare_cpus = octeon_78xx_prepare_cpus, 500 #ifdef CONFIG_HOTPLUG_CPU 501 .cpu_disable = octeon_cpu_disable, 502 .cpu_die = octeon_cpu_die, 503 #endif 504 }; 505 506 void __init octeon_setup_smp(void) 507 { 508 const struct plat_smp_ops *ops; 509 510 if (octeon_has_feature(OCTEON_FEATURE_CIU3)) 511 ops = &octeon_78xx_smp_ops; 512 else 513 ops = &octeon_smp_ops; 514 515 register_smp_ops(ops); 516 } 517