1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2004-2008, 2009, 2010 Cavium Networks 7 */ 8 #include <linux/cpu.h> 9 #include <linux/delay.h> 10 #include <linux/smp.h> 11 #include <linux/interrupt.h> 12 #include <linux/kernel_stat.h> 13 #include <linux/sched.h> 14 #include <linux/sched/hotplug.h> 15 #include <linux/sched/task_stack.h> 16 #include <linux/init.h> 17 #include <linux/export.h> 18 #include <linux/kexec.h> 19 20 #include <asm/mmu_context.h> 21 #include <asm/time.h> 22 #include <asm/setup.h> 23 24 #include <asm/octeon/octeon.h> 25 26 #include "octeon_boot.h" 27 28 volatile unsigned long octeon_processor_boot = 0xff; 29 volatile unsigned long octeon_processor_sp; 30 volatile unsigned long octeon_processor_gp; 31 #ifdef CONFIG_RELOCATABLE 32 volatile unsigned long octeon_processor_relocated_kernel_entry; 33 #endif /* CONFIG_RELOCATABLE */ 34 35 #ifdef CONFIG_HOTPLUG_CPU 36 uint64_t octeon_bootloader_entry_addr; 37 EXPORT_SYMBOL(octeon_bootloader_entry_addr); 38 #endif 39 40 extern void kernel_entry(unsigned long arg1, ...); 41 42 static void octeon_icache_flush(void) 43 { 44 asm volatile ("synci 0($0)\n"); 45 } 46 47 static void (*octeon_message_functions[8])(void) = { 48 scheduler_ipi, 49 generic_smp_call_function_interrupt, 50 octeon_icache_flush, 51 }; 52 53 static irqreturn_t mailbox_interrupt(int irq, void *dev_id) 54 { 55 u64 mbox_clrx = CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()); 56 u64 action; 57 int i; 58 59 /* 60 * Make sure the function array initialization remains 61 * correct. 62 */ 63 BUILD_BUG_ON(SMP_RESCHEDULE_YOURSELF != (1 << 0)); 64 BUILD_BUG_ON(SMP_CALL_FUNCTION != (1 << 1)); 65 BUILD_BUG_ON(SMP_ICACHE_FLUSH != (1 << 2)); 66 67 /* 68 * Load the mailbox register to figure out what we're supposed 69 * to do. 70 */ 71 action = cvmx_read_csr(mbox_clrx); 72 73 if (OCTEON_IS_MODEL(OCTEON_CN68XX)) 74 action &= 0xff; 75 else 76 action &= 0xffff; 77 78 /* Clear the mailbox to clear the interrupt */ 79 cvmx_write_csr(mbox_clrx, action); 80 81 for (i = 0; i < ARRAY_SIZE(octeon_message_functions) && action;) { 82 if (action & 1) { 83 void (*fn)(void) = octeon_message_functions[i]; 84 85 if (fn) 86 fn(); 87 } 88 action >>= 1; 89 i++; 90 } 91 return IRQ_HANDLED; 92 } 93 94 /** 95 * Cause the function described by call_data to be executed on the passed 96 * cpu. When the function has finished, increment the finished field of 97 * call_data. 98 */ 99 void octeon_send_ipi_single(int cpu, unsigned int action) 100 { 101 int coreid = cpu_logical_map(cpu); 102 /* 103 pr_info("SMP: Mailbox send cpu=%d, coreid=%d, action=%u\n", cpu, 104 coreid, action); 105 */ 106 cvmx_write_csr(CVMX_CIU_MBOX_SETX(coreid), action); 107 } 108 109 static inline void octeon_send_ipi_mask(const struct cpumask *mask, 110 unsigned int action) 111 { 112 unsigned int i; 113 114 for_each_cpu(i, mask) 115 octeon_send_ipi_single(i, action); 116 } 117 118 /** 119 * Detect available CPUs, populate cpu_possible_mask 120 */ 121 static void octeon_smp_hotplug_setup(void) 122 { 123 #ifdef CONFIG_HOTPLUG_CPU 124 struct linux_app_boot_info *labi; 125 126 if (!setup_max_cpus) 127 return; 128 129 labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER); 130 if (labi->labi_signature != LABI_SIGNATURE) { 131 pr_info("The bootloader on this board does not support HOTPLUG_CPU."); 132 return; 133 } 134 135 octeon_bootloader_entry_addr = labi->InitTLBStart_addr; 136 #endif 137 } 138 139 static void __init octeon_smp_setup(void) 140 { 141 const int coreid = cvmx_get_core_num(); 142 int cpus; 143 int id; 144 struct cvmx_sysinfo *sysinfo = cvmx_sysinfo_get(); 145 146 #ifdef CONFIG_HOTPLUG_CPU 147 int core_mask = octeon_get_boot_coremask(); 148 unsigned int num_cores = cvmx_octeon_num_cores(); 149 #endif 150 151 /* The present CPUs are initially just the boot cpu (CPU 0). */ 152 for (id = 0; id < NR_CPUS; id++) { 153 set_cpu_possible(id, id == 0); 154 set_cpu_present(id, id == 0); 155 } 156 157 __cpu_number_map[coreid] = 0; 158 __cpu_logical_map[0] = coreid; 159 160 /* The present CPUs get the lowest CPU numbers. */ 161 cpus = 1; 162 for (id = 0; id < NR_CPUS; id++) { 163 if ((id != coreid) && cvmx_coremask_is_core_set(&sysinfo->core_mask, id)) { 164 set_cpu_possible(cpus, true); 165 set_cpu_present(cpus, true); 166 __cpu_number_map[id] = cpus; 167 __cpu_logical_map[cpus] = id; 168 cpus++; 169 } 170 } 171 172 #ifdef CONFIG_HOTPLUG_CPU 173 /* 174 * The possible CPUs are all those present on the chip. We 175 * will assign CPU numbers for possible cores as well. Cores 176 * are always consecutively numberd from 0. 177 */ 178 for (id = 0; setup_max_cpus && octeon_bootloader_entry_addr && 179 id < num_cores && id < NR_CPUS; id++) { 180 if (!(core_mask & (1 << id))) { 181 set_cpu_possible(cpus, true); 182 __cpu_number_map[id] = cpus; 183 __cpu_logical_map[cpus] = id; 184 cpus++; 185 } 186 } 187 #endif 188 189 octeon_smp_hotplug_setup(); 190 } 191 192 193 #ifdef CONFIG_RELOCATABLE 194 int plat_post_relocation(long offset) 195 { 196 unsigned long entry = (unsigned long)kernel_entry; 197 198 /* Send secondaries into relocated kernel */ 199 octeon_processor_relocated_kernel_entry = entry + offset; 200 201 return 0; 202 } 203 #endif /* CONFIG_RELOCATABLE */ 204 205 /** 206 * Firmware CPU startup hook 207 * 208 */ 209 static int octeon_boot_secondary(int cpu, struct task_struct *idle) 210 { 211 int count; 212 213 pr_info("SMP: Booting CPU%02d (CoreId %2d)...\n", cpu, 214 cpu_logical_map(cpu)); 215 216 octeon_processor_sp = __KSTK_TOS(idle); 217 octeon_processor_gp = (unsigned long)(task_thread_info(idle)); 218 octeon_processor_boot = cpu_logical_map(cpu); 219 mb(); 220 221 count = 10000; 222 while (octeon_processor_sp && count) { 223 /* Waiting for processor to get the SP and GP */ 224 udelay(1); 225 count--; 226 } 227 if (count == 0) { 228 pr_err("Secondary boot timeout\n"); 229 return -ETIMEDOUT; 230 } 231 232 return 0; 233 } 234 235 /** 236 * After we've done initial boot, this function is called to allow the 237 * board code to clean up state, if needed 238 */ 239 static void octeon_init_secondary(void) 240 { 241 unsigned int sr; 242 243 sr = set_c0_status(ST0_BEV); 244 write_c0_ebase((u32)ebase); 245 write_c0_status(sr); 246 247 octeon_check_cpu_bist(); 248 octeon_init_cvmcount(); 249 250 octeon_irq_setup_secondary(); 251 } 252 253 /** 254 * Callout to firmware before smp_init 255 * 256 */ 257 static void __init octeon_prepare_cpus(unsigned int max_cpus) 258 { 259 /* 260 * Only the low order mailbox bits are used for IPIs, leave 261 * the other bits alone. 262 */ 263 cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()), 0xffff); 264 if (request_irq(OCTEON_IRQ_MBOX0, mailbox_interrupt, 265 IRQF_PERCPU | IRQF_NO_THREAD, "SMP-IPI", 266 mailbox_interrupt)) { 267 panic("Cannot request_irq(OCTEON_IRQ_MBOX0)"); 268 } 269 } 270 271 /** 272 * Last chance for the board code to finish SMP initialization before 273 * the CPU is "online". 274 */ 275 static void octeon_smp_finish(void) 276 { 277 octeon_user_io_init(); 278 279 /* to generate the first CPU timer interrupt */ 280 write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ); 281 local_irq_enable(); 282 } 283 284 #ifdef CONFIG_HOTPLUG_CPU 285 286 /* State of each CPU. */ 287 DEFINE_PER_CPU(int, cpu_state); 288 289 static int octeon_cpu_disable(void) 290 { 291 unsigned int cpu = smp_processor_id(); 292 293 if (cpu == 0) 294 return -EBUSY; 295 296 if (!octeon_bootloader_entry_addr) 297 return -ENOTSUPP; 298 299 set_cpu_online(cpu, false); 300 calculate_cpu_foreign_map(); 301 octeon_fixup_irqs(); 302 303 __flush_cache_all(); 304 local_flush_tlb_all(); 305 306 return 0; 307 } 308 309 static void octeon_cpu_die(unsigned int cpu) 310 { 311 int coreid = cpu_logical_map(cpu); 312 uint32_t mask, new_mask; 313 const struct cvmx_bootmem_named_block_desc *block_desc; 314 315 while (per_cpu(cpu_state, cpu) != CPU_DEAD) 316 cpu_relax(); 317 318 /* 319 * This is a bit complicated strategics of getting/settig available 320 * cores mask, copied from bootloader 321 */ 322 323 mask = 1 << coreid; 324 /* LINUX_APP_BOOT_BLOCK is initialized in bootoct binary */ 325 block_desc = cvmx_bootmem_find_named_block(LINUX_APP_BOOT_BLOCK_NAME); 326 327 if (!block_desc) { 328 struct linux_app_boot_info *labi; 329 330 labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER); 331 332 labi->avail_coremask |= mask; 333 new_mask = labi->avail_coremask; 334 } else { /* alternative, already initialized */ 335 uint32_t *p = (uint32_t *)PHYS_TO_XKSEG_CACHED(block_desc->base_addr + 336 AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK); 337 *p |= mask; 338 new_mask = *p; 339 } 340 341 pr_info("Reset core %d. Available Coremask = 0x%x \n", coreid, new_mask); 342 mb(); 343 cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid); 344 cvmx_write_csr(CVMX_CIU_PP_RST, 0); 345 } 346 347 void play_dead(void) 348 { 349 int cpu = cpu_number_map(cvmx_get_core_num()); 350 351 idle_task_exit(); 352 octeon_processor_boot = 0xff; 353 per_cpu(cpu_state, cpu) = CPU_DEAD; 354 355 mb(); 356 357 while (1) /* core will be reset here */ 358 ; 359 } 360 361 static void start_after_reset(void) 362 { 363 kernel_entry(0, 0, 0); /* set a2 = 0 for secondary core */ 364 } 365 366 static int octeon_update_boot_vector(unsigned int cpu) 367 { 368 369 int coreid = cpu_logical_map(cpu); 370 uint32_t avail_coremask; 371 const struct cvmx_bootmem_named_block_desc *block_desc; 372 struct boot_init_vector *boot_vect = 373 (struct boot_init_vector *)PHYS_TO_XKSEG_CACHED(BOOTLOADER_BOOT_VECTOR); 374 375 block_desc = cvmx_bootmem_find_named_block(LINUX_APP_BOOT_BLOCK_NAME); 376 377 if (!block_desc) { 378 struct linux_app_boot_info *labi; 379 380 labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER); 381 382 avail_coremask = labi->avail_coremask; 383 labi->avail_coremask &= ~(1 << coreid); 384 } else { /* alternative, already initialized */ 385 avail_coremask = *(uint32_t *)PHYS_TO_XKSEG_CACHED( 386 block_desc->base_addr + AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK); 387 } 388 389 if (!(avail_coremask & (1 << coreid))) { 390 /* core not available, assume, that caught by simple-executive */ 391 cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid); 392 cvmx_write_csr(CVMX_CIU_PP_RST, 0); 393 } 394 395 boot_vect[coreid].app_start_func_addr = 396 (uint32_t) (unsigned long) start_after_reset; 397 boot_vect[coreid].code_addr = octeon_bootloader_entry_addr; 398 399 mb(); 400 401 cvmx_write_csr(CVMX_CIU_NMI, (1 << coreid) & avail_coremask); 402 403 return 0; 404 } 405 406 static int register_cavium_notifier(void) 407 { 408 return cpuhp_setup_state_nocalls(CPUHP_MIPS_SOC_PREPARE, 409 "mips/cavium:prepare", 410 octeon_update_boot_vector, NULL); 411 } 412 late_initcall(register_cavium_notifier); 413 414 #endif /* CONFIG_HOTPLUG_CPU */ 415 416 const struct plat_smp_ops octeon_smp_ops = { 417 .send_ipi_single = octeon_send_ipi_single, 418 .send_ipi_mask = octeon_send_ipi_mask, 419 .init_secondary = octeon_init_secondary, 420 .smp_finish = octeon_smp_finish, 421 .boot_secondary = octeon_boot_secondary, 422 .smp_setup = octeon_smp_setup, 423 .prepare_cpus = octeon_prepare_cpus, 424 #ifdef CONFIG_HOTPLUG_CPU 425 .cpu_disable = octeon_cpu_disable, 426 .cpu_die = octeon_cpu_die, 427 #endif 428 #ifdef CONFIG_KEXEC 429 .kexec_nonboot_cpu = kexec_nonboot_cpu_jump, 430 #endif 431 }; 432 433 static irqreturn_t octeon_78xx_reched_interrupt(int irq, void *dev_id) 434 { 435 scheduler_ipi(); 436 return IRQ_HANDLED; 437 } 438 439 static irqreturn_t octeon_78xx_call_function_interrupt(int irq, void *dev_id) 440 { 441 generic_smp_call_function_interrupt(); 442 return IRQ_HANDLED; 443 } 444 445 static irqreturn_t octeon_78xx_icache_flush_interrupt(int irq, void *dev_id) 446 { 447 octeon_icache_flush(); 448 return IRQ_HANDLED; 449 } 450 451 /* 452 * Callout to firmware before smp_init 453 */ 454 static void octeon_78xx_prepare_cpus(unsigned int max_cpus) 455 { 456 if (request_irq(OCTEON_IRQ_MBOX0 + 0, 457 octeon_78xx_reched_interrupt, 458 IRQF_PERCPU | IRQF_NO_THREAD, "Scheduler", 459 octeon_78xx_reched_interrupt)) { 460 panic("Cannot request_irq for SchedulerIPI"); 461 } 462 if (request_irq(OCTEON_IRQ_MBOX0 + 1, 463 octeon_78xx_call_function_interrupt, 464 IRQF_PERCPU | IRQF_NO_THREAD, "SMP-Call", 465 octeon_78xx_call_function_interrupt)) { 466 panic("Cannot request_irq for SMP-Call"); 467 } 468 if (request_irq(OCTEON_IRQ_MBOX0 + 2, 469 octeon_78xx_icache_flush_interrupt, 470 IRQF_PERCPU | IRQF_NO_THREAD, "ICache-Flush", 471 octeon_78xx_icache_flush_interrupt)) { 472 panic("Cannot request_irq for ICache-Flush"); 473 } 474 } 475 476 static void octeon_78xx_send_ipi_single(int cpu, unsigned int action) 477 { 478 int i; 479 480 for (i = 0; i < 8; i++) { 481 if (action & 1) 482 octeon_ciu3_mbox_send(cpu, i); 483 action >>= 1; 484 } 485 } 486 487 static void octeon_78xx_send_ipi_mask(const struct cpumask *mask, 488 unsigned int action) 489 { 490 unsigned int cpu; 491 492 for_each_cpu(cpu, mask) 493 octeon_78xx_send_ipi_single(cpu, action); 494 } 495 496 static const struct plat_smp_ops octeon_78xx_smp_ops = { 497 .send_ipi_single = octeon_78xx_send_ipi_single, 498 .send_ipi_mask = octeon_78xx_send_ipi_mask, 499 .init_secondary = octeon_init_secondary, 500 .smp_finish = octeon_smp_finish, 501 .boot_secondary = octeon_boot_secondary, 502 .smp_setup = octeon_smp_setup, 503 .prepare_cpus = octeon_78xx_prepare_cpus, 504 #ifdef CONFIG_HOTPLUG_CPU 505 .cpu_disable = octeon_cpu_disable, 506 .cpu_die = octeon_cpu_die, 507 #endif 508 #ifdef CONFIG_KEXEC 509 .kexec_nonboot_cpu = kexec_nonboot_cpu_jump, 510 #endif 511 }; 512 513 void __init octeon_setup_smp(void) 514 { 515 const struct plat_smp_ops *ops; 516 517 if (octeon_has_feature(OCTEON_FEATURE_CIU3)) 518 ops = &octeon_78xx_smp_ops; 519 else 520 ops = &octeon_smp_ops; 521 522 register_smp_ops(ops); 523 } 524