1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2004-2008, 2009, 2010 Cavium Networks 7 */ 8 #include <linux/cpu.h> 9 #include <linux/delay.h> 10 #include <linux/smp.h> 11 #include <linux/interrupt.h> 12 #include <linux/kernel_stat.h> 13 #include <linux/sched.h> 14 #include <linux/module.h> 15 16 #include <asm/mmu_context.h> 17 #include <asm/time.h> 18 #include <asm/setup.h> 19 20 #include <asm/octeon/octeon.h> 21 22 #include "octeon_boot.h" 23 24 volatile unsigned long octeon_processor_boot = 0xff; 25 volatile unsigned long octeon_processor_sp; 26 volatile unsigned long octeon_processor_gp; 27 28 #ifdef CONFIG_HOTPLUG_CPU 29 uint64_t octeon_bootloader_entry_addr; 30 EXPORT_SYMBOL(octeon_bootloader_entry_addr); 31 #endif 32 33 static irqreturn_t mailbox_interrupt(int irq, void *dev_id) 34 { 35 const int coreid = cvmx_get_core_num(); 36 uint64_t action; 37 38 /* Load the mailbox register to figure out what we're supposed to do */ 39 action = cvmx_read_csr(CVMX_CIU_MBOX_CLRX(coreid)) & 0xffff; 40 41 /* Clear the mailbox to clear the interrupt */ 42 cvmx_write_csr(CVMX_CIU_MBOX_CLRX(coreid), action); 43 44 if (action & SMP_CALL_FUNCTION) 45 smp_call_function_interrupt(); 46 if (action & SMP_RESCHEDULE_YOURSELF) 47 scheduler_ipi(); 48 49 /* Check if we've been told to flush the icache */ 50 if (action & SMP_ICACHE_FLUSH) 51 asm volatile ("synci 0($0)\n"); 52 return IRQ_HANDLED; 53 } 54 55 /** 56 * Cause the function described by call_data to be executed on the passed 57 * cpu. When the function has finished, increment the finished field of 58 * call_data. 59 */ 60 void octeon_send_ipi_single(int cpu, unsigned int action) 61 { 62 int coreid = cpu_logical_map(cpu); 63 /* 64 pr_info("SMP: Mailbox send cpu=%d, coreid=%d, action=%u\n", cpu, 65 coreid, action); 66 */ 67 cvmx_write_csr(CVMX_CIU_MBOX_SETX(coreid), action); 68 } 69 70 static inline void octeon_send_ipi_mask(const struct cpumask *mask, 71 unsigned int action) 72 { 73 unsigned int i; 74 75 for_each_cpu_mask(i, *mask) 76 octeon_send_ipi_single(i, action); 77 } 78 79 /** 80 * Detect available CPUs, populate cpu_possible_mask 81 */ 82 static void octeon_smp_hotplug_setup(void) 83 { 84 #ifdef CONFIG_HOTPLUG_CPU 85 struct linux_app_boot_info *labi; 86 87 labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER); 88 if (labi->labi_signature != LABI_SIGNATURE) 89 panic("The bootloader version on this board is incorrect."); 90 91 octeon_bootloader_entry_addr = labi->InitTLBStart_addr; 92 #endif 93 } 94 95 static void octeon_smp_setup(void) 96 { 97 const int coreid = cvmx_get_core_num(); 98 int cpus; 99 int id; 100 int core_mask = octeon_get_boot_coremask(); 101 #ifdef CONFIG_HOTPLUG_CPU 102 unsigned int num_cores = cvmx_octeon_num_cores(); 103 #endif 104 105 /* The present CPUs are initially just the boot cpu (CPU 0). */ 106 for (id = 0; id < NR_CPUS; id++) { 107 set_cpu_possible(id, id == 0); 108 set_cpu_present(id, id == 0); 109 } 110 111 __cpu_number_map[coreid] = 0; 112 __cpu_logical_map[0] = coreid; 113 114 /* The present CPUs get the lowest CPU numbers. */ 115 cpus = 1; 116 for (id = 0; id < NR_CPUS; id++) { 117 if ((id != coreid) && (core_mask & (1 << id))) { 118 set_cpu_possible(cpus, true); 119 set_cpu_present(cpus, true); 120 __cpu_number_map[id] = cpus; 121 __cpu_logical_map[cpus] = id; 122 cpus++; 123 } 124 } 125 126 #ifdef CONFIG_HOTPLUG_CPU 127 /* 128 * The possible CPUs are all those present on the chip. We 129 * will assign CPU numbers for possible cores as well. Cores 130 * are always consecutively numberd from 0. 131 */ 132 for (id = 0; id < num_cores && id < NR_CPUS; id++) { 133 if (!(core_mask & (1 << id))) { 134 set_cpu_possible(cpus, true); 135 __cpu_number_map[id] = cpus; 136 __cpu_logical_map[cpus] = id; 137 cpus++; 138 } 139 } 140 #endif 141 142 octeon_smp_hotplug_setup(); 143 } 144 145 /** 146 * Firmware CPU startup hook 147 * 148 */ 149 static void octeon_boot_secondary(int cpu, struct task_struct *idle) 150 { 151 int count; 152 153 pr_info("SMP: Booting CPU%02d (CoreId %2d)...\n", cpu, 154 cpu_logical_map(cpu)); 155 156 octeon_processor_sp = __KSTK_TOS(idle); 157 octeon_processor_gp = (unsigned long)(task_thread_info(idle)); 158 octeon_processor_boot = cpu_logical_map(cpu); 159 mb(); 160 161 count = 10000; 162 while (octeon_processor_sp && count) { 163 /* Waiting for processor to get the SP and GP */ 164 udelay(1); 165 count--; 166 } 167 if (count == 0) 168 pr_err("Secondary boot timeout\n"); 169 } 170 171 /** 172 * After we've done initial boot, this function is called to allow the 173 * board code to clean up state, if needed 174 */ 175 static void octeon_init_secondary(void) 176 { 177 unsigned int sr; 178 179 sr = set_c0_status(ST0_BEV); 180 write_c0_ebase((u32)ebase); 181 write_c0_status(sr); 182 183 octeon_check_cpu_bist(); 184 octeon_init_cvmcount(); 185 186 octeon_irq_setup_secondary(); 187 } 188 189 /** 190 * Callout to firmware before smp_init 191 * 192 */ 193 void octeon_prepare_cpus(unsigned int max_cpus) 194 { 195 #ifdef CONFIG_HOTPLUG_CPU 196 struct linux_app_boot_info *labi; 197 198 labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER); 199 200 if (labi->labi_signature != LABI_SIGNATURE) 201 panic("The bootloader version on this board is incorrect."); 202 #endif 203 /* 204 * Only the low order mailbox bits are used for IPIs, leave 205 * the other bits alone. 206 */ 207 cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()), 0xffff); 208 if (request_irq(OCTEON_IRQ_MBOX0, mailbox_interrupt, 209 IRQF_PERCPU | IRQF_NO_THREAD, "SMP-IPI", 210 mailbox_interrupt)) { 211 panic("Cannot request_irq(OCTEON_IRQ_MBOX0)"); 212 } 213 } 214 215 /** 216 * Last chance for the board code to finish SMP initialization before 217 * the CPU is "online". 218 */ 219 static void octeon_smp_finish(void) 220 { 221 octeon_user_io_init(); 222 223 /* to generate the first CPU timer interrupt */ 224 write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ); 225 local_irq_enable(); 226 } 227 228 #ifdef CONFIG_HOTPLUG_CPU 229 230 /* State of each CPU. */ 231 DEFINE_PER_CPU(int, cpu_state); 232 233 static int octeon_cpu_disable(void) 234 { 235 unsigned int cpu = smp_processor_id(); 236 237 if (cpu == 0) 238 return -EBUSY; 239 240 set_cpu_online(cpu, false); 241 cpu_clear(cpu, cpu_callin_map); 242 local_irq_disable(); 243 octeon_fixup_irqs(); 244 local_irq_enable(); 245 246 flush_cache_all(); 247 local_flush_tlb_all(); 248 249 return 0; 250 } 251 252 static void octeon_cpu_die(unsigned int cpu) 253 { 254 int coreid = cpu_logical_map(cpu); 255 uint32_t mask, new_mask; 256 const struct cvmx_bootmem_named_block_desc *block_desc; 257 258 while (per_cpu(cpu_state, cpu) != CPU_DEAD) 259 cpu_relax(); 260 261 /* 262 * This is a bit complicated strategics of getting/settig available 263 * cores mask, copied from bootloader 264 */ 265 266 mask = 1 << coreid; 267 /* LINUX_APP_BOOT_BLOCK is initialized in bootoct binary */ 268 block_desc = cvmx_bootmem_find_named_block(LINUX_APP_BOOT_BLOCK_NAME); 269 270 if (!block_desc) { 271 struct linux_app_boot_info *labi; 272 273 labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER); 274 275 labi->avail_coremask |= mask; 276 new_mask = labi->avail_coremask; 277 } else { /* alternative, already initialized */ 278 uint32_t *p = (uint32_t *)PHYS_TO_XKSEG_CACHED(block_desc->base_addr + 279 AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK); 280 *p |= mask; 281 new_mask = *p; 282 } 283 284 pr_info("Reset core %d. Available Coremask = 0x%x \n", coreid, new_mask); 285 mb(); 286 cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid); 287 cvmx_write_csr(CVMX_CIU_PP_RST, 0); 288 } 289 290 void play_dead(void) 291 { 292 int cpu = cpu_number_map(cvmx_get_core_num()); 293 294 idle_task_exit(); 295 octeon_processor_boot = 0xff; 296 per_cpu(cpu_state, cpu) = CPU_DEAD; 297 298 mb(); 299 300 while (1) /* core will be reset here */ 301 ; 302 } 303 304 extern void kernel_entry(unsigned long arg1, ...); 305 306 static void start_after_reset(void) 307 { 308 kernel_entry(0, 0, 0); /* set a2 = 0 for secondary core */ 309 } 310 311 static int octeon_update_boot_vector(unsigned int cpu) 312 { 313 314 int coreid = cpu_logical_map(cpu); 315 uint32_t avail_coremask; 316 const struct cvmx_bootmem_named_block_desc *block_desc; 317 struct boot_init_vector *boot_vect = 318 (struct boot_init_vector *)PHYS_TO_XKSEG_CACHED(BOOTLOADER_BOOT_VECTOR); 319 320 block_desc = cvmx_bootmem_find_named_block(LINUX_APP_BOOT_BLOCK_NAME); 321 322 if (!block_desc) { 323 struct linux_app_boot_info *labi; 324 325 labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER); 326 327 avail_coremask = labi->avail_coremask; 328 labi->avail_coremask &= ~(1 << coreid); 329 } else { /* alternative, already initialized */ 330 avail_coremask = *(uint32_t *)PHYS_TO_XKSEG_CACHED( 331 block_desc->base_addr + AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK); 332 } 333 334 if (!(avail_coremask & (1 << coreid))) { 335 /* core not available, assume, that catched by simple-executive */ 336 cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid); 337 cvmx_write_csr(CVMX_CIU_PP_RST, 0); 338 } 339 340 boot_vect[coreid].app_start_func_addr = 341 (uint32_t) (unsigned long) start_after_reset; 342 boot_vect[coreid].code_addr = octeon_bootloader_entry_addr; 343 344 mb(); 345 346 cvmx_write_csr(CVMX_CIU_NMI, (1 << coreid) & avail_coremask); 347 348 return 0; 349 } 350 351 static int octeon_cpu_callback(struct notifier_block *nfb, 352 unsigned long action, void *hcpu) 353 { 354 unsigned int cpu = (unsigned long)hcpu; 355 356 switch (action) { 357 case CPU_UP_PREPARE: 358 octeon_update_boot_vector(cpu); 359 break; 360 case CPU_ONLINE: 361 pr_info("Cpu %d online\n", cpu); 362 break; 363 case CPU_DEAD: 364 break; 365 } 366 367 return NOTIFY_OK; 368 } 369 370 static int register_cavium_notifier(void) 371 { 372 hotcpu_notifier(octeon_cpu_callback, 0); 373 return 0; 374 } 375 late_initcall(register_cavium_notifier); 376 377 #endif /* CONFIG_HOTPLUG_CPU */ 378 379 struct plat_smp_ops octeon_smp_ops = { 380 .send_ipi_single = octeon_send_ipi_single, 381 .send_ipi_mask = octeon_send_ipi_mask, 382 .init_secondary = octeon_init_secondary, 383 .smp_finish = octeon_smp_finish, 384 .boot_secondary = octeon_boot_secondary, 385 .smp_setup = octeon_smp_setup, 386 .prepare_cpus = octeon_prepare_cpus, 387 #ifdef CONFIG_HOTPLUG_CPU 388 .cpu_disable = octeon_cpu_disable, 389 .cpu_die = octeon_cpu_die, 390 #endif 391 }; 392