1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2004-2008, 2009, 2010 Cavium Networks 7 */ 8 #include <linux/cpu.h> 9 #include <linux/delay.h> 10 #include <linux/smp.h> 11 #include <linux/interrupt.h> 12 #include <linux/kernel_stat.h> 13 #include <linux/sched.h> 14 #include <linux/init.h> 15 #include <linux/export.h> 16 17 #include <asm/mmu_context.h> 18 #include <asm/time.h> 19 #include <asm/setup.h> 20 21 #include <asm/octeon/octeon.h> 22 23 #include "octeon_boot.h" 24 25 volatile unsigned long octeon_processor_boot = 0xff; 26 volatile unsigned long octeon_processor_sp; 27 volatile unsigned long octeon_processor_gp; 28 #ifdef CONFIG_RELOCATABLE 29 volatile unsigned long octeon_processor_relocated_kernel_entry; 30 #endif /* CONFIG_RELOCATABLE */ 31 32 #ifdef CONFIG_HOTPLUG_CPU 33 uint64_t octeon_bootloader_entry_addr; 34 EXPORT_SYMBOL(octeon_bootloader_entry_addr); 35 #endif 36 37 extern void kernel_entry(unsigned long arg1, ...); 38 39 static void octeon_icache_flush(void) 40 { 41 asm volatile ("synci 0($0)\n"); 42 } 43 44 static void (*octeon_message_functions[8])(void) = { 45 scheduler_ipi, 46 generic_smp_call_function_interrupt, 47 octeon_icache_flush, 48 }; 49 50 static irqreturn_t mailbox_interrupt(int irq, void *dev_id) 51 { 52 u64 mbox_clrx = CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()); 53 u64 action; 54 int i; 55 56 /* 57 * Make sure the function array initialization remains 58 * correct. 59 */ 60 BUILD_BUG_ON(SMP_RESCHEDULE_YOURSELF != (1 << 0)); 61 BUILD_BUG_ON(SMP_CALL_FUNCTION != (1 << 1)); 62 BUILD_BUG_ON(SMP_ICACHE_FLUSH != (1 << 2)); 63 64 /* 65 * Load the mailbox register to figure out what we're supposed 66 * to do. 67 */ 68 action = cvmx_read_csr(mbox_clrx); 69 70 if (OCTEON_IS_MODEL(OCTEON_CN68XX)) 71 action &= 0xff; 72 else 73 action &= 0xffff; 74 75 /* Clear the mailbox to clear the interrupt */ 76 cvmx_write_csr(mbox_clrx, action); 77 78 for (i = 0; i < ARRAY_SIZE(octeon_message_functions) && action;) { 79 if (action & 1) { 80 void (*fn)(void) = octeon_message_functions[i]; 81 82 if (fn) 83 fn(); 84 } 85 action >>= 1; 86 i++; 87 } 88 return IRQ_HANDLED; 89 } 90 91 /** 92 * Cause the function described by call_data to be executed on the passed 93 * cpu. When the function has finished, increment the finished field of 94 * call_data. 95 */ 96 void octeon_send_ipi_single(int cpu, unsigned int action) 97 { 98 int coreid = cpu_logical_map(cpu); 99 /* 100 pr_info("SMP: Mailbox send cpu=%d, coreid=%d, action=%u\n", cpu, 101 coreid, action); 102 */ 103 cvmx_write_csr(CVMX_CIU_MBOX_SETX(coreid), action); 104 } 105 106 static inline void octeon_send_ipi_mask(const struct cpumask *mask, 107 unsigned int action) 108 { 109 unsigned int i; 110 111 for_each_cpu(i, mask) 112 octeon_send_ipi_single(i, action); 113 } 114 115 /** 116 * Detect available CPUs, populate cpu_possible_mask 117 */ 118 static void octeon_smp_hotplug_setup(void) 119 { 120 #ifdef CONFIG_HOTPLUG_CPU 121 struct linux_app_boot_info *labi; 122 123 if (!setup_max_cpus) 124 return; 125 126 labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER); 127 if (labi->labi_signature != LABI_SIGNATURE) { 128 pr_info("The bootloader on this board does not support HOTPLUG_CPU."); 129 return; 130 } 131 132 octeon_bootloader_entry_addr = labi->InitTLBStart_addr; 133 #endif 134 } 135 136 static void __init octeon_smp_setup(void) 137 { 138 const int coreid = cvmx_get_core_num(); 139 int cpus; 140 int id; 141 struct cvmx_sysinfo *sysinfo = cvmx_sysinfo_get(); 142 143 #ifdef CONFIG_HOTPLUG_CPU 144 int core_mask = octeon_get_boot_coremask(); 145 unsigned int num_cores = cvmx_octeon_num_cores(); 146 #endif 147 148 /* The present CPUs are initially just the boot cpu (CPU 0). */ 149 for (id = 0; id < NR_CPUS; id++) { 150 set_cpu_possible(id, id == 0); 151 set_cpu_present(id, id == 0); 152 } 153 154 __cpu_number_map[coreid] = 0; 155 __cpu_logical_map[0] = coreid; 156 157 /* The present CPUs get the lowest CPU numbers. */ 158 cpus = 1; 159 for (id = 0; id < NR_CPUS; id++) { 160 if ((id != coreid) && cvmx_coremask_is_core_set(&sysinfo->core_mask, id)) { 161 set_cpu_possible(cpus, true); 162 set_cpu_present(cpus, true); 163 __cpu_number_map[id] = cpus; 164 __cpu_logical_map[cpus] = id; 165 cpus++; 166 } 167 } 168 169 #ifdef CONFIG_HOTPLUG_CPU 170 /* 171 * The possible CPUs are all those present on the chip. We 172 * will assign CPU numbers for possible cores as well. Cores 173 * are always consecutively numberd from 0. 174 */ 175 for (id = 0; setup_max_cpus && octeon_bootloader_entry_addr && 176 id < num_cores && id < NR_CPUS; id++) { 177 if (!(core_mask & (1 << id))) { 178 set_cpu_possible(cpus, true); 179 __cpu_number_map[id] = cpus; 180 __cpu_logical_map[cpus] = id; 181 cpus++; 182 } 183 } 184 #endif 185 186 octeon_smp_hotplug_setup(); 187 } 188 189 190 #ifdef CONFIG_RELOCATABLE 191 int plat_post_relocation(long offset) 192 { 193 unsigned long entry = (unsigned long)kernel_entry; 194 195 /* Send secondaries into relocated kernel */ 196 octeon_processor_relocated_kernel_entry = entry + offset; 197 198 return 0; 199 } 200 #endif /* CONFIG_RELOCATABLE */ 201 202 /** 203 * Firmware CPU startup hook 204 * 205 */ 206 static void octeon_boot_secondary(int cpu, struct task_struct *idle) 207 { 208 int count; 209 210 pr_info("SMP: Booting CPU%02d (CoreId %2d)...\n", cpu, 211 cpu_logical_map(cpu)); 212 213 octeon_processor_sp = __KSTK_TOS(idle); 214 octeon_processor_gp = (unsigned long)(task_thread_info(idle)); 215 octeon_processor_boot = cpu_logical_map(cpu); 216 mb(); 217 218 count = 10000; 219 while (octeon_processor_sp && count) { 220 /* Waiting for processor to get the SP and GP */ 221 udelay(1); 222 count--; 223 } 224 if (count == 0) 225 pr_err("Secondary boot timeout\n"); 226 } 227 228 /** 229 * After we've done initial boot, this function is called to allow the 230 * board code to clean up state, if needed 231 */ 232 static void octeon_init_secondary(void) 233 { 234 unsigned int sr; 235 236 sr = set_c0_status(ST0_BEV); 237 write_c0_ebase((u32)ebase); 238 write_c0_status(sr); 239 240 octeon_check_cpu_bist(); 241 octeon_init_cvmcount(); 242 243 octeon_irq_setup_secondary(); 244 } 245 246 /** 247 * Callout to firmware before smp_init 248 * 249 */ 250 static void __init octeon_prepare_cpus(unsigned int max_cpus) 251 { 252 /* 253 * Only the low order mailbox bits are used for IPIs, leave 254 * the other bits alone. 255 */ 256 cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()), 0xffff); 257 if (request_irq(OCTEON_IRQ_MBOX0, mailbox_interrupt, 258 IRQF_PERCPU | IRQF_NO_THREAD, "SMP-IPI", 259 mailbox_interrupt)) { 260 panic("Cannot request_irq(OCTEON_IRQ_MBOX0)"); 261 } 262 } 263 264 /** 265 * Last chance for the board code to finish SMP initialization before 266 * the CPU is "online". 267 */ 268 static void octeon_smp_finish(void) 269 { 270 octeon_user_io_init(); 271 272 /* to generate the first CPU timer interrupt */ 273 write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ); 274 local_irq_enable(); 275 } 276 277 #ifdef CONFIG_HOTPLUG_CPU 278 279 /* State of each CPU. */ 280 DEFINE_PER_CPU(int, cpu_state); 281 282 static int octeon_cpu_disable(void) 283 { 284 unsigned int cpu = smp_processor_id(); 285 286 if (cpu == 0) 287 return -EBUSY; 288 289 if (!octeon_bootloader_entry_addr) 290 return -ENOTSUPP; 291 292 set_cpu_online(cpu, false); 293 calculate_cpu_foreign_map(); 294 octeon_fixup_irqs(); 295 296 __flush_cache_all(); 297 local_flush_tlb_all(); 298 299 return 0; 300 } 301 302 static void octeon_cpu_die(unsigned int cpu) 303 { 304 int coreid = cpu_logical_map(cpu); 305 uint32_t mask, new_mask; 306 const struct cvmx_bootmem_named_block_desc *block_desc; 307 308 while (per_cpu(cpu_state, cpu) != CPU_DEAD) 309 cpu_relax(); 310 311 /* 312 * This is a bit complicated strategics of getting/settig available 313 * cores mask, copied from bootloader 314 */ 315 316 mask = 1 << coreid; 317 /* LINUX_APP_BOOT_BLOCK is initialized in bootoct binary */ 318 block_desc = cvmx_bootmem_find_named_block(LINUX_APP_BOOT_BLOCK_NAME); 319 320 if (!block_desc) { 321 struct linux_app_boot_info *labi; 322 323 labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER); 324 325 labi->avail_coremask |= mask; 326 new_mask = labi->avail_coremask; 327 } else { /* alternative, already initialized */ 328 uint32_t *p = (uint32_t *)PHYS_TO_XKSEG_CACHED(block_desc->base_addr + 329 AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK); 330 *p |= mask; 331 new_mask = *p; 332 } 333 334 pr_info("Reset core %d. Available Coremask = 0x%x \n", coreid, new_mask); 335 mb(); 336 cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid); 337 cvmx_write_csr(CVMX_CIU_PP_RST, 0); 338 } 339 340 void play_dead(void) 341 { 342 int cpu = cpu_number_map(cvmx_get_core_num()); 343 344 idle_task_exit(); 345 octeon_processor_boot = 0xff; 346 per_cpu(cpu_state, cpu) = CPU_DEAD; 347 348 mb(); 349 350 while (1) /* core will be reset here */ 351 ; 352 } 353 354 static void start_after_reset(void) 355 { 356 kernel_entry(0, 0, 0); /* set a2 = 0 for secondary core */ 357 } 358 359 static int octeon_update_boot_vector(unsigned int cpu) 360 { 361 362 int coreid = cpu_logical_map(cpu); 363 uint32_t avail_coremask; 364 const struct cvmx_bootmem_named_block_desc *block_desc; 365 struct boot_init_vector *boot_vect = 366 (struct boot_init_vector *)PHYS_TO_XKSEG_CACHED(BOOTLOADER_BOOT_VECTOR); 367 368 block_desc = cvmx_bootmem_find_named_block(LINUX_APP_BOOT_BLOCK_NAME); 369 370 if (!block_desc) { 371 struct linux_app_boot_info *labi; 372 373 labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER); 374 375 avail_coremask = labi->avail_coremask; 376 labi->avail_coremask &= ~(1 << coreid); 377 } else { /* alternative, already initialized */ 378 avail_coremask = *(uint32_t *)PHYS_TO_XKSEG_CACHED( 379 block_desc->base_addr + AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK); 380 } 381 382 if (!(avail_coremask & (1 << coreid))) { 383 /* core not available, assume, that caught by simple-executive */ 384 cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid); 385 cvmx_write_csr(CVMX_CIU_PP_RST, 0); 386 } 387 388 boot_vect[coreid].app_start_func_addr = 389 (uint32_t) (unsigned long) start_after_reset; 390 boot_vect[coreid].code_addr = octeon_bootloader_entry_addr; 391 392 mb(); 393 394 cvmx_write_csr(CVMX_CIU_NMI, (1 << coreid) & avail_coremask); 395 396 return 0; 397 } 398 399 static int register_cavium_notifier(void) 400 { 401 return cpuhp_setup_state_nocalls(CPUHP_MIPS_SOC_PREPARE, 402 "mips/cavium:prepare", 403 octeon_update_boot_vector, NULL); 404 } 405 late_initcall(register_cavium_notifier); 406 407 #endif /* CONFIG_HOTPLUG_CPU */ 408 409 struct plat_smp_ops octeon_smp_ops = { 410 .send_ipi_single = octeon_send_ipi_single, 411 .send_ipi_mask = octeon_send_ipi_mask, 412 .init_secondary = octeon_init_secondary, 413 .smp_finish = octeon_smp_finish, 414 .boot_secondary = octeon_boot_secondary, 415 .smp_setup = octeon_smp_setup, 416 .prepare_cpus = octeon_prepare_cpus, 417 #ifdef CONFIG_HOTPLUG_CPU 418 .cpu_disable = octeon_cpu_disable, 419 .cpu_die = octeon_cpu_die, 420 #endif 421 }; 422 423 static irqreturn_t octeon_78xx_reched_interrupt(int irq, void *dev_id) 424 { 425 scheduler_ipi(); 426 return IRQ_HANDLED; 427 } 428 429 static irqreturn_t octeon_78xx_call_function_interrupt(int irq, void *dev_id) 430 { 431 generic_smp_call_function_interrupt(); 432 return IRQ_HANDLED; 433 } 434 435 static irqreturn_t octeon_78xx_icache_flush_interrupt(int irq, void *dev_id) 436 { 437 octeon_icache_flush(); 438 return IRQ_HANDLED; 439 } 440 441 /* 442 * Callout to firmware before smp_init 443 */ 444 static void octeon_78xx_prepare_cpus(unsigned int max_cpus) 445 { 446 if (request_irq(OCTEON_IRQ_MBOX0 + 0, 447 octeon_78xx_reched_interrupt, 448 IRQF_PERCPU | IRQF_NO_THREAD, "Scheduler", 449 octeon_78xx_reched_interrupt)) { 450 panic("Cannot request_irq for SchedulerIPI"); 451 } 452 if (request_irq(OCTEON_IRQ_MBOX0 + 1, 453 octeon_78xx_call_function_interrupt, 454 IRQF_PERCPU | IRQF_NO_THREAD, "SMP-Call", 455 octeon_78xx_call_function_interrupt)) { 456 panic("Cannot request_irq for SMP-Call"); 457 } 458 if (request_irq(OCTEON_IRQ_MBOX0 + 2, 459 octeon_78xx_icache_flush_interrupt, 460 IRQF_PERCPU | IRQF_NO_THREAD, "ICache-Flush", 461 octeon_78xx_icache_flush_interrupt)) { 462 panic("Cannot request_irq for ICache-Flush"); 463 } 464 } 465 466 static void octeon_78xx_send_ipi_single(int cpu, unsigned int action) 467 { 468 int i; 469 470 for (i = 0; i < 8; i++) { 471 if (action & 1) 472 octeon_ciu3_mbox_send(cpu, i); 473 action >>= 1; 474 } 475 } 476 477 static void octeon_78xx_send_ipi_mask(const struct cpumask *mask, 478 unsigned int action) 479 { 480 unsigned int cpu; 481 482 for_each_cpu(cpu, mask) 483 octeon_78xx_send_ipi_single(cpu, action); 484 } 485 486 static struct plat_smp_ops octeon_78xx_smp_ops = { 487 .send_ipi_single = octeon_78xx_send_ipi_single, 488 .send_ipi_mask = octeon_78xx_send_ipi_mask, 489 .init_secondary = octeon_init_secondary, 490 .smp_finish = octeon_smp_finish, 491 .boot_secondary = octeon_boot_secondary, 492 .smp_setup = octeon_smp_setup, 493 .prepare_cpus = octeon_78xx_prepare_cpus, 494 #ifdef CONFIG_HOTPLUG_CPU 495 .cpu_disable = octeon_cpu_disable, 496 .cpu_die = octeon_cpu_die, 497 #endif 498 }; 499 500 void __init octeon_setup_smp(void) 501 { 502 struct plat_smp_ops *ops; 503 504 if (octeon_has_feature(OCTEON_FEATURE_CIU3)) 505 ops = &octeon_78xx_smp_ops; 506 else 507 ops = &octeon_smp_ops; 508 509 register_smp_ops(ops); 510 } 511