1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2004-2007 Cavium Networks 7 * Copyright (C) 2008, 2009 Wind River Systems 8 * written by Ralf Baechle <ralf@linux-mips.org> 9 */ 10 #include <linux/compiler.h> 11 #include <linux/vmalloc.h> 12 #include <linux/init.h> 13 #include <linux/kernel.h> 14 #include <linux/console.h> 15 #include <linux/delay.h> 16 #include <linux/export.h> 17 #include <linux/interrupt.h> 18 #include <linux/io.h> 19 #include <linux/memblock.h> 20 #include <linux/serial.h> 21 #include <linux/smp.h> 22 #include <linux/types.h> 23 #include <linux/string.h> /* for memset */ 24 #include <linux/tty.h> 25 #include <linux/time.h> 26 #include <linux/platform_device.h> 27 #include <linux/serial_core.h> 28 #include <linux/serial_8250.h> 29 #include <linux/of_fdt.h> 30 #include <linux/libfdt.h> 31 #include <linux/kexec.h> 32 33 #include <asm/processor.h> 34 #include <asm/reboot.h> 35 #include <asm/smp-ops.h> 36 #include <asm/irq_cpu.h> 37 #include <asm/mipsregs.h> 38 #include <asm/bootinfo.h> 39 #include <asm/sections.h> 40 #include <asm/fw/fw.h> 41 #include <asm/setup.h> 42 #include <asm/prom.h> 43 #include <asm/time.h> 44 45 #include <asm/octeon/octeon.h> 46 #include <asm/octeon/pci-octeon.h> 47 #include <asm/octeon/cvmx-rst-defs.h> 48 49 /* 50 * TRUE for devices having registers with little-endian byte 51 * order, FALSE for registers with native-endian byte order. 52 * PCI mandates little-endian, USB and SATA are configuraable, 53 * but we chose little-endian for these. 54 */ 55 const bool octeon_should_swizzle_table[256] = { 56 [0x00] = true, /* bootbus/CF */ 57 [0x1b] = true, /* PCI mmio window */ 58 [0x1c] = true, /* PCI mmio window */ 59 [0x1d] = true, /* PCI mmio window */ 60 [0x1e] = true, /* PCI mmio window */ 61 [0x68] = true, /* OCTEON III USB */ 62 [0x69] = true, /* OCTEON III USB */ 63 [0x6c] = true, /* OCTEON III SATA */ 64 [0x6f] = true, /* OCTEON II USB */ 65 }; 66 EXPORT_SYMBOL(octeon_should_swizzle_table); 67 68 #ifdef CONFIG_PCI 69 extern void pci_console_init(const char *arg); 70 #endif 71 72 static unsigned long long max_memory = ULLONG_MAX; 73 static unsigned long long reserve_low_mem; 74 75 DEFINE_SEMAPHORE(octeon_bootbus_sem); 76 EXPORT_SYMBOL(octeon_bootbus_sem); 77 78 static struct octeon_boot_descriptor *octeon_boot_desc_ptr; 79 80 struct cvmx_bootinfo *octeon_bootinfo; 81 EXPORT_SYMBOL(octeon_bootinfo); 82 83 #ifdef CONFIG_KEXEC 84 #ifdef CONFIG_SMP 85 /* 86 * Wait for relocation code is prepared and send 87 * secondary CPUs to spin until kernel is relocated. 88 */ 89 static void octeon_kexec_smp_down(void *ignored) 90 { 91 int cpu = smp_processor_id(); 92 93 local_irq_disable(); 94 set_cpu_online(cpu, false); 95 while (!atomic_read(&kexec_ready_to_reboot)) 96 cpu_relax(); 97 98 asm volatile ( 99 " sync \n" 100 " synci ($0) \n"); 101 102 kexec_reboot(); 103 } 104 #endif 105 106 #define OCTEON_DDR0_BASE (0x0ULL) 107 #define OCTEON_DDR0_SIZE (0x010000000ULL) 108 #define OCTEON_DDR1_BASE (0x410000000ULL) 109 #define OCTEON_DDR1_SIZE (0x010000000ULL) 110 #define OCTEON_DDR2_BASE (0x020000000ULL) 111 #define OCTEON_DDR2_SIZE (0x3e0000000ULL) 112 #define OCTEON_MAX_PHY_MEM_SIZE (16*1024*1024*1024ULL) 113 114 static struct kimage *kimage_ptr; 115 116 static void kexec_bootmem_init(uint64_t mem_size, uint32_t low_reserved_bytes) 117 { 118 int64_t addr; 119 struct cvmx_bootmem_desc *bootmem_desc; 120 121 bootmem_desc = cvmx_bootmem_get_desc(); 122 123 if (mem_size > OCTEON_MAX_PHY_MEM_SIZE) { 124 mem_size = OCTEON_MAX_PHY_MEM_SIZE; 125 pr_err("Error: requested memory too large," 126 "truncating to maximum size\n"); 127 } 128 129 bootmem_desc->major_version = CVMX_BOOTMEM_DESC_MAJ_VER; 130 bootmem_desc->minor_version = CVMX_BOOTMEM_DESC_MIN_VER; 131 132 addr = (OCTEON_DDR0_BASE + reserve_low_mem + low_reserved_bytes); 133 bootmem_desc->head_addr = 0; 134 135 if (mem_size <= OCTEON_DDR0_SIZE) { 136 __cvmx_bootmem_phy_free(addr, 137 mem_size - reserve_low_mem - 138 low_reserved_bytes, 0); 139 return; 140 } 141 142 __cvmx_bootmem_phy_free(addr, 143 OCTEON_DDR0_SIZE - reserve_low_mem - 144 low_reserved_bytes, 0); 145 146 mem_size -= OCTEON_DDR0_SIZE; 147 148 if (mem_size > OCTEON_DDR1_SIZE) { 149 __cvmx_bootmem_phy_free(OCTEON_DDR1_BASE, OCTEON_DDR1_SIZE, 0); 150 __cvmx_bootmem_phy_free(OCTEON_DDR2_BASE, 151 mem_size - OCTEON_DDR1_SIZE, 0); 152 } else 153 __cvmx_bootmem_phy_free(OCTEON_DDR1_BASE, mem_size, 0); 154 } 155 156 static int octeon_kexec_prepare(struct kimage *image) 157 { 158 int i; 159 char *bootloader = "kexec"; 160 161 octeon_boot_desc_ptr->argc = 0; 162 for (i = 0; i < image->nr_segments; i++) { 163 if (!strncmp(bootloader, (char *)image->segment[i].buf, 164 strlen(bootloader))) { 165 /* 166 * convert command line string to array 167 * of parameters (as bootloader does). 168 */ 169 int argc = 0, offt; 170 char *str = (char *)image->segment[i].buf; 171 char *ptr = strchr(str, ' '); 172 while (ptr && (OCTEON_ARGV_MAX_ARGS > argc)) { 173 *ptr = '\0'; 174 if (ptr[1] != ' ') { 175 offt = (int)(ptr - str + 1); 176 octeon_boot_desc_ptr->argv[argc] = 177 image->segment[i].mem + offt; 178 argc++; 179 } 180 ptr = strchr(ptr + 1, ' '); 181 } 182 octeon_boot_desc_ptr->argc = argc; 183 break; 184 } 185 } 186 187 /* 188 * Information about segments will be needed during pre-boot memory 189 * initialization. 190 */ 191 kimage_ptr = image; 192 return 0; 193 } 194 195 static void octeon_generic_shutdown(void) 196 { 197 int i; 198 #ifdef CONFIG_SMP 199 int cpu; 200 #endif 201 struct cvmx_bootmem_desc *bootmem_desc; 202 void *named_block_array_ptr; 203 204 bootmem_desc = cvmx_bootmem_get_desc(); 205 named_block_array_ptr = 206 cvmx_phys_to_ptr(bootmem_desc->named_block_array_addr); 207 208 #ifdef CONFIG_SMP 209 /* disable watchdogs */ 210 for_each_online_cpu(cpu) 211 cvmx_write_csr(CVMX_CIU_WDOGX(cpu_logical_map(cpu)), 0); 212 #else 213 cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0); 214 #endif 215 if (kimage_ptr != kexec_crash_image) { 216 memset(named_block_array_ptr, 217 0x0, 218 CVMX_BOOTMEM_NUM_NAMED_BLOCKS * 219 sizeof(struct cvmx_bootmem_named_block_desc)); 220 /* 221 * Mark all memory (except low 0x100000 bytes) as free. 222 * It is the same thing that bootloader does. 223 */ 224 kexec_bootmem_init(octeon_bootinfo->dram_size*1024ULL*1024ULL, 225 0x100000); 226 /* 227 * Allocate all segments to avoid their corruption during boot. 228 */ 229 for (i = 0; i < kimage_ptr->nr_segments; i++) 230 cvmx_bootmem_alloc_address( 231 kimage_ptr->segment[i].memsz + 2*PAGE_SIZE, 232 kimage_ptr->segment[i].mem - PAGE_SIZE, 233 PAGE_SIZE); 234 } else { 235 /* 236 * Do not mark all memory as free. Free only named sections 237 * leaving the rest of memory unchanged. 238 */ 239 struct cvmx_bootmem_named_block_desc *ptr = 240 (struct cvmx_bootmem_named_block_desc *) 241 named_block_array_ptr; 242 243 for (i = 0; i < bootmem_desc->named_block_num_blocks; i++) 244 if (ptr[i].size) 245 cvmx_bootmem_free_named(ptr[i].name); 246 } 247 kexec_args[2] = 1UL; /* running on octeon_main_processor */ 248 kexec_args[3] = (unsigned long)octeon_boot_desc_ptr; 249 #ifdef CONFIG_SMP 250 secondary_kexec_args[2] = 0UL; /* running on secondary cpu */ 251 secondary_kexec_args[3] = (unsigned long)octeon_boot_desc_ptr; 252 #endif 253 } 254 255 static void octeon_shutdown(void) 256 { 257 octeon_generic_shutdown(); 258 #ifdef CONFIG_SMP 259 smp_call_function(octeon_kexec_smp_down, NULL, 0); 260 smp_wmb(); 261 while (num_online_cpus() > 1) { 262 cpu_relax(); 263 mdelay(1); 264 } 265 #endif 266 } 267 268 static void octeon_crash_shutdown(struct pt_regs *regs) 269 { 270 octeon_generic_shutdown(); 271 default_machine_crash_shutdown(regs); 272 } 273 274 #ifdef CONFIG_SMP 275 void octeon_crash_smp_send_stop(void) 276 { 277 int cpu; 278 279 /* disable watchdogs */ 280 for_each_online_cpu(cpu) 281 cvmx_write_csr(CVMX_CIU_WDOGX(cpu_logical_map(cpu)), 0); 282 } 283 #endif 284 285 #endif /* CONFIG_KEXEC */ 286 287 #ifdef CONFIG_CAVIUM_RESERVE32 288 uint64_t octeon_reserve32_memory; 289 EXPORT_SYMBOL(octeon_reserve32_memory); 290 #endif 291 292 #ifdef CONFIG_KEXEC 293 /* crashkernel cmdline parameter is parsed _after_ memory setup 294 * we also parse it here (workaround for EHB5200) */ 295 static uint64_t crashk_size, crashk_base; 296 #endif 297 298 static int octeon_uart; 299 300 extern asmlinkage void handle_int(void); 301 302 /** 303 * Return non zero if we are currently running in the Octeon simulator 304 * 305 * Returns 306 */ 307 int octeon_is_simulation(void) 308 { 309 return octeon_bootinfo->board_type == CVMX_BOARD_TYPE_SIM; 310 } 311 EXPORT_SYMBOL(octeon_is_simulation); 312 313 /** 314 * Return true if Octeon is in PCI Host mode. This means 315 * Linux can control the PCI bus. 316 * 317 * Returns Non zero if Octeon in host mode. 318 */ 319 int octeon_is_pci_host(void) 320 { 321 #ifdef CONFIG_PCI 322 return octeon_bootinfo->config_flags & CVMX_BOOTINFO_CFG_FLAG_PCI_HOST; 323 #else 324 return 0; 325 #endif 326 } 327 328 /** 329 * Get the clock rate of Octeon 330 * 331 * Returns Clock rate in HZ 332 */ 333 uint64_t octeon_get_clock_rate(void) 334 { 335 struct cvmx_sysinfo *sysinfo = cvmx_sysinfo_get(); 336 337 return sysinfo->cpu_clock_hz; 338 } 339 EXPORT_SYMBOL(octeon_get_clock_rate); 340 341 static u64 octeon_io_clock_rate; 342 343 u64 octeon_get_io_clock_rate(void) 344 { 345 return octeon_io_clock_rate; 346 } 347 EXPORT_SYMBOL(octeon_get_io_clock_rate); 348 349 350 /** 351 * Write to the LCD display connected to the bootbus. This display 352 * exists on most Cavium evaluation boards. If it doesn't exist, then 353 * this function doesn't do anything. 354 * 355 * @s: String to write 356 */ 357 static void octeon_write_lcd(const char *s) 358 { 359 if (octeon_bootinfo->led_display_base_addr) { 360 void __iomem *lcd_address = 361 ioremap(octeon_bootinfo->led_display_base_addr, 362 8); 363 int i; 364 for (i = 0; i < 8; i++, s++) { 365 if (*s) 366 iowrite8(*s, lcd_address + i); 367 else 368 iowrite8(' ', lcd_address + i); 369 } 370 iounmap(lcd_address); 371 } 372 } 373 374 /** 375 * Return the console uart passed by the bootloader 376 * 377 * Returns uart (0 or 1) 378 */ 379 static int octeon_get_boot_uart(void) 380 { 381 return (octeon_boot_desc_ptr->flags & OCTEON_BL_FLAG_CONSOLE_UART1) ? 382 1 : 0; 383 } 384 385 /** 386 * Get the coremask Linux was booted on. 387 * 388 * Returns Core mask 389 */ 390 int octeon_get_boot_coremask(void) 391 { 392 return octeon_boot_desc_ptr->core_mask; 393 } 394 395 /** 396 * Check the hardware BIST results for a CPU 397 */ 398 void octeon_check_cpu_bist(void) 399 { 400 const int coreid = cvmx_get_core_num(); 401 unsigned long long mask; 402 unsigned long long bist_val; 403 404 /* Check BIST results for COP0 registers */ 405 mask = 0x1f00000000ull; 406 bist_val = read_octeon_c0_icacheerr(); 407 if (bist_val & mask) 408 pr_err("Core%d BIST Failure: CacheErr(icache) = 0x%llx\n", 409 coreid, bist_val); 410 411 bist_val = read_octeon_c0_dcacheerr(); 412 if (bist_val & 1) 413 pr_err("Core%d L1 Dcache parity error: " 414 "CacheErr(dcache) = 0x%llx\n", 415 coreid, bist_val); 416 417 mask = 0xfc00000000000000ull; 418 bist_val = read_c0_cvmmemctl(); 419 if (bist_val & mask) 420 pr_err("Core%d BIST Failure: COP0_CVM_MEM_CTL = 0x%llx\n", 421 coreid, bist_val); 422 423 write_octeon_c0_dcacheerr(0); 424 } 425 426 /** 427 * Reboot Octeon 428 * 429 * @command: Command to pass to the bootloader. Currently ignored. 430 */ 431 static void octeon_restart(char *command) 432 { 433 /* Disable all watchdogs before soft reset. They don't get cleared */ 434 #ifdef CONFIG_SMP 435 int cpu; 436 for_each_online_cpu(cpu) 437 cvmx_write_csr(CVMX_CIU_WDOGX(cpu_logical_map(cpu)), 0); 438 #else 439 cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0); 440 #endif 441 442 mb(); 443 while (1) 444 if (OCTEON_IS_OCTEON3()) 445 cvmx_write_csr(CVMX_RST_SOFT_RST, 1); 446 else 447 cvmx_write_csr(CVMX_CIU_SOFT_RST, 1); 448 } 449 450 451 /** 452 * Permanently stop a core. 453 * 454 * @arg: Ignored. 455 */ 456 static void octeon_kill_core(void *arg) 457 { 458 if (octeon_is_simulation()) 459 /* A break instruction causes the simulator stop a core */ 460 asm volatile ("break" ::: "memory"); 461 462 local_irq_disable(); 463 /* Disable watchdog on this core. */ 464 cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0); 465 /* Spin in a low power mode. */ 466 while (true) 467 asm volatile ("wait" ::: "memory"); 468 } 469 470 471 /** 472 * Halt the system 473 */ 474 static void octeon_halt(void) 475 { 476 smp_call_function(octeon_kill_core, NULL, 0); 477 478 switch (octeon_bootinfo->board_type) { 479 case CVMX_BOARD_TYPE_NAO38: 480 /* Driving a 1 to GPIO 12 shuts off this board */ 481 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(12), 1); 482 cvmx_write_csr(CVMX_GPIO_TX_SET, 0x1000); 483 break; 484 default: 485 octeon_write_lcd("PowerOff"); 486 break; 487 } 488 489 octeon_kill_core(NULL); 490 } 491 492 static char __read_mostly octeon_system_type[80]; 493 494 static void __init init_octeon_system_type(void) 495 { 496 char const *board_type; 497 498 board_type = cvmx_board_type_to_string(octeon_bootinfo->board_type); 499 if (board_type == NULL) { 500 struct device_node *root; 501 int ret; 502 503 root = of_find_node_by_path("/"); 504 ret = of_property_read_string(root, "model", &board_type); 505 of_node_put(root); 506 if (ret) 507 board_type = "Unsupported Board"; 508 } 509 510 snprintf(octeon_system_type, sizeof(octeon_system_type), "%s (%s)", 511 board_type, octeon_model_get_string(read_c0_prid())); 512 } 513 514 /** 515 * Return a string representing the system type 516 * 517 * Returns 518 */ 519 const char *octeon_board_type_string(void) 520 { 521 return octeon_system_type; 522 } 523 524 const char *get_system_type(void) 525 __attribute__ ((alias("octeon_board_type_string"))); 526 527 void octeon_user_io_init(void) 528 { 529 union octeon_cvmemctl cvmmemctl; 530 531 /* Get the current settings for CP0_CVMMEMCTL_REG */ 532 cvmmemctl.u64 = read_c0_cvmmemctl(); 533 /* R/W If set, marked write-buffer entries time out the same 534 * as as other entries; if clear, marked write-buffer entries 535 * use the maximum timeout. */ 536 cvmmemctl.s.dismarkwblongto = 1; 537 /* R/W If set, a merged store does not clear the write-buffer 538 * entry timeout state. */ 539 cvmmemctl.s.dismrgclrwbto = 0; 540 /* R/W Two bits that are the MSBs of the resultant CVMSEG LM 541 * word location for an IOBDMA. The other 8 bits come from the 542 * SCRADDR field of the IOBDMA. */ 543 cvmmemctl.s.iobdmascrmsb = 0; 544 /* R/W If set, SYNCWS and SYNCS only order marked stores; if 545 * clear, SYNCWS and SYNCS only order unmarked 546 * stores. SYNCWSMARKED has no effect when DISSYNCWS is 547 * set. */ 548 cvmmemctl.s.syncwsmarked = 0; 549 /* R/W If set, SYNCWS acts as SYNCW and SYNCS acts as SYNC. */ 550 cvmmemctl.s.dissyncws = 0; 551 /* R/W If set, no stall happens on write buffer full. */ 552 if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2)) 553 cvmmemctl.s.diswbfst = 1; 554 else 555 cvmmemctl.s.diswbfst = 0; 556 /* R/W If set (and SX set), supervisor-level loads/stores can 557 * use XKPHYS addresses with <48>==0 */ 558 cvmmemctl.s.xkmemenas = 0; 559 560 /* R/W If set (and UX set), user-level loads/stores can use 561 * XKPHYS addresses with VA<48>==0 */ 562 cvmmemctl.s.xkmemenau = 0; 563 564 /* R/W If set (and SX set), supervisor-level loads/stores can 565 * use XKPHYS addresses with VA<48>==1 */ 566 cvmmemctl.s.xkioenas = 0; 567 568 /* R/W If set (and UX set), user-level loads/stores can use 569 * XKPHYS addresses with VA<48>==1 */ 570 cvmmemctl.s.xkioenau = 0; 571 572 /* R/W If set, all stores act as SYNCW (NOMERGE must be set 573 * when this is set) RW, reset to 0. */ 574 cvmmemctl.s.allsyncw = 0; 575 576 /* R/W If set, no stores merge, and all stores reach the 577 * coherent bus in order. */ 578 cvmmemctl.s.nomerge = 0; 579 /* R/W Selects the bit in the counter used for DID time-outs 0 580 * = 231, 1 = 230, 2 = 229, 3 = 214. Actual time-out is 581 * between 1x and 2x this interval. For example, with 582 * DIDTTO=3, expiration interval is between 16K and 32K. */ 583 cvmmemctl.s.didtto = 0; 584 /* R/W If set, the (mem) CSR clock never turns off. */ 585 cvmmemctl.s.csrckalwys = 0; 586 /* R/W If set, mclk never turns off. */ 587 cvmmemctl.s.mclkalwys = 0; 588 /* R/W Selects the bit in the counter used for write buffer 589 * flush time-outs (WBFLT+11) is the bit position in an 590 * internal counter used to determine expiration. The write 591 * buffer expires between 1x and 2x this interval. For 592 * example, with WBFLT = 0, a write buffer expires between 2K 593 * and 4K cycles after the write buffer entry is allocated. */ 594 cvmmemctl.s.wbfltime = 0; 595 /* R/W If set, do not put Istream in the L2 cache. */ 596 cvmmemctl.s.istrnol2 = 0; 597 598 /* 599 * R/W The write buffer threshold. As per erratum Core-14752 600 * for CN63XX, a sc/scd might fail if the write buffer is 601 * full. Lowering WBTHRESH greatly lowers the chances of the 602 * write buffer ever being full and triggering the erratum. 603 */ 604 if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X)) 605 cvmmemctl.s.wbthresh = 4; 606 else 607 cvmmemctl.s.wbthresh = 10; 608 609 /* R/W If set, CVMSEG is available for loads/stores in 610 * kernel/debug mode. */ 611 #if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0 612 cvmmemctl.s.cvmsegenak = 1; 613 #else 614 cvmmemctl.s.cvmsegenak = 0; 615 #endif 616 /* R/W If set, CVMSEG is available for loads/stores in 617 * supervisor mode. */ 618 cvmmemctl.s.cvmsegenas = 0; 619 /* R/W If set, CVMSEG is available for loads/stores in user 620 * mode. */ 621 cvmmemctl.s.cvmsegenau = 0; 622 623 write_c0_cvmmemctl(cvmmemctl.u64); 624 625 /* Setup of CVMSEG is done in kernel-entry-init.h */ 626 if (smp_processor_id() == 0) 627 pr_notice("CVMSEG size: %d cache lines (%d bytes)\n", 628 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE, 629 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128); 630 631 if (octeon_has_feature(OCTEON_FEATURE_FAU)) { 632 union cvmx_iob_fau_timeout fau_timeout; 633 634 /* Set a default for the hardware timeouts */ 635 fau_timeout.u64 = 0; 636 fau_timeout.s.tout_val = 0xfff; 637 /* Disable tagwait FAU timeout */ 638 fau_timeout.s.tout_enb = 0; 639 cvmx_write_csr(CVMX_IOB_FAU_TIMEOUT, fau_timeout.u64); 640 } 641 642 if ((!OCTEON_IS_MODEL(OCTEON_CN68XX) && 643 !OCTEON_IS_MODEL(OCTEON_CN7XXX)) || 644 OCTEON_IS_MODEL(OCTEON_CN70XX)) { 645 union cvmx_pow_nw_tim nm_tim; 646 647 nm_tim.u64 = 0; 648 /* 4096 cycles */ 649 nm_tim.s.nw_tim = 3; 650 cvmx_write_csr(CVMX_POW_NW_TIM, nm_tim.u64); 651 } 652 653 write_octeon_c0_icacheerr(0); 654 write_c0_derraddr1(0); 655 } 656 657 /** 658 * Early entry point for arch setup 659 */ 660 void __init prom_init(void) 661 { 662 struct cvmx_sysinfo *sysinfo; 663 const char *arg; 664 char *p; 665 int i; 666 u64 t; 667 int argc; 668 #ifdef CONFIG_CAVIUM_RESERVE32 669 int64_t addr = -1; 670 #endif 671 /* 672 * The bootloader passes a pointer to the boot descriptor in 673 * $a3, this is available as fw_arg3. 674 */ 675 octeon_boot_desc_ptr = (struct octeon_boot_descriptor *)fw_arg3; 676 octeon_bootinfo = 677 cvmx_phys_to_ptr(octeon_boot_desc_ptr->cvmx_desc_vaddr); 678 cvmx_bootmem_init(cvmx_phys_to_ptr(octeon_bootinfo->phy_mem_desc_addr)); 679 680 sysinfo = cvmx_sysinfo_get(); 681 memset(sysinfo, 0, sizeof(*sysinfo)); 682 sysinfo->system_dram_size = octeon_bootinfo->dram_size << 20; 683 sysinfo->phy_mem_desc_addr = (u64)phys_to_virt(octeon_bootinfo->phy_mem_desc_addr); 684 685 if ((octeon_bootinfo->major_version > 1) || 686 (octeon_bootinfo->major_version == 1 && 687 octeon_bootinfo->minor_version >= 4)) 688 cvmx_coremask_copy(&sysinfo->core_mask, 689 &octeon_bootinfo->ext_core_mask); 690 else 691 cvmx_coremask_set64(&sysinfo->core_mask, 692 octeon_bootinfo->core_mask); 693 694 /* Some broken u-boot pass garbage in upper bits, clear them out */ 695 if (!OCTEON_IS_MODEL(OCTEON_CN78XX)) 696 for (i = 512; i < 1024; i++) 697 cvmx_coremask_clear_core(&sysinfo->core_mask, i); 698 699 sysinfo->exception_base_addr = octeon_bootinfo->exception_base_addr; 700 sysinfo->cpu_clock_hz = octeon_bootinfo->eclock_hz; 701 sysinfo->dram_data_rate_hz = octeon_bootinfo->dclock_hz * 2; 702 sysinfo->board_type = octeon_bootinfo->board_type; 703 sysinfo->board_rev_major = octeon_bootinfo->board_rev_major; 704 sysinfo->board_rev_minor = octeon_bootinfo->board_rev_minor; 705 memcpy(sysinfo->mac_addr_base, octeon_bootinfo->mac_addr_base, 706 sizeof(sysinfo->mac_addr_base)); 707 sysinfo->mac_addr_count = octeon_bootinfo->mac_addr_count; 708 memcpy(sysinfo->board_serial_number, 709 octeon_bootinfo->board_serial_number, 710 sizeof(sysinfo->board_serial_number)); 711 sysinfo->compact_flash_common_base_addr = 712 octeon_bootinfo->compact_flash_common_base_addr; 713 sysinfo->compact_flash_attribute_base_addr = 714 octeon_bootinfo->compact_flash_attribute_base_addr; 715 sysinfo->led_display_base_addr = octeon_bootinfo->led_display_base_addr; 716 sysinfo->dfa_ref_clock_hz = octeon_bootinfo->dfa_ref_clock_hz; 717 sysinfo->bootloader_config_flags = octeon_bootinfo->config_flags; 718 719 if (OCTEON_IS_OCTEON2()) { 720 /* I/O clock runs at a different rate than the CPU. */ 721 union cvmx_mio_rst_boot rst_boot; 722 rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT); 723 octeon_io_clock_rate = 50000000 * rst_boot.s.pnr_mul; 724 } else if (OCTEON_IS_OCTEON3()) { 725 /* I/O clock runs at a different rate than the CPU. */ 726 union cvmx_rst_boot rst_boot; 727 rst_boot.u64 = cvmx_read_csr(CVMX_RST_BOOT); 728 octeon_io_clock_rate = 50000000 * rst_boot.s.pnr_mul; 729 } else { 730 octeon_io_clock_rate = sysinfo->cpu_clock_hz; 731 } 732 733 t = read_c0_cvmctl(); 734 if ((t & (1ull << 27)) == 0) { 735 /* 736 * Setup the multiplier save/restore code if 737 * CvmCtl[NOMUL] clear. 738 */ 739 void *save; 740 void *save_end; 741 void *restore; 742 void *restore_end; 743 int save_len; 744 int restore_len; 745 int save_max = (char *)octeon_mult_save_end - 746 (char *)octeon_mult_save; 747 int restore_max = (char *)octeon_mult_restore_end - 748 (char *)octeon_mult_restore; 749 if (current_cpu_data.cputype == CPU_CAVIUM_OCTEON3) { 750 save = octeon_mult_save3; 751 save_end = octeon_mult_save3_end; 752 restore = octeon_mult_restore3; 753 restore_end = octeon_mult_restore3_end; 754 } else { 755 save = octeon_mult_save2; 756 save_end = octeon_mult_save2_end; 757 restore = octeon_mult_restore2; 758 restore_end = octeon_mult_restore2_end; 759 } 760 save_len = (char *)save_end - (char *)save; 761 restore_len = (char *)restore_end - (char *)restore; 762 if (!WARN_ON(save_len > save_max || 763 restore_len > restore_max)) { 764 memcpy(octeon_mult_save, save, save_len); 765 memcpy(octeon_mult_restore, restore, restore_len); 766 } 767 } 768 769 /* 770 * Only enable the LED controller if we're running on a CN38XX, CN58XX, 771 * or CN56XX. The CN30XX and CN31XX don't have an LED controller. 772 */ 773 if (!octeon_is_simulation() && 774 octeon_has_feature(OCTEON_FEATURE_LED_CONTROLLER)) { 775 cvmx_write_csr(CVMX_LED_EN, 0); 776 cvmx_write_csr(CVMX_LED_PRT, 0); 777 cvmx_write_csr(CVMX_LED_DBG, 0); 778 cvmx_write_csr(CVMX_LED_PRT_FMT, 0); 779 cvmx_write_csr(CVMX_LED_UDD_CNTX(0), 32); 780 cvmx_write_csr(CVMX_LED_UDD_CNTX(1), 32); 781 cvmx_write_csr(CVMX_LED_UDD_DATX(0), 0); 782 cvmx_write_csr(CVMX_LED_UDD_DATX(1), 0); 783 cvmx_write_csr(CVMX_LED_EN, 1); 784 } 785 #ifdef CONFIG_CAVIUM_RESERVE32 786 /* 787 * We need to temporarily allocate all memory in the reserve32 788 * region. This makes sure the kernel doesn't allocate this 789 * memory when it is getting memory from the 790 * bootloader. Later, after the memory allocations are 791 * complete, the reserve32 will be freed. 792 * 793 * Allocate memory for RESERVED32 aligned on 2MB boundary. This 794 * is in case we later use hugetlb entries with it. 795 */ 796 addr = cvmx_bootmem_phy_named_block_alloc(CONFIG_CAVIUM_RESERVE32 << 20, 797 0, 0, 2 << 20, 798 "CAVIUM_RESERVE32", 0); 799 if (addr < 0) 800 pr_err("Failed to allocate CAVIUM_RESERVE32 memory area\n"); 801 else 802 octeon_reserve32_memory = addr; 803 #endif 804 805 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2 806 if (cvmx_read_csr(CVMX_L2D_FUS3) & (3ull << 34)) { 807 pr_info("Skipping L2 locking due to reduced L2 cache size\n"); 808 } else { 809 uint32_t __maybe_unused ebase = read_c0_ebase() & 0x3ffff000; 810 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_TLB 811 /* TLB refill */ 812 cvmx_l2c_lock_mem_region(ebase, 0x100); 813 #endif 814 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_EXCEPTION 815 /* General exception */ 816 cvmx_l2c_lock_mem_region(ebase + 0x180, 0x80); 817 #endif 818 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT 819 /* Interrupt handler */ 820 cvmx_l2c_lock_mem_region(ebase + 0x200, 0x80); 821 #endif 822 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_INTERRUPT 823 cvmx_l2c_lock_mem_region(__pa_symbol(handle_int), 0x100); 824 cvmx_l2c_lock_mem_region(__pa_symbol(plat_irq_dispatch), 0x80); 825 #endif 826 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_MEMCPY 827 cvmx_l2c_lock_mem_region(__pa_symbol(memcpy), 0x480); 828 #endif 829 } 830 #endif 831 832 octeon_check_cpu_bist(); 833 834 octeon_uart = octeon_get_boot_uart(); 835 836 #ifdef CONFIG_SMP 837 octeon_write_lcd("LinuxSMP"); 838 #else 839 octeon_write_lcd("Linux"); 840 #endif 841 842 octeon_setup_delays(); 843 844 /* 845 * BIST should always be enabled when doing a soft reset. L2 846 * Cache locking for instance is not cleared unless BIST is 847 * enabled. Unfortunately due to a chip errata G-200 for 848 * Cn38XX and CN31XX, BIST must be disabled on these parts. 849 */ 850 if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2) || 851 OCTEON_IS_MODEL(OCTEON_CN31XX)) 852 cvmx_write_csr(CVMX_CIU_SOFT_BIST, 0); 853 else 854 cvmx_write_csr(CVMX_CIU_SOFT_BIST, 1); 855 856 /* Default to 64MB in the simulator to speed things up */ 857 if (octeon_is_simulation()) 858 max_memory = 64ull << 20; 859 860 arg = strstr(arcs_cmdline, "mem="); 861 if (arg) { 862 max_memory = memparse(arg + 4, &p); 863 if (max_memory == 0) 864 max_memory = 32ull << 30; 865 if (*p == '@') 866 reserve_low_mem = memparse(p + 1, &p); 867 } 868 869 arcs_cmdline[0] = 0; 870 argc = octeon_boot_desc_ptr->argc; 871 for (i = 0; i < argc; i++) { 872 const char *arg = 873 cvmx_phys_to_ptr(octeon_boot_desc_ptr->argv[i]); 874 if ((strncmp(arg, "MEM=", 4) == 0) || 875 (strncmp(arg, "mem=", 4) == 0)) { 876 max_memory = memparse(arg + 4, &p); 877 if (max_memory == 0) 878 max_memory = 32ull << 30; 879 if (*p == '@') 880 reserve_low_mem = memparse(p + 1, &p); 881 #ifdef CONFIG_KEXEC 882 } else if (strncmp(arg, "crashkernel=", 12) == 0) { 883 crashk_size = memparse(arg+12, &p); 884 if (*p == '@') 885 crashk_base = memparse(p+1, &p); 886 strcat(arcs_cmdline, " "); 887 strcat(arcs_cmdline, arg); 888 /* 889 * To do: switch parsing to new style, something like: 890 * parse_crashkernel(arg, sysinfo->system_dram_size, 891 * &crashk_size, &crashk_base); 892 */ 893 #endif 894 } else if (strlen(arcs_cmdline) + strlen(arg) + 1 < 895 sizeof(arcs_cmdline) - 1) { 896 strcat(arcs_cmdline, " "); 897 strcat(arcs_cmdline, arg); 898 } 899 } 900 901 if (strstr(arcs_cmdline, "console=") == NULL) { 902 if (octeon_uart == 1) 903 strcat(arcs_cmdline, " console=ttyS1,115200"); 904 else 905 strcat(arcs_cmdline, " console=ttyS0,115200"); 906 } 907 908 mips_hpt_frequency = octeon_get_clock_rate(); 909 910 octeon_init_cvmcount(); 911 912 _machine_restart = octeon_restart; 913 _machine_halt = octeon_halt; 914 915 #ifdef CONFIG_KEXEC 916 _machine_kexec_shutdown = octeon_shutdown; 917 _machine_crash_shutdown = octeon_crash_shutdown; 918 _machine_kexec_prepare = octeon_kexec_prepare; 919 #ifdef CONFIG_SMP 920 _crash_smp_send_stop = octeon_crash_smp_send_stop; 921 #endif 922 #endif 923 924 octeon_user_io_init(); 925 octeon_setup_smp(); 926 } 927 928 /* Exclude a single page from the regions obtained in plat_mem_setup. */ 929 #ifndef CONFIG_CRASH_DUMP 930 static __init void memory_exclude_page(u64 addr, u64 *mem, u64 *size) 931 { 932 if (addr > *mem && addr < *mem + *size) { 933 u64 inc = addr - *mem; 934 memblock_add(*mem, inc); 935 *mem += inc; 936 *size -= inc; 937 } 938 939 if (addr == *mem && *size > PAGE_SIZE) { 940 *mem += PAGE_SIZE; 941 *size -= PAGE_SIZE; 942 } 943 } 944 #endif /* CONFIG_CRASH_DUMP */ 945 946 void __init fw_init_cmdline(void) 947 { 948 int i; 949 950 octeon_boot_desc_ptr = (struct octeon_boot_descriptor *)fw_arg3; 951 for (i = 0; i < octeon_boot_desc_ptr->argc; i++) { 952 const char *arg = 953 cvmx_phys_to_ptr(octeon_boot_desc_ptr->argv[i]); 954 if (strlen(arcs_cmdline) + strlen(arg) + 1 < 955 sizeof(arcs_cmdline) - 1) { 956 strcat(arcs_cmdline, " "); 957 strcat(arcs_cmdline, arg); 958 } 959 } 960 } 961 962 void __init *plat_get_fdt(void) 963 { 964 octeon_bootinfo = 965 cvmx_phys_to_ptr(octeon_boot_desc_ptr->cvmx_desc_vaddr); 966 return phys_to_virt(octeon_bootinfo->fdt_addr); 967 } 968 969 void __init plat_mem_setup(void) 970 { 971 uint64_t mem_alloc_size; 972 uint64_t total; 973 uint64_t crashk_end; 974 #ifndef CONFIG_CRASH_DUMP 975 int64_t memory; 976 uint64_t kernel_start; 977 uint64_t kernel_size; 978 #endif 979 980 total = 0; 981 crashk_end = 0; 982 983 /* 984 * The Mips memory init uses the first memory location for 985 * some memory vectors. When SPARSEMEM is in use, it doesn't 986 * verify that the size is big enough for the final 987 * vectors. Making the smallest chuck 4MB seems to be enough 988 * to consistently work. 989 */ 990 mem_alloc_size = 4 << 20; 991 if (mem_alloc_size > max_memory) 992 mem_alloc_size = max_memory; 993 994 /* Crashkernel ignores bootmem list. It relies on mem=X@Y option */ 995 #ifdef CONFIG_CRASH_DUMP 996 memblock_add(reserve_low_mem, max_memory); 997 total += max_memory; 998 #else 999 #ifdef CONFIG_KEXEC 1000 if (crashk_size > 0) { 1001 memblock_add(crashk_base, crashk_size); 1002 crashk_end = crashk_base + crashk_size; 1003 } 1004 #endif 1005 /* 1006 * When allocating memory, we want incrementing addresses, 1007 * which is handled by memblock 1008 */ 1009 cvmx_bootmem_lock(); 1010 while (total < max_memory) { 1011 memory = cvmx_bootmem_phy_alloc(mem_alloc_size, 1012 __pa_symbol(&_end), -1, 1013 0x100000, 1014 CVMX_BOOTMEM_FLAG_NO_LOCKING); 1015 if (memory >= 0) { 1016 u64 size = mem_alloc_size; 1017 #ifdef CONFIG_KEXEC 1018 uint64_t end; 1019 #endif 1020 1021 /* 1022 * exclude a page at the beginning and end of 1023 * the 256MB PCIe 'hole' so the kernel will not 1024 * try to allocate multi-page buffers that 1025 * span the discontinuity. 1026 */ 1027 memory_exclude_page(CVMX_PCIE_BAR1_PHYS_BASE, 1028 &memory, &size); 1029 memory_exclude_page(CVMX_PCIE_BAR1_PHYS_BASE + 1030 CVMX_PCIE_BAR1_PHYS_SIZE, 1031 &memory, &size); 1032 #ifdef CONFIG_KEXEC 1033 end = memory + mem_alloc_size; 1034 1035 /* 1036 * This function automatically merges address regions 1037 * next to each other if they are received in 1038 * incrementing order 1039 */ 1040 if (memory < crashk_base && end > crashk_end) { 1041 /* region is fully in */ 1042 memblock_add(memory, crashk_base - memory); 1043 total += crashk_base - memory; 1044 memblock_add(crashk_end, end - crashk_end); 1045 total += end - crashk_end; 1046 continue; 1047 } 1048 1049 if (memory >= crashk_base && end <= crashk_end) 1050 /* 1051 * Entire memory region is within the new 1052 * kernel's memory, ignore it. 1053 */ 1054 continue; 1055 1056 if (memory > crashk_base && memory < crashk_end && 1057 end > crashk_end) { 1058 /* 1059 * Overlap with the beginning of the region, 1060 * reserve the beginning. 1061 */ 1062 mem_alloc_size -= crashk_end - memory; 1063 memory = crashk_end; 1064 } else if (memory < crashk_base && end > crashk_base && 1065 end < crashk_end) 1066 /* 1067 * Overlap with the beginning of the region, 1068 * chop of end. 1069 */ 1070 mem_alloc_size -= end - crashk_base; 1071 #endif 1072 memblock_add(memory, mem_alloc_size); 1073 total += mem_alloc_size; 1074 /* Recovering mem_alloc_size */ 1075 mem_alloc_size = 4 << 20; 1076 } else { 1077 break; 1078 } 1079 } 1080 cvmx_bootmem_unlock(); 1081 /* Add the memory region for the kernel. */ 1082 kernel_start = (unsigned long) _text; 1083 kernel_size = _end - _text; 1084 1085 /* Adjust for physical offset. */ 1086 kernel_start &= ~0xffffffff80000000ULL; 1087 memblock_add(kernel_start, kernel_size); 1088 #endif /* CONFIG_CRASH_DUMP */ 1089 1090 #ifdef CONFIG_CAVIUM_RESERVE32 1091 /* 1092 * Now that we've allocated the kernel memory it is safe to 1093 * free the reserved region. We free it here so that builtin 1094 * drivers can use the memory. 1095 */ 1096 if (octeon_reserve32_memory) 1097 cvmx_bootmem_free_named("CAVIUM_RESERVE32"); 1098 #endif /* CONFIG_CAVIUM_RESERVE32 */ 1099 1100 if (total == 0) 1101 panic("Unable to allocate memory from " 1102 "cvmx_bootmem_phy_alloc"); 1103 } 1104 1105 /* 1106 * Emit one character to the boot UART. Exported for use by the 1107 * watchdog timer. 1108 */ 1109 void prom_putchar(char c) 1110 { 1111 uint64_t lsrval; 1112 1113 /* Spin until there is room */ 1114 do { 1115 lsrval = cvmx_read_csr(CVMX_MIO_UARTX_LSR(octeon_uart)); 1116 } while ((lsrval & 0x20) == 0); 1117 1118 /* Write the byte */ 1119 cvmx_write_csr(CVMX_MIO_UARTX_THR(octeon_uart), c & 0xffull); 1120 } 1121 EXPORT_SYMBOL(prom_putchar); 1122 1123 void __init prom_free_prom_memory(void) 1124 { 1125 if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) { 1126 /* Check for presence of Core-14449 fix. */ 1127 u32 insn; 1128 u32 *foo; 1129 1130 foo = &insn; 1131 1132 asm volatile("# before" : : : "memory"); 1133 prefetch(foo); 1134 asm volatile( 1135 ".set push\n\t" 1136 ".set noreorder\n\t" 1137 "bal 1f\n\t" 1138 "nop\n" 1139 "1:\tlw %0,-12($31)\n\t" 1140 ".set pop\n\t" 1141 : "=r" (insn) : : "$31", "memory"); 1142 1143 if ((insn >> 26) != 0x33) 1144 panic("No PREF instruction at Core-14449 probe point."); 1145 1146 if (((insn >> 16) & 0x1f) != 28) 1147 panic("OCTEON II DCache prefetch workaround not in place (%04x).\n" 1148 "Please build kernel with proper options (CONFIG_CAVIUM_CN63XXP1).", 1149 insn); 1150 } 1151 } 1152 1153 void __init octeon_fill_mac_addresses(void); 1154 1155 void __init device_tree_init(void) 1156 { 1157 const void *fdt; 1158 bool do_prune; 1159 bool fill_mac; 1160 1161 if (fw_passed_dtb) { 1162 fdt = (void *)fw_passed_dtb; 1163 do_prune = false; 1164 fill_mac = true; 1165 pr_info("Using appended Device Tree.\n"); 1166 } else if (octeon_bootinfo->minor_version >= 3 && octeon_bootinfo->fdt_addr) { 1167 fdt = phys_to_virt(octeon_bootinfo->fdt_addr); 1168 if (fdt_check_header(fdt)) 1169 panic("Corrupt Device Tree passed to kernel."); 1170 do_prune = false; 1171 fill_mac = false; 1172 pr_info("Using passed Device Tree.\n"); 1173 } else if (OCTEON_IS_MODEL(OCTEON_CN68XX)) { 1174 fdt = &__dtb_octeon_68xx_begin; 1175 do_prune = true; 1176 fill_mac = true; 1177 } else { 1178 fdt = &__dtb_octeon_3xxx_begin; 1179 do_prune = true; 1180 fill_mac = true; 1181 } 1182 1183 initial_boot_params = (void *)fdt; 1184 1185 if (do_prune) { 1186 octeon_prune_device_tree(); 1187 pr_info("Using internal Device Tree.\n"); 1188 } 1189 if (fill_mac) 1190 octeon_fill_mac_addresses(); 1191 unflatten_and_copy_device_tree(); 1192 init_octeon_system_type(); 1193 } 1194 1195 static int __initdata disable_octeon_edac_p; 1196 1197 static int __init disable_octeon_edac(char *str) 1198 { 1199 disable_octeon_edac_p = 1; 1200 return 0; 1201 } 1202 early_param("disable_octeon_edac", disable_octeon_edac); 1203 1204 static char *edac_device_names[] = { 1205 "octeon_l2c_edac", 1206 "octeon_pc_edac", 1207 }; 1208 1209 static int __init edac_devinit(void) 1210 { 1211 struct platform_device *dev; 1212 int i, err = 0; 1213 int num_lmc; 1214 char *name; 1215 1216 if (disable_octeon_edac_p) 1217 return 0; 1218 1219 for (i = 0; i < ARRAY_SIZE(edac_device_names); i++) { 1220 name = edac_device_names[i]; 1221 dev = platform_device_register_simple(name, -1, NULL, 0); 1222 if (IS_ERR(dev)) { 1223 pr_err("Registration of %s failed!\n", name); 1224 err = PTR_ERR(dev); 1225 } 1226 } 1227 1228 num_lmc = OCTEON_IS_MODEL(OCTEON_CN68XX) ? 4 : 1229 (OCTEON_IS_MODEL(OCTEON_CN56XX) ? 2 : 1); 1230 for (i = 0; i < num_lmc; i++) { 1231 dev = platform_device_register_simple("octeon_lmc_edac", 1232 i, NULL, 0); 1233 if (IS_ERR(dev)) { 1234 pr_err("Registration of octeon_lmc_edac %d failed!\n", i); 1235 err = PTR_ERR(dev); 1236 } 1237 } 1238 1239 return err; 1240 } 1241 device_initcall(edac_devinit); 1242 1243 static void __initdata *octeon_dummy_iospace; 1244 1245 static int __init octeon_no_pci_init(void) 1246 { 1247 /* 1248 * Initially assume there is no PCI. The PCI/PCIe platform code will 1249 * later re-initialize these to correct values if they are present. 1250 */ 1251 octeon_dummy_iospace = vzalloc(IO_SPACE_LIMIT); 1252 set_io_port_base((unsigned long)octeon_dummy_iospace); 1253 ioport_resource.start = MAX_RESOURCE; 1254 ioport_resource.end = 0; 1255 return 0; 1256 } 1257 core_initcall(octeon_no_pci_init); 1258 1259 static int __init octeon_no_pci_release(void) 1260 { 1261 /* 1262 * Release the allocated memory if a real IO space is there. 1263 */ 1264 if ((unsigned long)octeon_dummy_iospace != mips_io_port_base) 1265 vfree(octeon_dummy_iospace); 1266 return 0; 1267 } 1268 late_initcall(octeon_no_pci_release); 1269