1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2004-2007 Cavium Networks 7 * Copyright (C) 2008, 2009 Wind River Systems 8 * written by Ralf Baechle <ralf@linux-mips.org> 9 */ 10 #include <linux/compiler.h> 11 #include <linux/vmalloc.h> 12 #include <linux/init.h> 13 #include <linux/kernel.h> 14 #include <linux/console.h> 15 #include <linux/delay.h> 16 #include <linux/export.h> 17 #include <linux/interrupt.h> 18 #include <linux/io.h> 19 #include <linux/serial.h> 20 #include <linux/smp.h> 21 #include <linux/types.h> 22 #include <linux/string.h> /* for memset */ 23 #include <linux/tty.h> 24 #include <linux/time.h> 25 #include <linux/platform_device.h> 26 #include <linux/serial_core.h> 27 #include <linux/serial_8250.h> 28 #include <linux/of_fdt.h> 29 #include <linux/libfdt.h> 30 #include <linux/kexec.h> 31 32 #include <asm/processor.h> 33 #include <asm/reboot.h> 34 #include <asm/smp-ops.h> 35 #include <asm/irq_cpu.h> 36 #include <asm/mipsregs.h> 37 #include <asm/bootinfo.h> 38 #include <asm/sections.h> 39 #include <asm/time.h> 40 41 #include <asm/octeon/octeon.h> 42 #include <asm/octeon/pci-octeon.h> 43 #include <asm/octeon/cvmx-mio-defs.h> 44 #include <asm/octeon/cvmx-rst-defs.h> 45 46 #ifdef CONFIG_PCI 47 extern void pci_console_init(const char *arg); 48 #endif 49 50 static unsigned long long MAX_MEMORY = 512ull << 20; 51 52 DEFINE_SEMAPHORE(octeon_bootbus_sem); 53 EXPORT_SYMBOL(octeon_bootbus_sem); 54 55 struct octeon_boot_descriptor *octeon_boot_desc_ptr; 56 57 struct cvmx_bootinfo *octeon_bootinfo; 58 EXPORT_SYMBOL(octeon_bootinfo); 59 60 static unsigned long long RESERVE_LOW_MEM = 0ull; 61 #ifdef CONFIG_KEXEC 62 #ifdef CONFIG_SMP 63 /* 64 * Wait for relocation code is prepared and send 65 * secondary CPUs to spin until kernel is relocated. 66 */ 67 static void octeon_kexec_smp_down(void *ignored) 68 { 69 int cpu = smp_processor_id(); 70 71 local_irq_disable(); 72 set_cpu_online(cpu, false); 73 while (!atomic_read(&kexec_ready_to_reboot)) 74 cpu_relax(); 75 76 asm volatile ( 77 " sync \n" 78 " synci ($0) \n"); 79 80 relocated_kexec_smp_wait(NULL); 81 } 82 #endif 83 84 #define OCTEON_DDR0_BASE (0x0ULL) 85 #define OCTEON_DDR0_SIZE (0x010000000ULL) 86 #define OCTEON_DDR1_BASE (0x410000000ULL) 87 #define OCTEON_DDR1_SIZE (0x010000000ULL) 88 #define OCTEON_DDR2_BASE (0x020000000ULL) 89 #define OCTEON_DDR2_SIZE (0x3e0000000ULL) 90 #define OCTEON_MAX_PHY_MEM_SIZE (16*1024*1024*1024ULL) 91 92 static struct kimage *kimage_ptr; 93 94 static void kexec_bootmem_init(uint64_t mem_size, uint32_t low_reserved_bytes) 95 { 96 int64_t addr; 97 struct cvmx_bootmem_desc *bootmem_desc; 98 99 bootmem_desc = cvmx_bootmem_get_desc(); 100 101 if (mem_size > OCTEON_MAX_PHY_MEM_SIZE) { 102 mem_size = OCTEON_MAX_PHY_MEM_SIZE; 103 pr_err("Error: requested memory too large," 104 "truncating to maximum size\n"); 105 } 106 107 bootmem_desc->major_version = CVMX_BOOTMEM_DESC_MAJ_VER; 108 bootmem_desc->minor_version = CVMX_BOOTMEM_DESC_MIN_VER; 109 110 addr = (OCTEON_DDR0_BASE + RESERVE_LOW_MEM + low_reserved_bytes); 111 bootmem_desc->head_addr = 0; 112 113 if (mem_size <= OCTEON_DDR0_SIZE) { 114 __cvmx_bootmem_phy_free(addr, 115 mem_size - RESERVE_LOW_MEM - 116 low_reserved_bytes, 0); 117 return; 118 } 119 120 __cvmx_bootmem_phy_free(addr, 121 OCTEON_DDR0_SIZE - RESERVE_LOW_MEM - 122 low_reserved_bytes, 0); 123 124 mem_size -= OCTEON_DDR0_SIZE; 125 126 if (mem_size > OCTEON_DDR1_SIZE) { 127 __cvmx_bootmem_phy_free(OCTEON_DDR1_BASE, OCTEON_DDR1_SIZE, 0); 128 __cvmx_bootmem_phy_free(OCTEON_DDR2_BASE, 129 mem_size - OCTEON_DDR1_SIZE, 0); 130 } else 131 __cvmx_bootmem_phy_free(OCTEON_DDR1_BASE, mem_size, 0); 132 } 133 134 static int octeon_kexec_prepare(struct kimage *image) 135 { 136 int i; 137 char *bootloader = "kexec"; 138 139 octeon_boot_desc_ptr->argc = 0; 140 for (i = 0; i < image->nr_segments; i++) { 141 if (!strncmp(bootloader, (char *)image->segment[i].buf, 142 strlen(bootloader))) { 143 /* 144 * convert command line string to array 145 * of parameters (as bootloader does). 146 */ 147 int argc = 0, offt; 148 char *str = (char *)image->segment[i].buf; 149 char *ptr = strchr(str, ' '); 150 while (ptr && (OCTEON_ARGV_MAX_ARGS > argc)) { 151 *ptr = '\0'; 152 if (ptr[1] != ' ') { 153 offt = (int)(ptr - str + 1); 154 octeon_boot_desc_ptr->argv[argc] = 155 image->segment[i].mem + offt; 156 argc++; 157 } 158 ptr = strchr(ptr + 1, ' '); 159 } 160 octeon_boot_desc_ptr->argc = argc; 161 break; 162 } 163 } 164 165 /* 166 * Information about segments will be needed during pre-boot memory 167 * initialization. 168 */ 169 kimage_ptr = image; 170 return 0; 171 } 172 173 static void octeon_generic_shutdown(void) 174 { 175 int i; 176 #ifdef CONFIG_SMP 177 int cpu; 178 #endif 179 struct cvmx_bootmem_desc *bootmem_desc; 180 void *named_block_array_ptr; 181 182 bootmem_desc = cvmx_bootmem_get_desc(); 183 named_block_array_ptr = 184 cvmx_phys_to_ptr(bootmem_desc->named_block_array_addr); 185 186 #ifdef CONFIG_SMP 187 /* disable watchdogs */ 188 for_each_online_cpu(cpu) 189 cvmx_write_csr(CVMX_CIU_WDOGX(cpu_logical_map(cpu)), 0); 190 #else 191 cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0); 192 #endif 193 if (kimage_ptr != kexec_crash_image) { 194 memset(named_block_array_ptr, 195 0x0, 196 CVMX_BOOTMEM_NUM_NAMED_BLOCKS * 197 sizeof(struct cvmx_bootmem_named_block_desc)); 198 /* 199 * Mark all memory (except low 0x100000 bytes) as free. 200 * It is the same thing that bootloader does. 201 */ 202 kexec_bootmem_init(octeon_bootinfo->dram_size*1024ULL*1024ULL, 203 0x100000); 204 /* 205 * Allocate all segments to avoid their corruption during boot. 206 */ 207 for (i = 0; i < kimage_ptr->nr_segments; i++) 208 cvmx_bootmem_alloc_address( 209 kimage_ptr->segment[i].memsz + 2*PAGE_SIZE, 210 kimage_ptr->segment[i].mem - PAGE_SIZE, 211 PAGE_SIZE); 212 } else { 213 /* 214 * Do not mark all memory as free. Free only named sections 215 * leaving the rest of memory unchanged. 216 */ 217 struct cvmx_bootmem_named_block_desc *ptr = 218 (struct cvmx_bootmem_named_block_desc *) 219 named_block_array_ptr; 220 221 for (i = 0; i < bootmem_desc->named_block_num_blocks; i++) 222 if (ptr[i].size) 223 cvmx_bootmem_free_named(ptr[i].name); 224 } 225 kexec_args[2] = 1UL; /* running on octeon_main_processor */ 226 kexec_args[3] = (unsigned long)octeon_boot_desc_ptr; 227 #ifdef CONFIG_SMP 228 secondary_kexec_args[2] = 0UL; /* running on secondary cpu */ 229 secondary_kexec_args[3] = (unsigned long)octeon_boot_desc_ptr; 230 #endif 231 } 232 233 static void octeon_shutdown(void) 234 { 235 octeon_generic_shutdown(); 236 #ifdef CONFIG_SMP 237 smp_call_function(octeon_kexec_smp_down, NULL, 0); 238 smp_wmb(); 239 while (num_online_cpus() > 1) { 240 cpu_relax(); 241 mdelay(1); 242 } 243 #endif 244 } 245 246 static void octeon_crash_shutdown(struct pt_regs *regs) 247 { 248 octeon_generic_shutdown(); 249 default_machine_crash_shutdown(regs); 250 } 251 252 #endif /* CONFIG_KEXEC */ 253 254 #ifdef CONFIG_CAVIUM_RESERVE32 255 uint64_t octeon_reserve32_memory; 256 EXPORT_SYMBOL(octeon_reserve32_memory); 257 #endif 258 259 #ifdef CONFIG_KEXEC 260 /* crashkernel cmdline parameter is parsed _after_ memory setup 261 * we also parse it here (workaround for EHB5200) */ 262 static uint64_t crashk_size, crashk_base; 263 #endif 264 265 static int octeon_uart; 266 267 extern asmlinkage void handle_int(void); 268 269 /** 270 * Return non zero if we are currently running in the Octeon simulator 271 * 272 * Returns 273 */ 274 int octeon_is_simulation(void) 275 { 276 return octeon_bootinfo->board_type == CVMX_BOARD_TYPE_SIM; 277 } 278 EXPORT_SYMBOL(octeon_is_simulation); 279 280 /** 281 * Return true if Octeon is in PCI Host mode. This means 282 * Linux can control the PCI bus. 283 * 284 * Returns Non zero if Octeon in host mode. 285 */ 286 int octeon_is_pci_host(void) 287 { 288 #ifdef CONFIG_PCI 289 return octeon_bootinfo->config_flags & CVMX_BOOTINFO_CFG_FLAG_PCI_HOST; 290 #else 291 return 0; 292 #endif 293 } 294 295 /** 296 * Get the clock rate of Octeon 297 * 298 * Returns Clock rate in HZ 299 */ 300 uint64_t octeon_get_clock_rate(void) 301 { 302 struct cvmx_sysinfo *sysinfo = cvmx_sysinfo_get(); 303 304 return sysinfo->cpu_clock_hz; 305 } 306 EXPORT_SYMBOL(octeon_get_clock_rate); 307 308 static u64 octeon_io_clock_rate; 309 310 u64 octeon_get_io_clock_rate(void) 311 { 312 return octeon_io_clock_rate; 313 } 314 EXPORT_SYMBOL(octeon_get_io_clock_rate); 315 316 317 /** 318 * Write to the LCD display connected to the bootbus. This display 319 * exists on most Cavium evaluation boards. If it doesn't exist, then 320 * this function doesn't do anything. 321 * 322 * @s: String to write 323 */ 324 void octeon_write_lcd(const char *s) 325 { 326 if (octeon_bootinfo->led_display_base_addr) { 327 void __iomem *lcd_address = 328 ioremap_nocache(octeon_bootinfo->led_display_base_addr, 329 8); 330 int i; 331 for (i = 0; i < 8; i++, s++) { 332 if (*s) 333 iowrite8(*s, lcd_address + i); 334 else 335 iowrite8(' ', lcd_address + i); 336 } 337 iounmap(lcd_address); 338 } 339 } 340 341 /** 342 * Return the console uart passed by the bootloader 343 * 344 * Returns uart (0 or 1) 345 */ 346 int octeon_get_boot_uart(void) 347 { 348 int uart; 349 #ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL 350 uart = 1; 351 #else 352 uart = (octeon_boot_desc_ptr->flags & OCTEON_BL_FLAG_CONSOLE_UART1) ? 353 1 : 0; 354 #endif 355 return uart; 356 } 357 358 /** 359 * Get the coremask Linux was booted on. 360 * 361 * Returns Core mask 362 */ 363 int octeon_get_boot_coremask(void) 364 { 365 return octeon_boot_desc_ptr->core_mask; 366 } 367 368 /** 369 * Check the hardware BIST results for a CPU 370 */ 371 void octeon_check_cpu_bist(void) 372 { 373 const int coreid = cvmx_get_core_num(); 374 unsigned long long mask; 375 unsigned long long bist_val; 376 377 /* Check BIST results for COP0 registers */ 378 mask = 0x1f00000000ull; 379 bist_val = read_octeon_c0_icacheerr(); 380 if (bist_val & mask) 381 pr_err("Core%d BIST Failure: CacheErr(icache) = 0x%llx\n", 382 coreid, bist_val); 383 384 bist_val = read_octeon_c0_dcacheerr(); 385 if (bist_val & 1) 386 pr_err("Core%d L1 Dcache parity error: " 387 "CacheErr(dcache) = 0x%llx\n", 388 coreid, bist_val); 389 390 mask = 0xfc00000000000000ull; 391 bist_val = read_c0_cvmmemctl(); 392 if (bist_val & mask) 393 pr_err("Core%d BIST Failure: COP0_CVM_MEM_CTL = 0x%llx\n", 394 coreid, bist_val); 395 396 write_octeon_c0_dcacheerr(0); 397 } 398 399 /** 400 * Reboot Octeon 401 * 402 * @command: Command to pass to the bootloader. Currently ignored. 403 */ 404 static void octeon_restart(char *command) 405 { 406 /* Disable all watchdogs before soft reset. They don't get cleared */ 407 #ifdef CONFIG_SMP 408 int cpu; 409 for_each_online_cpu(cpu) 410 cvmx_write_csr(CVMX_CIU_WDOGX(cpu_logical_map(cpu)), 0); 411 #else 412 cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0); 413 #endif 414 415 mb(); 416 while (1) 417 if (OCTEON_IS_OCTEON3()) 418 cvmx_write_csr(CVMX_RST_SOFT_RST, 1); 419 else 420 cvmx_write_csr(CVMX_CIU_SOFT_RST, 1); 421 } 422 423 424 /** 425 * Permanently stop a core. 426 * 427 * @arg: Ignored. 428 */ 429 static void octeon_kill_core(void *arg) 430 { 431 if (octeon_is_simulation()) 432 /* A break instruction causes the simulator stop a core */ 433 asm volatile ("break" ::: "memory"); 434 435 local_irq_disable(); 436 /* Disable watchdog on this core. */ 437 cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0); 438 /* Spin in a low power mode. */ 439 while (true) 440 asm volatile ("wait" ::: "memory"); 441 } 442 443 444 /** 445 * Halt the system 446 */ 447 static void octeon_halt(void) 448 { 449 smp_call_function(octeon_kill_core, NULL, 0); 450 451 switch (octeon_bootinfo->board_type) { 452 case CVMX_BOARD_TYPE_NAO38: 453 /* Driving a 1 to GPIO 12 shuts off this board */ 454 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(12), 1); 455 cvmx_write_csr(CVMX_GPIO_TX_SET, 0x1000); 456 break; 457 default: 458 octeon_write_lcd("PowerOff"); 459 break; 460 } 461 462 octeon_kill_core(NULL); 463 } 464 465 static char __read_mostly octeon_system_type[80]; 466 467 static void __init init_octeon_system_type(void) 468 { 469 char const *board_type; 470 471 board_type = cvmx_board_type_to_string(octeon_bootinfo->board_type); 472 if (board_type == NULL) { 473 struct device_node *root; 474 int ret; 475 476 root = of_find_node_by_path("/"); 477 ret = of_property_read_string(root, "model", &board_type); 478 of_node_put(root); 479 if (ret) 480 board_type = "Unsupported Board"; 481 } 482 483 snprintf(octeon_system_type, sizeof(octeon_system_type), "%s (%s)", 484 board_type, octeon_model_get_string(read_c0_prid())); 485 } 486 487 /** 488 * Return a string representing the system type 489 * 490 * Returns 491 */ 492 const char *octeon_board_type_string(void) 493 { 494 return octeon_system_type; 495 } 496 497 const char *get_system_type(void) 498 __attribute__ ((alias("octeon_board_type_string"))); 499 500 void octeon_user_io_init(void) 501 { 502 union octeon_cvmemctl cvmmemctl; 503 504 /* Get the current settings for CP0_CVMMEMCTL_REG */ 505 cvmmemctl.u64 = read_c0_cvmmemctl(); 506 /* R/W If set, marked write-buffer entries time out the same 507 * as as other entries; if clear, marked write-buffer entries 508 * use the maximum timeout. */ 509 cvmmemctl.s.dismarkwblongto = 1; 510 /* R/W If set, a merged store does not clear the write-buffer 511 * entry timeout state. */ 512 cvmmemctl.s.dismrgclrwbto = 0; 513 /* R/W Two bits that are the MSBs of the resultant CVMSEG LM 514 * word location for an IOBDMA. The other 8 bits come from the 515 * SCRADDR field of the IOBDMA. */ 516 cvmmemctl.s.iobdmascrmsb = 0; 517 /* R/W If set, SYNCWS and SYNCS only order marked stores; if 518 * clear, SYNCWS and SYNCS only order unmarked 519 * stores. SYNCWSMARKED has no effect when DISSYNCWS is 520 * set. */ 521 cvmmemctl.s.syncwsmarked = 0; 522 /* R/W If set, SYNCWS acts as SYNCW and SYNCS acts as SYNC. */ 523 cvmmemctl.s.dissyncws = 0; 524 /* R/W If set, no stall happens on write buffer full. */ 525 if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2)) 526 cvmmemctl.s.diswbfst = 1; 527 else 528 cvmmemctl.s.diswbfst = 0; 529 /* R/W If set (and SX set), supervisor-level loads/stores can 530 * use XKPHYS addresses with <48>==0 */ 531 cvmmemctl.s.xkmemenas = 0; 532 533 /* R/W If set (and UX set), user-level loads/stores can use 534 * XKPHYS addresses with VA<48>==0 */ 535 cvmmemctl.s.xkmemenau = 0; 536 537 /* R/W If set (and SX set), supervisor-level loads/stores can 538 * use XKPHYS addresses with VA<48>==1 */ 539 cvmmemctl.s.xkioenas = 0; 540 541 /* R/W If set (and UX set), user-level loads/stores can use 542 * XKPHYS addresses with VA<48>==1 */ 543 cvmmemctl.s.xkioenau = 0; 544 545 /* R/W If set, all stores act as SYNCW (NOMERGE must be set 546 * when this is set) RW, reset to 0. */ 547 cvmmemctl.s.allsyncw = 0; 548 549 /* R/W If set, no stores merge, and all stores reach the 550 * coherent bus in order. */ 551 cvmmemctl.s.nomerge = 0; 552 /* R/W Selects the bit in the counter used for DID time-outs 0 553 * = 231, 1 = 230, 2 = 229, 3 = 214. Actual time-out is 554 * between 1x and 2x this interval. For example, with 555 * DIDTTO=3, expiration interval is between 16K and 32K. */ 556 cvmmemctl.s.didtto = 0; 557 /* R/W If set, the (mem) CSR clock never turns off. */ 558 cvmmemctl.s.csrckalwys = 0; 559 /* R/W If set, mclk never turns off. */ 560 cvmmemctl.s.mclkalwys = 0; 561 /* R/W Selects the bit in the counter used for write buffer 562 * flush time-outs (WBFLT+11) is the bit position in an 563 * internal counter used to determine expiration. The write 564 * buffer expires between 1x and 2x this interval. For 565 * example, with WBFLT = 0, a write buffer expires between 2K 566 * and 4K cycles after the write buffer entry is allocated. */ 567 cvmmemctl.s.wbfltime = 0; 568 /* R/W If set, do not put Istream in the L2 cache. */ 569 cvmmemctl.s.istrnol2 = 0; 570 571 /* 572 * R/W The write buffer threshold. As per erratum Core-14752 573 * for CN63XX, a sc/scd might fail if the write buffer is 574 * full. Lowering WBTHRESH greatly lowers the chances of the 575 * write buffer ever being full and triggering the erratum. 576 */ 577 if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X)) 578 cvmmemctl.s.wbthresh = 4; 579 else 580 cvmmemctl.s.wbthresh = 10; 581 582 /* R/W If set, CVMSEG is available for loads/stores in 583 * kernel/debug mode. */ 584 #if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0 585 cvmmemctl.s.cvmsegenak = 1; 586 #else 587 cvmmemctl.s.cvmsegenak = 0; 588 #endif 589 /* R/W If set, CVMSEG is available for loads/stores in 590 * supervisor mode. */ 591 cvmmemctl.s.cvmsegenas = 0; 592 /* R/W If set, CVMSEG is available for loads/stores in user 593 * mode. */ 594 cvmmemctl.s.cvmsegenau = 0; 595 596 write_c0_cvmmemctl(cvmmemctl.u64); 597 598 /* Setup of CVMSEG is done in kernel-entry-init.h */ 599 if (smp_processor_id() == 0) 600 pr_notice("CVMSEG size: %d cache lines (%d bytes)\n", 601 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE, 602 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128); 603 604 if (octeon_has_feature(OCTEON_FEATURE_FAU)) { 605 union cvmx_iob_fau_timeout fau_timeout; 606 607 /* Set a default for the hardware timeouts */ 608 fau_timeout.u64 = 0; 609 fau_timeout.s.tout_val = 0xfff; 610 /* Disable tagwait FAU timeout */ 611 fau_timeout.s.tout_enb = 0; 612 cvmx_write_csr(CVMX_IOB_FAU_TIMEOUT, fau_timeout.u64); 613 } 614 615 if ((!OCTEON_IS_MODEL(OCTEON_CN68XX) && 616 !OCTEON_IS_MODEL(OCTEON_CN7XXX)) || 617 OCTEON_IS_MODEL(OCTEON_CN70XX)) { 618 union cvmx_pow_nw_tim nm_tim; 619 620 nm_tim.u64 = 0; 621 /* 4096 cycles */ 622 nm_tim.s.nw_tim = 3; 623 cvmx_write_csr(CVMX_POW_NW_TIM, nm_tim.u64); 624 } 625 626 write_octeon_c0_icacheerr(0); 627 write_c0_derraddr1(0); 628 } 629 630 /** 631 * Early entry point for arch setup 632 */ 633 void __init prom_init(void) 634 { 635 struct cvmx_sysinfo *sysinfo; 636 const char *arg; 637 char *p; 638 int i; 639 u64 t; 640 int argc; 641 #ifdef CONFIG_CAVIUM_RESERVE32 642 int64_t addr = -1; 643 #endif 644 /* 645 * The bootloader passes a pointer to the boot descriptor in 646 * $a3, this is available as fw_arg3. 647 */ 648 octeon_boot_desc_ptr = (struct octeon_boot_descriptor *)fw_arg3; 649 octeon_bootinfo = 650 cvmx_phys_to_ptr(octeon_boot_desc_ptr->cvmx_desc_vaddr); 651 cvmx_bootmem_init(cvmx_phys_to_ptr(octeon_bootinfo->phy_mem_desc_addr)); 652 653 sysinfo = cvmx_sysinfo_get(); 654 memset(sysinfo, 0, sizeof(*sysinfo)); 655 sysinfo->system_dram_size = octeon_bootinfo->dram_size << 20; 656 sysinfo->phy_mem_desc_addr = (u64)phys_to_virt(octeon_bootinfo->phy_mem_desc_addr); 657 658 if ((octeon_bootinfo->major_version > 1) || 659 (octeon_bootinfo->major_version == 1 && 660 octeon_bootinfo->minor_version >= 4)) 661 cvmx_coremask_copy(&sysinfo->core_mask, 662 &octeon_bootinfo->ext_core_mask); 663 else 664 cvmx_coremask_set64(&sysinfo->core_mask, 665 octeon_bootinfo->core_mask); 666 667 /* Some broken u-boot pass garbage in upper bits, clear them out */ 668 if (!OCTEON_IS_MODEL(OCTEON_CN78XX)) 669 for (i = 512; i < 1024; i++) 670 cvmx_coremask_clear_core(&sysinfo->core_mask, i); 671 672 sysinfo->exception_base_addr = octeon_bootinfo->exception_base_addr; 673 sysinfo->cpu_clock_hz = octeon_bootinfo->eclock_hz; 674 sysinfo->dram_data_rate_hz = octeon_bootinfo->dclock_hz * 2; 675 sysinfo->board_type = octeon_bootinfo->board_type; 676 sysinfo->board_rev_major = octeon_bootinfo->board_rev_major; 677 sysinfo->board_rev_minor = octeon_bootinfo->board_rev_minor; 678 memcpy(sysinfo->mac_addr_base, octeon_bootinfo->mac_addr_base, 679 sizeof(sysinfo->mac_addr_base)); 680 sysinfo->mac_addr_count = octeon_bootinfo->mac_addr_count; 681 memcpy(sysinfo->board_serial_number, 682 octeon_bootinfo->board_serial_number, 683 sizeof(sysinfo->board_serial_number)); 684 sysinfo->compact_flash_common_base_addr = 685 octeon_bootinfo->compact_flash_common_base_addr; 686 sysinfo->compact_flash_attribute_base_addr = 687 octeon_bootinfo->compact_flash_attribute_base_addr; 688 sysinfo->led_display_base_addr = octeon_bootinfo->led_display_base_addr; 689 sysinfo->dfa_ref_clock_hz = octeon_bootinfo->dfa_ref_clock_hz; 690 sysinfo->bootloader_config_flags = octeon_bootinfo->config_flags; 691 692 if (OCTEON_IS_OCTEON2()) { 693 /* I/O clock runs at a different rate than the CPU. */ 694 union cvmx_mio_rst_boot rst_boot; 695 rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT); 696 octeon_io_clock_rate = 50000000 * rst_boot.s.pnr_mul; 697 } else if (OCTEON_IS_OCTEON3()) { 698 /* I/O clock runs at a different rate than the CPU. */ 699 union cvmx_rst_boot rst_boot; 700 rst_boot.u64 = cvmx_read_csr(CVMX_RST_BOOT); 701 octeon_io_clock_rate = 50000000 * rst_boot.s.pnr_mul; 702 } else { 703 octeon_io_clock_rate = sysinfo->cpu_clock_hz; 704 } 705 706 t = read_c0_cvmctl(); 707 if ((t & (1ull << 27)) == 0) { 708 /* 709 * Setup the multiplier save/restore code if 710 * CvmCtl[NOMUL] clear. 711 */ 712 void *save; 713 void *save_end; 714 void *restore; 715 void *restore_end; 716 int save_len; 717 int restore_len; 718 int save_max = (char *)octeon_mult_save_end - 719 (char *)octeon_mult_save; 720 int restore_max = (char *)octeon_mult_restore_end - 721 (char *)octeon_mult_restore; 722 if (current_cpu_data.cputype == CPU_CAVIUM_OCTEON3) { 723 save = octeon_mult_save3; 724 save_end = octeon_mult_save3_end; 725 restore = octeon_mult_restore3; 726 restore_end = octeon_mult_restore3_end; 727 } else { 728 save = octeon_mult_save2; 729 save_end = octeon_mult_save2_end; 730 restore = octeon_mult_restore2; 731 restore_end = octeon_mult_restore2_end; 732 } 733 save_len = (char *)save_end - (char *)save; 734 restore_len = (char *)restore_end - (char *)restore; 735 if (!WARN_ON(save_len > save_max || 736 restore_len > restore_max)) { 737 memcpy(octeon_mult_save, save, save_len); 738 memcpy(octeon_mult_restore, restore, restore_len); 739 } 740 } 741 742 /* 743 * Only enable the LED controller if we're running on a CN38XX, CN58XX, 744 * or CN56XX. The CN30XX and CN31XX don't have an LED controller. 745 */ 746 if (!octeon_is_simulation() && 747 octeon_has_feature(OCTEON_FEATURE_LED_CONTROLLER)) { 748 cvmx_write_csr(CVMX_LED_EN, 0); 749 cvmx_write_csr(CVMX_LED_PRT, 0); 750 cvmx_write_csr(CVMX_LED_DBG, 0); 751 cvmx_write_csr(CVMX_LED_PRT_FMT, 0); 752 cvmx_write_csr(CVMX_LED_UDD_CNTX(0), 32); 753 cvmx_write_csr(CVMX_LED_UDD_CNTX(1), 32); 754 cvmx_write_csr(CVMX_LED_UDD_DATX(0), 0); 755 cvmx_write_csr(CVMX_LED_UDD_DATX(1), 0); 756 cvmx_write_csr(CVMX_LED_EN, 1); 757 } 758 #ifdef CONFIG_CAVIUM_RESERVE32 759 /* 760 * We need to temporarily allocate all memory in the reserve32 761 * region. This makes sure the kernel doesn't allocate this 762 * memory when it is getting memory from the 763 * bootloader. Later, after the memory allocations are 764 * complete, the reserve32 will be freed. 765 * 766 * Allocate memory for RESERVED32 aligned on 2MB boundary. This 767 * is in case we later use hugetlb entries with it. 768 */ 769 addr = cvmx_bootmem_phy_named_block_alloc(CONFIG_CAVIUM_RESERVE32 << 20, 770 0, 0, 2 << 20, 771 "CAVIUM_RESERVE32", 0); 772 if (addr < 0) 773 pr_err("Failed to allocate CAVIUM_RESERVE32 memory area\n"); 774 else 775 octeon_reserve32_memory = addr; 776 #endif 777 778 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2 779 if (cvmx_read_csr(CVMX_L2D_FUS3) & (3ull << 34)) { 780 pr_info("Skipping L2 locking due to reduced L2 cache size\n"); 781 } else { 782 uint32_t __maybe_unused ebase = read_c0_ebase() & 0x3ffff000; 783 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_TLB 784 /* TLB refill */ 785 cvmx_l2c_lock_mem_region(ebase, 0x100); 786 #endif 787 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_EXCEPTION 788 /* General exception */ 789 cvmx_l2c_lock_mem_region(ebase + 0x180, 0x80); 790 #endif 791 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT 792 /* Interrupt handler */ 793 cvmx_l2c_lock_mem_region(ebase + 0x200, 0x80); 794 #endif 795 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_INTERRUPT 796 cvmx_l2c_lock_mem_region(__pa_symbol(handle_int), 0x100); 797 cvmx_l2c_lock_mem_region(__pa_symbol(plat_irq_dispatch), 0x80); 798 #endif 799 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_MEMCPY 800 cvmx_l2c_lock_mem_region(__pa_symbol(memcpy), 0x480); 801 #endif 802 } 803 #endif 804 805 octeon_check_cpu_bist(); 806 807 octeon_uart = octeon_get_boot_uart(); 808 809 #ifdef CONFIG_SMP 810 octeon_write_lcd("LinuxSMP"); 811 #else 812 octeon_write_lcd("Linux"); 813 #endif 814 815 octeon_setup_delays(); 816 817 /* 818 * BIST should always be enabled when doing a soft reset. L2 819 * Cache locking for instance is not cleared unless BIST is 820 * enabled. Unfortunately due to a chip errata G-200 for 821 * Cn38XX and CN31XX, BIST msut be disabled on these parts. 822 */ 823 if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2) || 824 OCTEON_IS_MODEL(OCTEON_CN31XX)) 825 cvmx_write_csr(CVMX_CIU_SOFT_BIST, 0); 826 else 827 cvmx_write_csr(CVMX_CIU_SOFT_BIST, 1); 828 829 /* Default to 64MB in the simulator to speed things up */ 830 if (octeon_is_simulation()) 831 MAX_MEMORY = 64ull << 20; 832 833 arg = strstr(arcs_cmdline, "mem="); 834 if (arg) { 835 MAX_MEMORY = memparse(arg + 4, &p); 836 if (MAX_MEMORY == 0) 837 MAX_MEMORY = 32ull << 30; 838 if (*p == '@') 839 RESERVE_LOW_MEM = memparse(p + 1, &p); 840 } 841 842 arcs_cmdline[0] = 0; 843 argc = octeon_boot_desc_ptr->argc; 844 for (i = 0; i < argc; i++) { 845 const char *arg = 846 cvmx_phys_to_ptr(octeon_boot_desc_ptr->argv[i]); 847 if ((strncmp(arg, "MEM=", 4) == 0) || 848 (strncmp(arg, "mem=", 4) == 0)) { 849 MAX_MEMORY = memparse(arg + 4, &p); 850 if (MAX_MEMORY == 0) 851 MAX_MEMORY = 32ull << 30; 852 if (*p == '@') 853 RESERVE_LOW_MEM = memparse(p + 1, &p); 854 #ifdef CONFIG_KEXEC 855 } else if (strncmp(arg, "crashkernel=", 12) == 0) { 856 crashk_size = memparse(arg+12, &p); 857 if (*p == '@') 858 crashk_base = memparse(p+1, &p); 859 strcat(arcs_cmdline, " "); 860 strcat(arcs_cmdline, arg); 861 /* 862 * To do: switch parsing to new style, something like: 863 * parse_crashkernel(arg, sysinfo->system_dram_size, 864 * &crashk_size, &crashk_base); 865 */ 866 #endif 867 } else if (strlen(arcs_cmdline) + strlen(arg) + 1 < 868 sizeof(arcs_cmdline) - 1) { 869 strcat(arcs_cmdline, " "); 870 strcat(arcs_cmdline, arg); 871 } 872 } 873 874 if (strstr(arcs_cmdline, "console=") == NULL) { 875 #ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL 876 strcat(arcs_cmdline, " console=ttyS0,115200"); 877 #else 878 if (octeon_uart == 1) 879 strcat(arcs_cmdline, " console=ttyS1,115200"); 880 else 881 strcat(arcs_cmdline, " console=ttyS0,115200"); 882 #endif 883 } 884 885 mips_hpt_frequency = octeon_get_clock_rate(); 886 887 octeon_init_cvmcount(); 888 889 _machine_restart = octeon_restart; 890 _machine_halt = octeon_halt; 891 892 #ifdef CONFIG_KEXEC 893 _machine_kexec_shutdown = octeon_shutdown; 894 _machine_crash_shutdown = octeon_crash_shutdown; 895 _machine_kexec_prepare = octeon_kexec_prepare; 896 #endif 897 898 octeon_user_io_init(); 899 octeon_setup_smp(); 900 } 901 902 /* Exclude a single page from the regions obtained in plat_mem_setup. */ 903 #ifndef CONFIG_CRASH_DUMP 904 static __init void memory_exclude_page(u64 addr, u64 *mem, u64 *size) 905 { 906 if (addr > *mem && addr < *mem + *size) { 907 u64 inc = addr - *mem; 908 add_memory_region(*mem, inc, BOOT_MEM_RAM); 909 *mem += inc; 910 *size -= inc; 911 } 912 913 if (addr == *mem && *size > PAGE_SIZE) { 914 *mem += PAGE_SIZE; 915 *size -= PAGE_SIZE; 916 } 917 } 918 #endif /* CONFIG_CRASH_DUMP */ 919 920 void __init plat_mem_setup(void) 921 { 922 uint64_t mem_alloc_size; 923 uint64_t total; 924 uint64_t crashk_end; 925 #ifndef CONFIG_CRASH_DUMP 926 int64_t memory; 927 uint64_t kernel_start; 928 uint64_t kernel_size; 929 #endif 930 931 total = 0; 932 crashk_end = 0; 933 934 /* 935 * The Mips memory init uses the first memory location for 936 * some memory vectors. When SPARSEMEM is in use, it doesn't 937 * verify that the size is big enough for the final 938 * vectors. Making the smallest chuck 4MB seems to be enough 939 * to consistently work. 940 */ 941 mem_alloc_size = 4 << 20; 942 if (mem_alloc_size > MAX_MEMORY) 943 mem_alloc_size = MAX_MEMORY; 944 945 /* Crashkernel ignores bootmem list. It relies on mem=X@Y option */ 946 #ifdef CONFIG_CRASH_DUMP 947 add_memory_region(RESERVE_LOW_MEM, MAX_MEMORY, BOOT_MEM_RAM); 948 total += MAX_MEMORY; 949 #else 950 #ifdef CONFIG_KEXEC 951 if (crashk_size > 0) { 952 add_memory_region(crashk_base, crashk_size, BOOT_MEM_RAM); 953 crashk_end = crashk_base + crashk_size; 954 } 955 #endif 956 /* 957 * When allocating memory, we want incrementing addresses from 958 * bootmem_alloc so the code in add_memory_region can merge 959 * regions next to each other. 960 */ 961 cvmx_bootmem_lock(); 962 while ((boot_mem_map.nr_map < BOOT_MEM_MAP_MAX) 963 && (total < MAX_MEMORY)) { 964 memory = cvmx_bootmem_phy_alloc(mem_alloc_size, 965 __pa_symbol(&_end), -1, 966 0x100000, 967 CVMX_BOOTMEM_FLAG_NO_LOCKING); 968 if (memory >= 0) { 969 u64 size = mem_alloc_size; 970 #ifdef CONFIG_KEXEC 971 uint64_t end; 972 #endif 973 974 /* 975 * exclude a page at the beginning and end of 976 * the 256MB PCIe 'hole' so the kernel will not 977 * try to allocate multi-page buffers that 978 * span the discontinuity. 979 */ 980 memory_exclude_page(CVMX_PCIE_BAR1_PHYS_BASE, 981 &memory, &size); 982 memory_exclude_page(CVMX_PCIE_BAR1_PHYS_BASE + 983 CVMX_PCIE_BAR1_PHYS_SIZE, 984 &memory, &size); 985 #ifdef CONFIG_KEXEC 986 end = memory + mem_alloc_size; 987 988 /* 989 * This function automatically merges address regions 990 * next to each other if they are received in 991 * incrementing order 992 */ 993 if (memory < crashk_base && end > crashk_end) { 994 /* region is fully in */ 995 add_memory_region(memory, 996 crashk_base - memory, 997 BOOT_MEM_RAM); 998 total += crashk_base - memory; 999 add_memory_region(crashk_end, 1000 end - crashk_end, 1001 BOOT_MEM_RAM); 1002 total += end - crashk_end; 1003 continue; 1004 } 1005 1006 if (memory >= crashk_base && end <= crashk_end) 1007 /* 1008 * Entire memory region is within the new 1009 * kernel's memory, ignore it. 1010 */ 1011 continue; 1012 1013 if (memory > crashk_base && memory < crashk_end && 1014 end > crashk_end) { 1015 /* 1016 * Overlap with the beginning of the region, 1017 * reserve the beginning. 1018 */ 1019 mem_alloc_size -= crashk_end - memory; 1020 memory = crashk_end; 1021 } else if (memory < crashk_base && end > crashk_base && 1022 end < crashk_end) 1023 /* 1024 * Overlap with the beginning of the region, 1025 * chop of end. 1026 */ 1027 mem_alloc_size -= end - crashk_base; 1028 #endif 1029 add_memory_region(memory, mem_alloc_size, BOOT_MEM_RAM); 1030 total += mem_alloc_size; 1031 /* Recovering mem_alloc_size */ 1032 mem_alloc_size = 4 << 20; 1033 } else { 1034 break; 1035 } 1036 } 1037 cvmx_bootmem_unlock(); 1038 /* Add the memory region for the kernel. */ 1039 kernel_start = (unsigned long) _text; 1040 kernel_size = _end - _text; 1041 1042 /* Adjust for physical offset. */ 1043 kernel_start &= ~0xffffffff80000000ULL; 1044 add_memory_region(kernel_start, kernel_size, BOOT_MEM_RAM); 1045 #endif /* CONFIG_CRASH_DUMP */ 1046 1047 #ifdef CONFIG_CAVIUM_RESERVE32 1048 /* 1049 * Now that we've allocated the kernel memory it is safe to 1050 * free the reserved region. We free it here so that builtin 1051 * drivers can use the memory. 1052 */ 1053 if (octeon_reserve32_memory) 1054 cvmx_bootmem_free_named("CAVIUM_RESERVE32"); 1055 #endif /* CONFIG_CAVIUM_RESERVE32 */ 1056 1057 if (total == 0) 1058 panic("Unable to allocate memory from " 1059 "cvmx_bootmem_phy_alloc"); 1060 } 1061 1062 /* 1063 * Emit one character to the boot UART. Exported for use by the 1064 * watchdog timer. 1065 */ 1066 int prom_putchar(char c) 1067 { 1068 uint64_t lsrval; 1069 1070 /* Spin until there is room */ 1071 do { 1072 lsrval = cvmx_read_csr(CVMX_MIO_UARTX_LSR(octeon_uart)); 1073 } while ((lsrval & 0x20) == 0); 1074 1075 /* Write the byte */ 1076 cvmx_write_csr(CVMX_MIO_UARTX_THR(octeon_uart), c & 0xffull); 1077 return 1; 1078 } 1079 EXPORT_SYMBOL(prom_putchar); 1080 1081 void __init prom_free_prom_memory(void) 1082 { 1083 if (CAVIUM_OCTEON_DCACHE_PREFETCH_WAR) { 1084 /* Check for presence of Core-14449 fix. */ 1085 u32 insn; 1086 u32 *foo; 1087 1088 foo = &insn; 1089 1090 asm volatile("# before" : : : "memory"); 1091 prefetch(foo); 1092 asm volatile( 1093 ".set push\n\t" 1094 ".set noreorder\n\t" 1095 "bal 1f\n\t" 1096 "nop\n" 1097 "1:\tlw %0,-12($31)\n\t" 1098 ".set pop\n\t" 1099 : "=r" (insn) : : "$31", "memory"); 1100 1101 if ((insn >> 26) != 0x33) 1102 panic("No PREF instruction at Core-14449 probe point."); 1103 1104 if (((insn >> 16) & 0x1f) != 28) 1105 panic("OCTEON II DCache prefetch workaround not in place (%04x).\n" 1106 "Please build kernel with proper options (CONFIG_CAVIUM_CN63XXP1).", 1107 insn); 1108 } 1109 } 1110 1111 void __init octeon_fill_mac_addresses(void); 1112 int octeon_prune_device_tree(void); 1113 1114 extern const char __appended_dtb; 1115 extern const char __dtb_octeon_3xxx_begin; 1116 extern const char __dtb_octeon_68xx_begin; 1117 void __init device_tree_init(void) 1118 { 1119 const void *fdt; 1120 bool do_prune; 1121 bool fill_mac; 1122 1123 #ifdef CONFIG_MIPS_ELF_APPENDED_DTB 1124 if (!fdt_check_header(&__appended_dtb)) { 1125 fdt = &__appended_dtb; 1126 do_prune = false; 1127 fill_mac = true; 1128 pr_info("Using appended Device Tree.\n"); 1129 } else 1130 #endif 1131 if (octeon_bootinfo->minor_version >= 3 && octeon_bootinfo->fdt_addr) { 1132 fdt = phys_to_virt(octeon_bootinfo->fdt_addr); 1133 if (fdt_check_header(fdt)) 1134 panic("Corrupt Device Tree passed to kernel."); 1135 do_prune = false; 1136 fill_mac = false; 1137 pr_info("Using passed Device Tree.\n"); 1138 } else if (OCTEON_IS_MODEL(OCTEON_CN68XX)) { 1139 fdt = &__dtb_octeon_68xx_begin; 1140 do_prune = true; 1141 fill_mac = true; 1142 } else { 1143 fdt = &__dtb_octeon_3xxx_begin; 1144 do_prune = true; 1145 fill_mac = true; 1146 } 1147 1148 initial_boot_params = (void *)fdt; 1149 1150 if (do_prune) { 1151 octeon_prune_device_tree(); 1152 pr_info("Using internal Device Tree.\n"); 1153 } 1154 if (fill_mac) 1155 octeon_fill_mac_addresses(); 1156 unflatten_and_copy_device_tree(); 1157 init_octeon_system_type(); 1158 } 1159 1160 static int __initdata disable_octeon_edac_p; 1161 1162 static int __init disable_octeon_edac(char *str) 1163 { 1164 disable_octeon_edac_p = 1; 1165 return 0; 1166 } 1167 early_param("disable_octeon_edac", disable_octeon_edac); 1168 1169 static char *edac_device_names[] = { 1170 "octeon_l2c_edac", 1171 "octeon_pc_edac", 1172 }; 1173 1174 static int __init edac_devinit(void) 1175 { 1176 struct platform_device *dev; 1177 int i, err = 0; 1178 int num_lmc; 1179 char *name; 1180 1181 if (disable_octeon_edac_p) 1182 return 0; 1183 1184 for (i = 0; i < ARRAY_SIZE(edac_device_names); i++) { 1185 name = edac_device_names[i]; 1186 dev = platform_device_register_simple(name, -1, NULL, 0); 1187 if (IS_ERR(dev)) { 1188 pr_err("Registration of %s failed!\n", name); 1189 err = PTR_ERR(dev); 1190 } 1191 } 1192 1193 num_lmc = OCTEON_IS_MODEL(OCTEON_CN68XX) ? 4 : 1194 (OCTEON_IS_MODEL(OCTEON_CN56XX) ? 2 : 1); 1195 for (i = 0; i < num_lmc; i++) { 1196 dev = platform_device_register_simple("octeon_lmc_edac", 1197 i, NULL, 0); 1198 if (IS_ERR(dev)) { 1199 pr_err("Registration of octeon_lmc_edac %d failed!\n", i); 1200 err = PTR_ERR(dev); 1201 } 1202 } 1203 1204 return err; 1205 } 1206 device_initcall(edac_devinit); 1207 1208 static void __initdata *octeon_dummy_iospace; 1209 1210 static int __init octeon_no_pci_init(void) 1211 { 1212 /* 1213 * Initially assume there is no PCI. The PCI/PCIe platform code will 1214 * later re-initialize these to correct values if they are present. 1215 */ 1216 octeon_dummy_iospace = vzalloc(IO_SPACE_LIMIT); 1217 set_io_port_base((unsigned long)octeon_dummy_iospace); 1218 ioport_resource.start = MAX_RESOURCE; 1219 ioport_resource.end = 0; 1220 return 0; 1221 } 1222 core_initcall(octeon_no_pci_init); 1223 1224 static int __init octeon_no_pci_release(void) 1225 { 1226 /* 1227 * Release the allocated memory if a real IO space is there. 1228 */ 1229 if ((unsigned long)octeon_dummy_iospace != mips_io_port_base) 1230 vfree(octeon_dummy_iospace); 1231 return 0; 1232 } 1233 late_initcall(octeon_no_pci_release); 1234