1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2004-2007 Cavium Networks 7 * Copyright (C) 2008, 2009 Wind River Systems 8 * written by Ralf Baechle <ralf@linux-mips.org> 9 */ 10 #include <linux/compiler.h> 11 #include <linux/init.h> 12 #include <linux/kernel.h> 13 #include <linux/console.h> 14 #include <linux/delay.h> 15 #include <linux/export.h> 16 #include <linux/interrupt.h> 17 #include <linux/io.h> 18 #include <linux/serial.h> 19 #include <linux/smp.h> 20 #include <linux/types.h> 21 #include <linux/string.h> /* for memset */ 22 #include <linux/tty.h> 23 #include <linux/time.h> 24 #include <linux/platform_device.h> 25 #include <linux/serial_core.h> 26 #include <linux/serial_8250.h> 27 #include <linux/of_fdt.h> 28 #include <linux/libfdt.h> 29 #include <linux/kexec.h> 30 31 #include <asm/processor.h> 32 #include <asm/reboot.h> 33 #include <asm/smp-ops.h> 34 #include <asm/irq_cpu.h> 35 #include <asm/mipsregs.h> 36 #include <asm/bootinfo.h> 37 #include <asm/sections.h> 38 #include <asm/time.h> 39 40 #include <asm/octeon/octeon.h> 41 #include <asm/octeon/pci-octeon.h> 42 #include <asm/octeon/cvmx-mio-defs.h> 43 44 #ifdef CONFIG_CAVIUM_DECODE_RSL 45 extern void cvmx_interrupt_rsl_decode(void); 46 extern int __cvmx_interrupt_ecc_report_single_bit_errors; 47 extern void cvmx_interrupt_rsl_enable(void); 48 #endif 49 50 extern struct plat_smp_ops octeon_smp_ops; 51 52 #ifdef CONFIG_PCI 53 extern void pci_console_init(const char *arg); 54 #endif 55 56 static unsigned long long MAX_MEMORY = 512ull << 20; 57 58 struct octeon_boot_descriptor *octeon_boot_desc_ptr; 59 60 struct cvmx_bootinfo *octeon_bootinfo; 61 EXPORT_SYMBOL(octeon_bootinfo); 62 63 static unsigned long long RESERVE_LOW_MEM = 0ull; 64 #ifdef CONFIG_KEXEC 65 #ifdef CONFIG_SMP 66 /* 67 * Wait for relocation code is prepared and send 68 * secondary CPUs to spin until kernel is relocated. 69 */ 70 static void octeon_kexec_smp_down(void *ignored) 71 { 72 int cpu = smp_processor_id(); 73 74 local_irq_disable(); 75 set_cpu_online(cpu, false); 76 while (!atomic_read(&kexec_ready_to_reboot)) 77 cpu_relax(); 78 79 asm volatile ( 80 " sync \n" 81 " synci ($0) \n"); 82 83 relocated_kexec_smp_wait(NULL); 84 } 85 #endif 86 87 #define OCTEON_DDR0_BASE (0x0ULL) 88 #define OCTEON_DDR0_SIZE (0x010000000ULL) 89 #define OCTEON_DDR1_BASE (0x410000000ULL) 90 #define OCTEON_DDR1_SIZE (0x010000000ULL) 91 #define OCTEON_DDR2_BASE (0x020000000ULL) 92 #define OCTEON_DDR2_SIZE (0x3e0000000ULL) 93 #define OCTEON_MAX_PHY_MEM_SIZE (16*1024*1024*1024ULL) 94 95 static struct kimage *kimage_ptr; 96 97 static void kexec_bootmem_init(uint64_t mem_size, uint32_t low_reserved_bytes) 98 { 99 int64_t addr; 100 struct cvmx_bootmem_desc *bootmem_desc; 101 102 bootmem_desc = cvmx_bootmem_get_desc(); 103 104 if (mem_size > OCTEON_MAX_PHY_MEM_SIZE) { 105 mem_size = OCTEON_MAX_PHY_MEM_SIZE; 106 pr_err("Error: requested memory too large," 107 "truncating to maximum size\n"); 108 } 109 110 bootmem_desc->major_version = CVMX_BOOTMEM_DESC_MAJ_VER; 111 bootmem_desc->minor_version = CVMX_BOOTMEM_DESC_MIN_VER; 112 113 addr = (OCTEON_DDR0_BASE + RESERVE_LOW_MEM + low_reserved_bytes); 114 bootmem_desc->head_addr = 0; 115 116 if (mem_size <= OCTEON_DDR0_SIZE) { 117 __cvmx_bootmem_phy_free(addr, 118 mem_size - RESERVE_LOW_MEM - 119 low_reserved_bytes, 0); 120 return; 121 } 122 123 __cvmx_bootmem_phy_free(addr, 124 OCTEON_DDR0_SIZE - RESERVE_LOW_MEM - 125 low_reserved_bytes, 0); 126 127 mem_size -= OCTEON_DDR0_SIZE; 128 129 if (mem_size > OCTEON_DDR1_SIZE) { 130 __cvmx_bootmem_phy_free(OCTEON_DDR1_BASE, OCTEON_DDR1_SIZE, 0); 131 __cvmx_bootmem_phy_free(OCTEON_DDR2_BASE, 132 mem_size - OCTEON_DDR1_SIZE, 0); 133 } else 134 __cvmx_bootmem_phy_free(OCTEON_DDR1_BASE, mem_size, 0); 135 } 136 137 static int octeon_kexec_prepare(struct kimage *image) 138 { 139 int i; 140 char *bootloader = "kexec"; 141 142 octeon_boot_desc_ptr->argc = 0; 143 for (i = 0; i < image->nr_segments; i++) { 144 if (!strncmp(bootloader, (char *)image->segment[i].buf, 145 strlen(bootloader))) { 146 /* 147 * convert command line string to array 148 * of parameters (as bootloader does). 149 */ 150 int argc = 0, offt; 151 char *str = (char *)image->segment[i].buf; 152 char *ptr = strchr(str, ' '); 153 while (ptr && (OCTEON_ARGV_MAX_ARGS > argc)) { 154 *ptr = '\0'; 155 if (ptr[1] != ' ') { 156 offt = (int)(ptr - str + 1); 157 octeon_boot_desc_ptr->argv[argc] = 158 image->segment[i].mem + offt; 159 argc++; 160 } 161 ptr = strchr(ptr + 1, ' '); 162 } 163 octeon_boot_desc_ptr->argc = argc; 164 break; 165 } 166 } 167 168 /* 169 * Information about segments will be needed during pre-boot memory 170 * initialization. 171 */ 172 kimage_ptr = image; 173 return 0; 174 } 175 176 static void octeon_generic_shutdown(void) 177 { 178 int i; 179 #ifdef CONFIG_SMP 180 int cpu; 181 #endif 182 struct cvmx_bootmem_desc *bootmem_desc; 183 void *named_block_array_ptr; 184 185 bootmem_desc = cvmx_bootmem_get_desc(); 186 named_block_array_ptr = 187 cvmx_phys_to_ptr(bootmem_desc->named_block_array_addr); 188 189 #ifdef CONFIG_SMP 190 /* disable watchdogs */ 191 for_each_online_cpu(cpu) 192 cvmx_write_csr(CVMX_CIU_WDOGX(cpu_logical_map(cpu)), 0); 193 #else 194 cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0); 195 #endif 196 if (kimage_ptr != kexec_crash_image) { 197 memset(named_block_array_ptr, 198 0x0, 199 CVMX_BOOTMEM_NUM_NAMED_BLOCKS * 200 sizeof(struct cvmx_bootmem_named_block_desc)); 201 /* 202 * Mark all memory (except low 0x100000 bytes) as free. 203 * It is the same thing that bootloader does. 204 */ 205 kexec_bootmem_init(octeon_bootinfo->dram_size*1024ULL*1024ULL, 206 0x100000); 207 /* 208 * Allocate all segments to avoid their corruption during boot. 209 */ 210 for (i = 0; i < kimage_ptr->nr_segments; i++) 211 cvmx_bootmem_alloc_address( 212 kimage_ptr->segment[i].memsz + 2*PAGE_SIZE, 213 kimage_ptr->segment[i].mem - PAGE_SIZE, 214 PAGE_SIZE); 215 } else { 216 /* 217 * Do not mark all memory as free. Free only named sections 218 * leaving the rest of memory unchanged. 219 */ 220 struct cvmx_bootmem_named_block_desc *ptr = 221 (struct cvmx_bootmem_named_block_desc *) 222 named_block_array_ptr; 223 224 for (i = 0; i < bootmem_desc->named_block_num_blocks; i++) 225 if (ptr[i].size) 226 cvmx_bootmem_free_named(ptr[i].name); 227 } 228 kexec_args[2] = 1UL; /* running on octeon_main_processor */ 229 kexec_args[3] = (unsigned long)octeon_boot_desc_ptr; 230 #ifdef CONFIG_SMP 231 secondary_kexec_args[2] = 0UL; /* running on secondary cpu */ 232 secondary_kexec_args[3] = (unsigned long)octeon_boot_desc_ptr; 233 #endif 234 } 235 236 static void octeon_shutdown(void) 237 { 238 octeon_generic_shutdown(); 239 #ifdef CONFIG_SMP 240 smp_call_function(octeon_kexec_smp_down, NULL, 0); 241 smp_wmb(); 242 while (num_online_cpus() > 1) { 243 cpu_relax(); 244 mdelay(1); 245 } 246 #endif 247 } 248 249 static void octeon_crash_shutdown(struct pt_regs *regs) 250 { 251 octeon_generic_shutdown(); 252 default_machine_crash_shutdown(regs); 253 } 254 255 #endif /* CONFIG_KEXEC */ 256 257 #ifdef CONFIG_CAVIUM_RESERVE32 258 uint64_t octeon_reserve32_memory; 259 EXPORT_SYMBOL(octeon_reserve32_memory); 260 #endif 261 262 #ifdef CONFIG_KEXEC 263 /* crashkernel cmdline parameter is parsed _after_ memory setup 264 * we also parse it here (workaround for EHB5200) */ 265 static uint64_t crashk_size, crashk_base; 266 #endif 267 268 static int octeon_uart; 269 270 extern asmlinkage void handle_int(void); 271 extern asmlinkage void plat_irq_dispatch(void); 272 273 /** 274 * Return non zero if we are currently running in the Octeon simulator 275 * 276 * Returns 277 */ 278 int octeon_is_simulation(void) 279 { 280 return octeon_bootinfo->board_type == CVMX_BOARD_TYPE_SIM; 281 } 282 EXPORT_SYMBOL(octeon_is_simulation); 283 284 /** 285 * Return true if Octeon is in PCI Host mode. This means 286 * Linux can control the PCI bus. 287 * 288 * Returns Non zero if Octeon in host mode. 289 */ 290 int octeon_is_pci_host(void) 291 { 292 #ifdef CONFIG_PCI 293 return octeon_bootinfo->config_flags & CVMX_BOOTINFO_CFG_FLAG_PCI_HOST; 294 #else 295 return 0; 296 #endif 297 } 298 299 /** 300 * Get the clock rate of Octeon 301 * 302 * Returns Clock rate in HZ 303 */ 304 uint64_t octeon_get_clock_rate(void) 305 { 306 struct cvmx_sysinfo *sysinfo = cvmx_sysinfo_get(); 307 308 return sysinfo->cpu_clock_hz; 309 } 310 EXPORT_SYMBOL(octeon_get_clock_rate); 311 312 static u64 octeon_io_clock_rate; 313 314 u64 octeon_get_io_clock_rate(void) 315 { 316 return octeon_io_clock_rate; 317 } 318 EXPORT_SYMBOL(octeon_get_io_clock_rate); 319 320 321 /** 322 * Write to the LCD display connected to the bootbus. This display 323 * exists on most Cavium evaluation boards. If it doesn't exist, then 324 * this function doesn't do anything. 325 * 326 * @s: String to write 327 */ 328 void octeon_write_lcd(const char *s) 329 { 330 if (octeon_bootinfo->led_display_base_addr) { 331 void __iomem *lcd_address = 332 ioremap_nocache(octeon_bootinfo->led_display_base_addr, 333 8); 334 int i; 335 for (i = 0; i < 8; i++, s++) { 336 if (*s) 337 iowrite8(*s, lcd_address + i); 338 else 339 iowrite8(' ', lcd_address + i); 340 } 341 iounmap(lcd_address); 342 } 343 } 344 345 /** 346 * Return the console uart passed by the bootloader 347 * 348 * Returns uart (0 or 1) 349 */ 350 int octeon_get_boot_uart(void) 351 { 352 int uart; 353 #ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL 354 uart = 1; 355 #else 356 uart = (octeon_boot_desc_ptr->flags & OCTEON_BL_FLAG_CONSOLE_UART1) ? 357 1 : 0; 358 #endif 359 return uart; 360 } 361 362 /** 363 * Get the coremask Linux was booted on. 364 * 365 * Returns Core mask 366 */ 367 int octeon_get_boot_coremask(void) 368 { 369 return octeon_boot_desc_ptr->core_mask; 370 } 371 372 /** 373 * Check the hardware BIST results for a CPU 374 */ 375 void octeon_check_cpu_bist(void) 376 { 377 const int coreid = cvmx_get_core_num(); 378 unsigned long long mask; 379 unsigned long long bist_val; 380 381 /* Check BIST results for COP0 registers */ 382 mask = 0x1f00000000ull; 383 bist_val = read_octeon_c0_icacheerr(); 384 if (bist_val & mask) 385 pr_err("Core%d BIST Failure: CacheErr(icache) = 0x%llx\n", 386 coreid, bist_val); 387 388 bist_val = read_octeon_c0_dcacheerr(); 389 if (bist_val & 1) 390 pr_err("Core%d L1 Dcache parity error: " 391 "CacheErr(dcache) = 0x%llx\n", 392 coreid, bist_val); 393 394 mask = 0xfc00000000000000ull; 395 bist_val = read_c0_cvmmemctl(); 396 if (bist_val & mask) 397 pr_err("Core%d BIST Failure: COP0_CVM_MEM_CTL = 0x%llx\n", 398 coreid, bist_val); 399 400 write_octeon_c0_dcacheerr(0); 401 } 402 403 /** 404 * Reboot Octeon 405 * 406 * @command: Command to pass to the bootloader. Currently ignored. 407 */ 408 static void octeon_restart(char *command) 409 { 410 /* Disable all watchdogs before soft reset. They don't get cleared */ 411 #ifdef CONFIG_SMP 412 int cpu; 413 for_each_online_cpu(cpu) 414 cvmx_write_csr(CVMX_CIU_WDOGX(cpu_logical_map(cpu)), 0); 415 #else 416 cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0); 417 #endif 418 419 mb(); 420 while (1) 421 cvmx_write_csr(CVMX_CIU_SOFT_RST, 1); 422 } 423 424 425 /** 426 * Permanently stop a core. 427 * 428 * @arg: Ignored. 429 */ 430 static void octeon_kill_core(void *arg) 431 { 432 if (octeon_is_simulation()) 433 /* A break instruction causes the simulator stop a core */ 434 asm volatile ("break" ::: "memory"); 435 436 local_irq_disable(); 437 /* Disable watchdog on this core. */ 438 cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0); 439 /* Spin in a low power mode. */ 440 while (true) 441 asm volatile ("wait" ::: "memory"); 442 } 443 444 445 /** 446 * Halt the system 447 */ 448 static void octeon_halt(void) 449 { 450 smp_call_function(octeon_kill_core, NULL, 0); 451 452 switch (octeon_bootinfo->board_type) { 453 case CVMX_BOARD_TYPE_NAO38: 454 /* Driving a 1 to GPIO 12 shuts off this board */ 455 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(12), 1); 456 cvmx_write_csr(CVMX_GPIO_TX_SET, 0x1000); 457 break; 458 default: 459 octeon_write_lcd("PowerOff"); 460 break; 461 } 462 463 octeon_kill_core(NULL); 464 } 465 466 /** 467 * Handle all the error condition interrupts that might occur. 468 * 469 */ 470 #ifdef CONFIG_CAVIUM_DECODE_RSL 471 static irqreturn_t octeon_rlm_interrupt(int cpl, void *dev_id) 472 { 473 cvmx_interrupt_rsl_decode(); 474 return IRQ_HANDLED; 475 } 476 #endif 477 478 /** 479 * Return a string representing the system type 480 * 481 * Returns 482 */ 483 const char *octeon_board_type_string(void) 484 { 485 static char name[80]; 486 sprintf(name, "%s (%s)", 487 cvmx_board_type_to_string(octeon_bootinfo->board_type), 488 octeon_model_get_string(read_c0_prid())); 489 return name; 490 } 491 492 const char *get_system_type(void) 493 __attribute__ ((alias("octeon_board_type_string"))); 494 495 void octeon_user_io_init(void) 496 { 497 union octeon_cvmemctl cvmmemctl; 498 union cvmx_iob_fau_timeout fau_timeout; 499 union cvmx_pow_nw_tim nm_tim; 500 501 /* Get the current settings for CP0_CVMMEMCTL_REG */ 502 cvmmemctl.u64 = read_c0_cvmmemctl(); 503 /* R/W If set, marked write-buffer entries time out the same 504 * as as other entries; if clear, marked write-buffer entries 505 * use the maximum timeout. */ 506 cvmmemctl.s.dismarkwblongto = 1; 507 /* R/W If set, a merged store does not clear the write-buffer 508 * entry timeout state. */ 509 cvmmemctl.s.dismrgclrwbto = 0; 510 /* R/W Two bits that are the MSBs of the resultant CVMSEG LM 511 * word location for an IOBDMA. The other 8 bits come from the 512 * SCRADDR field of the IOBDMA. */ 513 cvmmemctl.s.iobdmascrmsb = 0; 514 /* R/W If set, SYNCWS and SYNCS only order marked stores; if 515 * clear, SYNCWS and SYNCS only order unmarked 516 * stores. SYNCWSMARKED has no effect when DISSYNCWS is 517 * set. */ 518 cvmmemctl.s.syncwsmarked = 0; 519 /* R/W If set, SYNCWS acts as SYNCW and SYNCS acts as SYNC. */ 520 cvmmemctl.s.dissyncws = 0; 521 /* R/W If set, no stall happens on write buffer full. */ 522 if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2)) 523 cvmmemctl.s.diswbfst = 1; 524 else 525 cvmmemctl.s.diswbfst = 0; 526 /* R/W If set (and SX set), supervisor-level loads/stores can 527 * use XKPHYS addresses with <48>==0 */ 528 cvmmemctl.s.xkmemenas = 0; 529 530 /* R/W If set (and UX set), user-level loads/stores can use 531 * XKPHYS addresses with VA<48>==0 */ 532 cvmmemctl.s.xkmemenau = 0; 533 534 /* R/W If set (and SX set), supervisor-level loads/stores can 535 * use XKPHYS addresses with VA<48>==1 */ 536 cvmmemctl.s.xkioenas = 0; 537 538 /* R/W If set (and UX set), user-level loads/stores can use 539 * XKPHYS addresses with VA<48>==1 */ 540 cvmmemctl.s.xkioenau = 0; 541 542 /* R/W If set, all stores act as SYNCW (NOMERGE must be set 543 * when this is set) RW, reset to 0. */ 544 cvmmemctl.s.allsyncw = 0; 545 546 /* R/W If set, no stores merge, and all stores reach the 547 * coherent bus in order. */ 548 cvmmemctl.s.nomerge = 0; 549 /* R/W Selects the bit in the counter used for DID time-outs 0 550 * = 231, 1 = 230, 2 = 229, 3 = 214. Actual time-out is 551 * between 1x and 2x this interval. For example, with 552 * DIDTTO=3, expiration interval is between 16K and 32K. */ 553 cvmmemctl.s.didtto = 0; 554 /* R/W If set, the (mem) CSR clock never turns off. */ 555 cvmmemctl.s.csrckalwys = 0; 556 /* R/W If set, mclk never turns off. */ 557 cvmmemctl.s.mclkalwys = 0; 558 /* R/W Selects the bit in the counter used for write buffer 559 * flush time-outs (WBFLT+11) is the bit position in an 560 * internal counter used to determine expiration. The write 561 * buffer expires between 1x and 2x this interval. For 562 * example, with WBFLT = 0, a write buffer expires between 2K 563 * and 4K cycles after the write buffer entry is allocated. */ 564 cvmmemctl.s.wbfltime = 0; 565 /* R/W If set, do not put Istream in the L2 cache. */ 566 cvmmemctl.s.istrnol2 = 0; 567 568 /* 569 * R/W The write buffer threshold. As per erratum Core-14752 570 * for CN63XX, a sc/scd might fail if the write buffer is 571 * full. Lowering WBTHRESH greatly lowers the chances of the 572 * write buffer ever being full and triggering the erratum. 573 */ 574 if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X)) 575 cvmmemctl.s.wbthresh = 4; 576 else 577 cvmmemctl.s.wbthresh = 10; 578 579 /* R/W If set, CVMSEG is available for loads/stores in 580 * kernel/debug mode. */ 581 #if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0 582 cvmmemctl.s.cvmsegenak = 1; 583 #else 584 cvmmemctl.s.cvmsegenak = 0; 585 #endif 586 /* R/W If set, CVMSEG is available for loads/stores in 587 * supervisor mode. */ 588 cvmmemctl.s.cvmsegenas = 0; 589 /* R/W If set, CVMSEG is available for loads/stores in user 590 * mode. */ 591 cvmmemctl.s.cvmsegenau = 0; 592 /* R/W Size of local memory in cache blocks, 54 (6912 bytes) 593 * is max legal value. */ 594 cvmmemctl.s.lmemsz = CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE; 595 596 write_c0_cvmmemctl(cvmmemctl.u64); 597 598 if (smp_processor_id() == 0) 599 pr_notice("CVMSEG size: %d cache lines (%d bytes)\n", 600 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE, 601 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128); 602 603 /* Set a default for the hardware timeouts */ 604 fau_timeout.u64 = 0; 605 fau_timeout.s.tout_val = 0xfff; 606 /* Disable tagwait FAU timeout */ 607 fau_timeout.s.tout_enb = 0; 608 cvmx_write_csr(CVMX_IOB_FAU_TIMEOUT, fau_timeout.u64); 609 610 nm_tim.u64 = 0; 611 /* 4096 cycles */ 612 nm_tim.s.nw_tim = 3; 613 cvmx_write_csr(CVMX_POW_NW_TIM, nm_tim.u64); 614 615 write_octeon_c0_icacheerr(0); 616 write_c0_derraddr1(0); 617 } 618 619 /** 620 * Early entry point for arch setup 621 */ 622 void __init prom_init(void) 623 { 624 struct cvmx_sysinfo *sysinfo; 625 const char *arg; 626 char *p; 627 int i; 628 int argc; 629 #ifdef CONFIG_CAVIUM_RESERVE32 630 int64_t addr = -1; 631 #endif 632 /* 633 * The bootloader passes a pointer to the boot descriptor in 634 * $a3, this is available as fw_arg3. 635 */ 636 octeon_boot_desc_ptr = (struct octeon_boot_descriptor *)fw_arg3; 637 octeon_bootinfo = 638 cvmx_phys_to_ptr(octeon_boot_desc_ptr->cvmx_desc_vaddr); 639 cvmx_bootmem_init(cvmx_phys_to_ptr(octeon_bootinfo->phy_mem_desc_addr)); 640 641 sysinfo = cvmx_sysinfo_get(); 642 memset(sysinfo, 0, sizeof(*sysinfo)); 643 sysinfo->system_dram_size = octeon_bootinfo->dram_size << 20; 644 sysinfo->phy_mem_desc_ptr = 645 cvmx_phys_to_ptr(octeon_bootinfo->phy_mem_desc_addr); 646 sysinfo->core_mask = octeon_bootinfo->core_mask; 647 sysinfo->exception_base_addr = octeon_bootinfo->exception_base_addr; 648 sysinfo->cpu_clock_hz = octeon_bootinfo->eclock_hz; 649 sysinfo->dram_data_rate_hz = octeon_bootinfo->dclock_hz * 2; 650 sysinfo->board_type = octeon_bootinfo->board_type; 651 sysinfo->board_rev_major = octeon_bootinfo->board_rev_major; 652 sysinfo->board_rev_minor = octeon_bootinfo->board_rev_minor; 653 memcpy(sysinfo->mac_addr_base, octeon_bootinfo->mac_addr_base, 654 sizeof(sysinfo->mac_addr_base)); 655 sysinfo->mac_addr_count = octeon_bootinfo->mac_addr_count; 656 memcpy(sysinfo->board_serial_number, 657 octeon_bootinfo->board_serial_number, 658 sizeof(sysinfo->board_serial_number)); 659 sysinfo->compact_flash_common_base_addr = 660 octeon_bootinfo->compact_flash_common_base_addr; 661 sysinfo->compact_flash_attribute_base_addr = 662 octeon_bootinfo->compact_flash_attribute_base_addr; 663 sysinfo->led_display_base_addr = octeon_bootinfo->led_display_base_addr; 664 sysinfo->dfa_ref_clock_hz = octeon_bootinfo->dfa_ref_clock_hz; 665 sysinfo->bootloader_config_flags = octeon_bootinfo->config_flags; 666 667 if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) { 668 /* I/O clock runs at a different rate than the CPU. */ 669 union cvmx_mio_rst_boot rst_boot; 670 rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT); 671 octeon_io_clock_rate = 50000000 * rst_boot.s.pnr_mul; 672 } else { 673 octeon_io_clock_rate = sysinfo->cpu_clock_hz; 674 } 675 676 /* 677 * Only enable the LED controller if we're running on a CN38XX, CN58XX, 678 * or CN56XX. The CN30XX and CN31XX don't have an LED controller. 679 */ 680 if (!octeon_is_simulation() && 681 octeon_has_feature(OCTEON_FEATURE_LED_CONTROLLER)) { 682 cvmx_write_csr(CVMX_LED_EN, 0); 683 cvmx_write_csr(CVMX_LED_PRT, 0); 684 cvmx_write_csr(CVMX_LED_DBG, 0); 685 cvmx_write_csr(CVMX_LED_PRT_FMT, 0); 686 cvmx_write_csr(CVMX_LED_UDD_CNTX(0), 32); 687 cvmx_write_csr(CVMX_LED_UDD_CNTX(1), 32); 688 cvmx_write_csr(CVMX_LED_UDD_DATX(0), 0); 689 cvmx_write_csr(CVMX_LED_UDD_DATX(1), 0); 690 cvmx_write_csr(CVMX_LED_EN, 1); 691 } 692 #ifdef CONFIG_CAVIUM_RESERVE32 693 /* 694 * We need to temporarily allocate all memory in the reserve32 695 * region. This makes sure the kernel doesn't allocate this 696 * memory when it is getting memory from the 697 * bootloader. Later, after the memory allocations are 698 * complete, the reserve32 will be freed. 699 * 700 * Allocate memory for RESERVED32 aligned on 2MB boundary. This 701 * is in case we later use hugetlb entries with it. 702 */ 703 addr = cvmx_bootmem_phy_named_block_alloc(CONFIG_CAVIUM_RESERVE32 << 20, 704 0, 0, 2 << 20, 705 "CAVIUM_RESERVE32", 0); 706 if (addr < 0) 707 pr_err("Failed to allocate CAVIUM_RESERVE32 memory area\n"); 708 else 709 octeon_reserve32_memory = addr; 710 #endif 711 712 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2 713 if (cvmx_read_csr(CVMX_L2D_FUS3) & (3ull << 34)) { 714 pr_info("Skipping L2 locking due to reduced L2 cache size\n"); 715 } else { 716 uint32_t __maybe_unused ebase = read_c0_ebase() & 0x3ffff000; 717 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_TLB 718 /* TLB refill */ 719 cvmx_l2c_lock_mem_region(ebase, 0x100); 720 #endif 721 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_EXCEPTION 722 /* General exception */ 723 cvmx_l2c_lock_mem_region(ebase + 0x180, 0x80); 724 #endif 725 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT 726 /* Interrupt handler */ 727 cvmx_l2c_lock_mem_region(ebase + 0x200, 0x80); 728 #endif 729 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_INTERRUPT 730 cvmx_l2c_lock_mem_region(__pa_symbol(handle_int), 0x100); 731 cvmx_l2c_lock_mem_region(__pa_symbol(plat_irq_dispatch), 0x80); 732 #endif 733 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_MEMCPY 734 cvmx_l2c_lock_mem_region(__pa_symbol(memcpy), 0x480); 735 #endif 736 } 737 #endif 738 739 octeon_check_cpu_bist(); 740 741 octeon_uart = octeon_get_boot_uart(); 742 743 #ifdef CONFIG_SMP 744 octeon_write_lcd("LinuxSMP"); 745 #else 746 octeon_write_lcd("Linux"); 747 #endif 748 749 #ifdef CONFIG_CAVIUM_GDB 750 /* 751 * When debugging the linux kernel, force the cores to enter 752 * the debug exception handler to break in. 753 */ 754 if (octeon_get_boot_debug_flag()) { 755 cvmx_write_csr(CVMX_CIU_DINT, 1 << cvmx_get_core_num()); 756 cvmx_read_csr(CVMX_CIU_DINT); 757 } 758 #endif 759 760 octeon_setup_delays(); 761 762 /* 763 * BIST should always be enabled when doing a soft reset. L2 764 * Cache locking for instance is not cleared unless BIST is 765 * enabled. Unfortunately due to a chip errata G-200 for 766 * Cn38XX and CN31XX, BIST msut be disabled on these parts. 767 */ 768 if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2) || 769 OCTEON_IS_MODEL(OCTEON_CN31XX)) 770 cvmx_write_csr(CVMX_CIU_SOFT_BIST, 0); 771 else 772 cvmx_write_csr(CVMX_CIU_SOFT_BIST, 1); 773 774 /* Default to 64MB in the simulator to speed things up */ 775 if (octeon_is_simulation()) 776 MAX_MEMORY = 64ull << 20; 777 778 arg = strstr(arcs_cmdline, "mem="); 779 if (arg) { 780 MAX_MEMORY = memparse(arg + 4, &p); 781 if (MAX_MEMORY == 0) 782 MAX_MEMORY = 32ull << 30; 783 if (*p == '@') 784 RESERVE_LOW_MEM = memparse(p + 1, &p); 785 } 786 787 arcs_cmdline[0] = 0; 788 argc = octeon_boot_desc_ptr->argc; 789 for (i = 0; i < argc; i++) { 790 const char *arg = 791 cvmx_phys_to_ptr(octeon_boot_desc_ptr->argv[i]); 792 if ((strncmp(arg, "MEM=", 4) == 0) || 793 (strncmp(arg, "mem=", 4) == 0)) { 794 MAX_MEMORY = memparse(arg + 4, &p); 795 if (MAX_MEMORY == 0) 796 MAX_MEMORY = 32ull << 30; 797 if (*p == '@') 798 RESERVE_LOW_MEM = memparse(p + 1, &p); 799 } else if (strcmp(arg, "ecc_verbose") == 0) { 800 #ifdef CONFIG_CAVIUM_REPORT_SINGLE_BIT_ECC 801 __cvmx_interrupt_ecc_report_single_bit_errors = 1; 802 pr_notice("Reporting of single bit ECC errors is " 803 "turned on\n"); 804 #endif 805 #ifdef CONFIG_KEXEC 806 } else if (strncmp(arg, "crashkernel=", 12) == 0) { 807 crashk_size = memparse(arg+12, &p); 808 if (*p == '@') 809 crashk_base = memparse(p+1, &p); 810 strcat(arcs_cmdline, " "); 811 strcat(arcs_cmdline, arg); 812 /* 813 * To do: switch parsing to new style, something like: 814 * parse_crashkernel(arg, sysinfo->system_dram_size, 815 * &crashk_size, &crashk_base); 816 */ 817 #endif 818 } else if (strlen(arcs_cmdline) + strlen(arg) + 1 < 819 sizeof(arcs_cmdline) - 1) { 820 strcat(arcs_cmdline, " "); 821 strcat(arcs_cmdline, arg); 822 } 823 } 824 825 if (strstr(arcs_cmdline, "console=") == NULL) { 826 #ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL 827 strcat(arcs_cmdline, " console=ttyS0,115200"); 828 #else 829 if (octeon_uart == 1) 830 strcat(arcs_cmdline, " console=ttyS1,115200"); 831 else 832 strcat(arcs_cmdline, " console=ttyS0,115200"); 833 #endif 834 } 835 836 if (octeon_is_simulation()) { 837 /* 838 * The simulator uses a mtdram device pre filled with 839 * the filesystem. Also specify the calibration delay 840 * to avoid calculating it every time. 841 */ 842 strcat(arcs_cmdline, " rw root=1f00 slram=root,0x40000000,+1073741824"); 843 } 844 845 mips_hpt_frequency = octeon_get_clock_rate(); 846 847 octeon_init_cvmcount(); 848 849 _machine_restart = octeon_restart; 850 _machine_halt = octeon_halt; 851 852 #ifdef CONFIG_KEXEC 853 _machine_kexec_shutdown = octeon_shutdown; 854 _machine_crash_shutdown = octeon_crash_shutdown; 855 _machine_kexec_prepare = octeon_kexec_prepare; 856 #endif 857 858 octeon_user_io_init(); 859 register_smp_ops(&octeon_smp_ops); 860 } 861 862 /* Exclude a single page from the regions obtained in plat_mem_setup. */ 863 #ifndef CONFIG_CRASH_DUMP 864 static __init void memory_exclude_page(u64 addr, u64 *mem, u64 *size) 865 { 866 if (addr > *mem && addr < *mem + *size) { 867 u64 inc = addr - *mem; 868 add_memory_region(*mem, inc, BOOT_MEM_RAM); 869 *mem += inc; 870 *size -= inc; 871 } 872 873 if (addr == *mem && *size > PAGE_SIZE) { 874 *mem += PAGE_SIZE; 875 *size -= PAGE_SIZE; 876 } 877 } 878 #endif /* CONFIG_CRASH_DUMP */ 879 880 void __init plat_mem_setup(void) 881 { 882 uint64_t mem_alloc_size; 883 uint64_t total; 884 uint64_t crashk_end; 885 #ifndef CONFIG_CRASH_DUMP 886 int64_t memory; 887 uint64_t kernel_start; 888 uint64_t kernel_size; 889 #endif 890 891 total = 0; 892 crashk_end = 0; 893 894 /* 895 * The Mips memory init uses the first memory location for 896 * some memory vectors. When SPARSEMEM is in use, it doesn't 897 * verify that the size is big enough for the final 898 * vectors. Making the smallest chuck 4MB seems to be enough 899 * to consistently work. 900 */ 901 mem_alloc_size = 4 << 20; 902 if (mem_alloc_size > MAX_MEMORY) 903 mem_alloc_size = MAX_MEMORY; 904 905 /* Crashkernel ignores bootmem list. It relies on mem=X@Y option */ 906 #ifdef CONFIG_CRASH_DUMP 907 add_memory_region(RESERVE_LOW_MEM, MAX_MEMORY, BOOT_MEM_RAM); 908 total += MAX_MEMORY; 909 #else 910 #ifdef CONFIG_KEXEC 911 if (crashk_size > 0) { 912 add_memory_region(crashk_base, crashk_size, BOOT_MEM_RAM); 913 crashk_end = crashk_base + crashk_size; 914 } 915 #endif 916 /* 917 * When allocating memory, we want incrementing addresses from 918 * bootmem_alloc so the code in add_memory_region can merge 919 * regions next to each other. 920 */ 921 cvmx_bootmem_lock(); 922 while ((boot_mem_map.nr_map < BOOT_MEM_MAP_MAX) 923 && (total < MAX_MEMORY)) { 924 memory = cvmx_bootmem_phy_alloc(mem_alloc_size, 925 __pa_symbol(&__init_end), -1, 926 0x100000, 927 CVMX_BOOTMEM_FLAG_NO_LOCKING); 928 if (memory >= 0) { 929 u64 size = mem_alloc_size; 930 #ifdef CONFIG_KEXEC 931 uint64_t end; 932 #endif 933 934 /* 935 * exclude a page at the beginning and end of 936 * the 256MB PCIe 'hole' so the kernel will not 937 * try to allocate multi-page buffers that 938 * span the discontinuity. 939 */ 940 memory_exclude_page(CVMX_PCIE_BAR1_PHYS_BASE, 941 &memory, &size); 942 memory_exclude_page(CVMX_PCIE_BAR1_PHYS_BASE + 943 CVMX_PCIE_BAR1_PHYS_SIZE, 944 &memory, &size); 945 #ifdef CONFIG_KEXEC 946 end = memory + mem_alloc_size; 947 948 /* 949 * This function automatically merges address regions 950 * next to each other if they are received in 951 * incrementing order 952 */ 953 if (memory < crashk_base && end > crashk_end) { 954 /* region is fully in */ 955 add_memory_region(memory, 956 crashk_base - memory, 957 BOOT_MEM_RAM); 958 total += crashk_base - memory; 959 add_memory_region(crashk_end, 960 end - crashk_end, 961 BOOT_MEM_RAM); 962 total += end - crashk_end; 963 continue; 964 } 965 966 if (memory >= crashk_base && end <= crashk_end) 967 /* 968 * Entire memory region is within the new 969 * kernel's memory, ignore it. 970 */ 971 continue; 972 973 if (memory > crashk_base && memory < crashk_end && 974 end > crashk_end) { 975 /* 976 * Overlap with the beginning of the region, 977 * reserve the beginning. 978 */ 979 mem_alloc_size -= crashk_end - memory; 980 memory = crashk_end; 981 } else if (memory < crashk_base && end > crashk_base && 982 end < crashk_end) 983 /* 984 * Overlap with the beginning of the region, 985 * chop of end. 986 */ 987 mem_alloc_size -= end - crashk_base; 988 #endif 989 add_memory_region(memory, mem_alloc_size, BOOT_MEM_RAM); 990 total += mem_alloc_size; 991 /* Recovering mem_alloc_size */ 992 mem_alloc_size = 4 << 20; 993 } else { 994 break; 995 } 996 } 997 cvmx_bootmem_unlock(); 998 /* Add the memory region for the kernel. */ 999 kernel_start = (unsigned long) _text; 1000 kernel_size = _end - _text; 1001 1002 /* Adjust for physical offset. */ 1003 kernel_start &= ~0xffffffff80000000ULL; 1004 add_memory_region(kernel_start, kernel_size, BOOT_MEM_RAM); 1005 #endif /* CONFIG_CRASH_DUMP */ 1006 1007 #ifdef CONFIG_CAVIUM_RESERVE32 1008 /* 1009 * Now that we've allocated the kernel memory it is safe to 1010 * free the reserved region. We free it here so that builtin 1011 * drivers can use the memory. 1012 */ 1013 if (octeon_reserve32_memory) 1014 cvmx_bootmem_free_named("CAVIUM_RESERVE32"); 1015 #endif /* CONFIG_CAVIUM_RESERVE32 */ 1016 1017 if (total == 0) 1018 panic("Unable to allocate memory from " 1019 "cvmx_bootmem_phy_alloc\n"); 1020 } 1021 1022 /* 1023 * Emit one character to the boot UART. Exported for use by the 1024 * watchdog timer. 1025 */ 1026 int prom_putchar(char c) 1027 { 1028 uint64_t lsrval; 1029 1030 /* Spin until there is room */ 1031 do { 1032 lsrval = cvmx_read_csr(CVMX_MIO_UARTX_LSR(octeon_uart)); 1033 } while ((lsrval & 0x20) == 0); 1034 1035 /* Write the byte */ 1036 cvmx_write_csr(CVMX_MIO_UARTX_THR(octeon_uart), c & 0xffull); 1037 return 1; 1038 } 1039 EXPORT_SYMBOL(prom_putchar); 1040 1041 void prom_free_prom_memory(void) 1042 { 1043 if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X)) { 1044 /* Check for presence of Core-14449 fix. */ 1045 u32 insn; 1046 u32 *foo; 1047 1048 foo = &insn; 1049 1050 asm volatile("# before" : : : "memory"); 1051 prefetch(foo); 1052 asm volatile( 1053 ".set push\n\t" 1054 ".set noreorder\n\t" 1055 "bal 1f\n\t" 1056 "nop\n" 1057 "1:\tlw %0,-12($31)\n\t" 1058 ".set pop\n\t" 1059 : "=r" (insn) : : "$31", "memory"); 1060 1061 if ((insn >> 26) != 0x33) 1062 panic("No PREF instruction at Core-14449 probe point."); 1063 1064 if (((insn >> 16) & 0x1f) != 28) 1065 panic("Core-14449 WAR not in place (%04x).\n" 1066 "Please build kernel with proper options (CONFIG_CAVIUM_CN63XXP1).", insn); 1067 } 1068 #ifdef CONFIG_CAVIUM_DECODE_RSL 1069 cvmx_interrupt_rsl_enable(); 1070 1071 /* Add an interrupt handler for general failures. */ 1072 if (request_irq(OCTEON_IRQ_RML, octeon_rlm_interrupt, IRQF_SHARED, 1073 "RML/RSL", octeon_rlm_interrupt)) { 1074 panic("Unable to request_irq(OCTEON_IRQ_RML)"); 1075 } 1076 #endif 1077 } 1078 1079 int octeon_prune_device_tree(void); 1080 1081 extern const char __dtb_octeon_3xxx_begin; 1082 extern const char __dtb_octeon_3xxx_end; 1083 extern const char __dtb_octeon_68xx_begin; 1084 extern const char __dtb_octeon_68xx_end; 1085 void __init device_tree_init(void) 1086 { 1087 int dt_size; 1088 struct boot_param_header *fdt; 1089 bool do_prune; 1090 1091 if (octeon_bootinfo->minor_version >= 3 && octeon_bootinfo->fdt_addr) { 1092 fdt = phys_to_virt(octeon_bootinfo->fdt_addr); 1093 if (fdt_check_header(fdt)) 1094 panic("Corrupt Device Tree passed to kernel."); 1095 dt_size = be32_to_cpu(fdt->totalsize); 1096 do_prune = false; 1097 } else if (OCTEON_IS_MODEL(OCTEON_CN68XX)) { 1098 fdt = (struct boot_param_header *)&__dtb_octeon_68xx_begin; 1099 dt_size = &__dtb_octeon_68xx_end - &__dtb_octeon_68xx_begin; 1100 do_prune = true; 1101 } else { 1102 fdt = (struct boot_param_header *)&__dtb_octeon_3xxx_begin; 1103 dt_size = &__dtb_octeon_3xxx_end - &__dtb_octeon_3xxx_begin; 1104 do_prune = true; 1105 } 1106 1107 /* Copy the default tree from init memory. */ 1108 initial_boot_params = early_init_dt_alloc_memory_arch(dt_size, 8); 1109 if (initial_boot_params == NULL) 1110 panic("Could not allocate initial_boot_params\n"); 1111 memcpy(initial_boot_params, fdt, dt_size); 1112 1113 if (do_prune) { 1114 octeon_prune_device_tree(); 1115 pr_info("Using internal Device Tree.\n"); 1116 } else { 1117 pr_info("Using passed Device Tree.\n"); 1118 } 1119 unflatten_device_tree(); 1120 } 1121 1122 static int __initdata disable_octeon_edac_p; 1123 1124 static int __init disable_octeon_edac(char *str) 1125 { 1126 disable_octeon_edac_p = 1; 1127 return 0; 1128 } 1129 early_param("disable_octeon_edac", disable_octeon_edac); 1130 1131 static char *edac_device_names[] = { 1132 "octeon_l2c_edac", 1133 "octeon_pc_edac", 1134 }; 1135 1136 static int __init edac_devinit(void) 1137 { 1138 struct platform_device *dev; 1139 int i, err = 0; 1140 int num_lmc; 1141 char *name; 1142 1143 if (disable_octeon_edac_p) 1144 return 0; 1145 1146 for (i = 0; i < ARRAY_SIZE(edac_device_names); i++) { 1147 name = edac_device_names[i]; 1148 dev = platform_device_register_simple(name, -1, NULL, 0); 1149 if (IS_ERR(dev)) { 1150 pr_err("Registation of %s failed!\n", name); 1151 err = PTR_ERR(dev); 1152 } 1153 } 1154 1155 num_lmc = OCTEON_IS_MODEL(OCTEON_CN68XX) ? 4 : 1156 (OCTEON_IS_MODEL(OCTEON_CN56XX) ? 2 : 1); 1157 for (i = 0; i < num_lmc; i++) { 1158 dev = platform_device_register_simple("octeon_lmc_edac", 1159 i, NULL, 0); 1160 if (IS_ERR(dev)) { 1161 pr_err("Registation of octeon_lmc_edac %d failed!\n", i); 1162 err = PTR_ERR(dev); 1163 } 1164 } 1165 1166 return err; 1167 } 1168 device_initcall(edac_devinit); 1169