1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2004-2007 Cavium Networks 7 * Copyright (C) 2008 Wind River Systems 8 */ 9 #include <linux/init.h> 10 #include <linux/console.h> 11 #include <linux/delay.h> 12 #include <linux/interrupt.h> 13 #include <linux/io.h> 14 #include <linux/serial.h> 15 #include <linux/smp.h> 16 #include <linux/types.h> 17 #include <linux/string.h> /* for memset */ 18 #include <linux/tty.h> 19 #include <linux/time.h> 20 #include <linux/platform_device.h> 21 #include <linux/serial_core.h> 22 #include <linux/serial_8250.h> 23 24 #include <asm/processor.h> 25 #include <asm/reboot.h> 26 #include <asm/smp-ops.h> 27 #include <asm/system.h> 28 #include <asm/irq_cpu.h> 29 #include <asm/mipsregs.h> 30 #include <asm/bootinfo.h> 31 #include <asm/sections.h> 32 #include <asm/time.h> 33 34 #include <asm/octeon/octeon.h> 35 #include <asm/octeon/pci-octeon.h> 36 #include <asm/octeon/cvmx-mio-defs.h> 37 38 #ifdef CONFIG_CAVIUM_DECODE_RSL 39 extern void cvmx_interrupt_rsl_decode(void); 40 extern int __cvmx_interrupt_ecc_report_single_bit_errors; 41 extern void cvmx_interrupt_rsl_enable(void); 42 #endif 43 44 extern struct plat_smp_ops octeon_smp_ops; 45 46 #ifdef CONFIG_PCI 47 extern void pci_console_init(const char *arg); 48 #endif 49 50 static unsigned long long MAX_MEMORY = 512ull << 20; 51 52 struct octeon_boot_descriptor *octeon_boot_desc_ptr; 53 54 struct cvmx_bootinfo *octeon_bootinfo; 55 EXPORT_SYMBOL(octeon_bootinfo); 56 57 #ifdef CONFIG_CAVIUM_RESERVE32 58 uint64_t octeon_reserve32_memory; 59 EXPORT_SYMBOL(octeon_reserve32_memory); 60 #endif 61 62 static int octeon_uart; 63 64 extern asmlinkage void handle_int(void); 65 extern asmlinkage void plat_irq_dispatch(void); 66 67 /** 68 * Return non zero if we are currently running in the Octeon simulator 69 * 70 * Returns 71 */ 72 int octeon_is_simulation(void) 73 { 74 return octeon_bootinfo->board_type == CVMX_BOARD_TYPE_SIM; 75 } 76 EXPORT_SYMBOL(octeon_is_simulation); 77 78 /** 79 * Return true if Octeon is in PCI Host mode. This means 80 * Linux can control the PCI bus. 81 * 82 * Returns Non zero if Octeon in host mode. 83 */ 84 int octeon_is_pci_host(void) 85 { 86 #ifdef CONFIG_PCI 87 return octeon_bootinfo->config_flags & CVMX_BOOTINFO_CFG_FLAG_PCI_HOST; 88 #else 89 return 0; 90 #endif 91 } 92 93 /** 94 * Get the clock rate of Octeon 95 * 96 * Returns Clock rate in HZ 97 */ 98 uint64_t octeon_get_clock_rate(void) 99 { 100 struct cvmx_sysinfo *sysinfo = cvmx_sysinfo_get(); 101 102 return sysinfo->cpu_clock_hz; 103 } 104 EXPORT_SYMBOL(octeon_get_clock_rate); 105 106 static u64 octeon_io_clock_rate; 107 108 u64 octeon_get_io_clock_rate(void) 109 { 110 return octeon_io_clock_rate; 111 } 112 EXPORT_SYMBOL(octeon_get_io_clock_rate); 113 114 115 /** 116 * Write to the LCD display connected to the bootbus. This display 117 * exists on most Cavium evaluation boards. If it doesn't exist, then 118 * this function doesn't do anything. 119 * 120 * @s: String to write 121 */ 122 void octeon_write_lcd(const char *s) 123 { 124 if (octeon_bootinfo->led_display_base_addr) { 125 void __iomem *lcd_address = 126 ioremap_nocache(octeon_bootinfo->led_display_base_addr, 127 8); 128 int i; 129 for (i = 0; i < 8; i++, s++) { 130 if (*s) 131 iowrite8(*s, lcd_address + i); 132 else 133 iowrite8(' ', lcd_address + i); 134 } 135 iounmap(lcd_address); 136 } 137 } 138 139 /** 140 * Return the console uart passed by the bootloader 141 * 142 * Returns uart (0 or 1) 143 */ 144 int octeon_get_boot_uart(void) 145 { 146 int uart; 147 #ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL 148 uart = 1; 149 #else 150 uart = (octeon_boot_desc_ptr->flags & OCTEON_BL_FLAG_CONSOLE_UART1) ? 151 1 : 0; 152 #endif 153 return uart; 154 } 155 156 /** 157 * Get the coremask Linux was booted on. 158 * 159 * Returns Core mask 160 */ 161 int octeon_get_boot_coremask(void) 162 { 163 return octeon_boot_desc_ptr->core_mask; 164 } 165 166 /** 167 * Check the hardware BIST results for a CPU 168 */ 169 void octeon_check_cpu_bist(void) 170 { 171 const int coreid = cvmx_get_core_num(); 172 unsigned long long mask; 173 unsigned long long bist_val; 174 175 /* Check BIST results for COP0 registers */ 176 mask = 0x1f00000000ull; 177 bist_val = read_octeon_c0_icacheerr(); 178 if (bist_val & mask) 179 pr_err("Core%d BIST Failure: CacheErr(icache) = 0x%llx\n", 180 coreid, bist_val); 181 182 bist_val = read_octeon_c0_dcacheerr(); 183 if (bist_val & 1) 184 pr_err("Core%d L1 Dcache parity error: " 185 "CacheErr(dcache) = 0x%llx\n", 186 coreid, bist_val); 187 188 mask = 0xfc00000000000000ull; 189 bist_val = read_c0_cvmmemctl(); 190 if (bist_val & mask) 191 pr_err("Core%d BIST Failure: COP0_CVM_MEM_CTL = 0x%llx\n", 192 coreid, bist_val); 193 194 write_octeon_c0_dcacheerr(0); 195 } 196 197 /** 198 * Reboot Octeon 199 * 200 * @command: Command to pass to the bootloader. Currently ignored. 201 */ 202 static void octeon_restart(char *command) 203 { 204 /* Disable all watchdogs before soft reset. They don't get cleared */ 205 #ifdef CONFIG_SMP 206 int cpu; 207 for_each_online_cpu(cpu) 208 cvmx_write_csr(CVMX_CIU_WDOGX(cpu_logical_map(cpu)), 0); 209 #else 210 cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0); 211 #endif 212 213 mb(); 214 while (1) 215 cvmx_write_csr(CVMX_CIU_SOFT_RST, 1); 216 } 217 218 219 /** 220 * Permanently stop a core. 221 * 222 * @arg: Ignored. 223 */ 224 static void octeon_kill_core(void *arg) 225 { 226 mb(); 227 if (octeon_is_simulation()) { 228 /* The simulator needs the watchdog to stop for dead cores */ 229 cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0); 230 /* A break instruction causes the simulator stop a core */ 231 asm volatile ("sync\nbreak"); 232 } 233 } 234 235 236 /** 237 * Halt the system 238 */ 239 static void octeon_halt(void) 240 { 241 smp_call_function(octeon_kill_core, NULL, 0); 242 243 switch (octeon_bootinfo->board_type) { 244 case CVMX_BOARD_TYPE_NAO38: 245 /* Driving a 1 to GPIO 12 shuts off this board */ 246 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(12), 1); 247 cvmx_write_csr(CVMX_GPIO_TX_SET, 0x1000); 248 break; 249 default: 250 octeon_write_lcd("PowerOff"); 251 break; 252 } 253 254 octeon_kill_core(NULL); 255 } 256 257 /** 258 * Handle all the error condition interrupts that might occur. 259 * 260 */ 261 #ifdef CONFIG_CAVIUM_DECODE_RSL 262 static irqreturn_t octeon_rlm_interrupt(int cpl, void *dev_id) 263 { 264 cvmx_interrupt_rsl_decode(); 265 return IRQ_HANDLED; 266 } 267 #endif 268 269 /** 270 * Return a string representing the system type 271 * 272 * Returns 273 */ 274 const char *octeon_board_type_string(void) 275 { 276 static char name[80]; 277 sprintf(name, "%s (%s)", 278 cvmx_board_type_to_string(octeon_bootinfo->board_type), 279 octeon_model_get_string(read_c0_prid())); 280 return name; 281 } 282 283 const char *get_system_type(void) 284 __attribute__ ((alias("octeon_board_type_string"))); 285 286 void octeon_user_io_init(void) 287 { 288 union octeon_cvmemctl cvmmemctl; 289 union cvmx_iob_fau_timeout fau_timeout; 290 union cvmx_pow_nw_tim nm_tim; 291 292 /* Get the current settings for CP0_CVMMEMCTL_REG */ 293 cvmmemctl.u64 = read_c0_cvmmemctl(); 294 /* R/W If set, marked write-buffer entries time out the same 295 * as as other entries; if clear, marked write-buffer entries 296 * use the maximum timeout. */ 297 cvmmemctl.s.dismarkwblongto = 1; 298 /* R/W If set, a merged store does not clear the write-buffer 299 * entry timeout state. */ 300 cvmmemctl.s.dismrgclrwbto = 0; 301 /* R/W Two bits that are the MSBs of the resultant CVMSEG LM 302 * word location for an IOBDMA. The other 8 bits come from the 303 * SCRADDR field of the IOBDMA. */ 304 cvmmemctl.s.iobdmascrmsb = 0; 305 /* R/W If set, SYNCWS and SYNCS only order marked stores; if 306 * clear, SYNCWS and SYNCS only order unmarked 307 * stores. SYNCWSMARKED has no effect when DISSYNCWS is 308 * set. */ 309 cvmmemctl.s.syncwsmarked = 0; 310 /* R/W If set, SYNCWS acts as SYNCW and SYNCS acts as SYNC. */ 311 cvmmemctl.s.dissyncws = 0; 312 /* R/W If set, no stall happens on write buffer full. */ 313 if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2)) 314 cvmmemctl.s.diswbfst = 1; 315 else 316 cvmmemctl.s.diswbfst = 0; 317 /* R/W If set (and SX set), supervisor-level loads/stores can 318 * use XKPHYS addresses with <48>==0 */ 319 cvmmemctl.s.xkmemenas = 0; 320 321 /* R/W If set (and UX set), user-level loads/stores can use 322 * XKPHYS addresses with VA<48>==0 */ 323 cvmmemctl.s.xkmemenau = 0; 324 325 /* R/W If set (and SX set), supervisor-level loads/stores can 326 * use XKPHYS addresses with VA<48>==1 */ 327 cvmmemctl.s.xkioenas = 0; 328 329 /* R/W If set (and UX set), user-level loads/stores can use 330 * XKPHYS addresses with VA<48>==1 */ 331 cvmmemctl.s.xkioenau = 0; 332 333 /* R/W If set, all stores act as SYNCW (NOMERGE must be set 334 * when this is set) RW, reset to 0. */ 335 cvmmemctl.s.allsyncw = 0; 336 337 /* R/W If set, no stores merge, and all stores reach the 338 * coherent bus in order. */ 339 cvmmemctl.s.nomerge = 0; 340 /* R/W Selects the bit in the counter used for DID time-outs 0 341 * = 231, 1 = 230, 2 = 229, 3 = 214. Actual time-out is 342 * between 1x and 2x this interval. For example, with 343 * DIDTTO=3, expiration interval is between 16K and 32K. */ 344 cvmmemctl.s.didtto = 0; 345 /* R/W If set, the (mem) CSR clock never turns off. */ 346 cvmmemctl.s.csrckalwys = 0; 347 /* R/W If set, mclk never turns off. */ 348 cvmmemctl.s.mclkalwys = 0; 349 /* R/W Selects the bit in the counter used for write buffer 350 * flush time-outs (WBFLT+11) is the bit position in an 351 * internal counter used to determine expiration. The write 352 * buffer expires between 1x and 2x this interval. For 353 * example, with WBFLT = 0, a write buffer expires between 2K 354 * and 4K cycles after the write buffer entry is allocated. */ 355 cvmmemctl.s.wbfltime = 0; 356 /* R/W If set, do not put Istream in the L2 cache. */ 357 cvmmemctl.s.istrnol2 = 0; 358 359 /* 360 * R/W The write buffer threshold. As per erratum Core-14752 361 * for CN63XX, a sc/scd might fail if the write buffer is 362 * full. Lowering WBTHRESH greatly lowers the chances of the 363 * write buffer ever being full and triggering the erratum. 364 */ 365 if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X)) 366 cvmmemctl.s.wbthresh = 4; 367 else 368 cvmmemctl.s.wbthresh = 10; 369 370 /* R/W If set, CVMSEG is available for loads/stores in 371 * kernel/debug mode. */ 372 #if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0 373 cvmmemctl.s.cvmsegenak = 1; 374 #else 375 cvmmemctl.s.cvmsegenak = 0; 376 #endif 377 /* R/W If set, CVMSEG is available for loads/stores in 378 * supervisor mode. */ 379 cvmmemctl.s.cvmsegenas = 0; 380 /* R/W If set, CVMSEG is available for loads/stores in user 381 * mode. */ 382 cvmmemctl.s.cvmsegenau = 0; 383 /* R/W Size of local memory in cache blocks, 54 (6912 bytes) 384 * is max legal value. */ 385 cvmmemctl.s.lmemsz = CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE; 386 387 write_c0_cvmmemctl(cvmmemctl.u64); 388 389 if (smp_processor_id() == 0) 390 pr_notice("CVMSEG size: %d cache lines (%d bytes)\n", 391 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE, 392 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128); 393 394 /* Set a default for the hardware timeouts */ 395 fau_timeout.u64 = 0; 396 fau_timeout.s.tout_val = 0xfff; 397 /* Disable tagwait FAU timeout */ 398 fau_timeout.s.tout_enb = 0; 399 cvmx_write_csr(CVMX_IOB_FAU_TIMEOUT, fau_timeout.u64); 400 401 nm_tim.u64 = 0; 402 /* 4096 cycles */ 403 nm_tim.s.nw_tim = 3; 404 cvmx_write_csr(CVMX_POW_NW_TIM, nm_tim.u64); 405 406 write_octeon_c0_icacheerr(0); 407 write_c0_derraddr1(0); 408 } 409 410 /** 411 * Early entry point for arch setup 412 */ 413 void __init prom_init(void) 414 { 415 struct cvmx_sysinfo *sysinfo; 416 int i; 417 int argc; 418 #ifdef CONFIG_CAVIUM_RESERVE32 419 int64_t addr = -1; 420 #endif 421 /* 422 * The bootloader passes a pointer to the boot descriptor in 423 * $a3, this is available as fw_arg3. 424 */ 425 octeon_boot_desc_ptr = (struct octeon_boot_descriptor *)fw_arg3; 426 octeon_bootinfo = 427 cvmx_phys_to_ptr(octeon_boot_desc_ptr->cvmx_desc_vaddr); 428 cvmx_bootmem_init(cvmx_phys_to_ptr(octeon_bootinfo->phy_mem_desc_addr)); 429 430 sysinfo = cvmx_sysinfo_get(); 431 memset(sysinfo, 0, sizeof(*sysinfo)); 432 sysinfo->system_dram_size = octeon_bootinfo->dram_size << 20; 433 sysinfo->phy_mem_desc_ptr = 434 cvmx_phys_to_ptr(octeon_bootinfo->phy_mem_desc_addr); 435 sysinfo->core_mask = octeon_bootinfo->core_mask; 436 sysinfo->exception_base_addr = octeon_bootinfo->exception_base_addr; 437 sysinfo->cpu_clock_hz = octeon_bootinfo->eclock_hz; 438 sysinfo->dram_data_rate_hz = octeon_bootinfo->dclock_hz * 2; 439 sysinfo->board_type = octeon_bootinfo->board_type; 440 sysinfo->board_rev_major = octeon_bootinfo->board_rev_major; 441 sysinfo->board_rev_minor = octeon_bootinfo->board_rev_minor; 442 memcpy(sysinfo->mac_addr_base, octeon_bootinfo->mac_addr_base, 443 sizeof(sysinfo->mac_addr_base)); 444 sysinfo->mac_addr_count = octeon_bootinfo->mac_addr_count; 445 memcpy(sysinfo->board_serial_number, 446 octeon_bootinfo->board_serial_number, 447 sizeof(sysinfo->board_serial_number)); 448 sysinfo->compact_flash_common_base_addr = 449 octeon_bootinfo->compact_flash_common_base_addr; 450 sysinfo->compact_flash_attribute_base_addr = 451 octeon_bootinfo->compact_flash_attribute_base_addr; 452 sysinfo->led_display_base_addr = octeon_bootinfo->led_display_base_addr; 453 sysinfo->dfa_ref_clock_hz = octeon_bootinfo->dfa_ref_clock_hz; 454 sysinfo->bootloader_config_flags = octeon_bootinfo->config_flags; 455 456 if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) { 457 /* I/O clock runs at a different rate than the CPU. */ 458 union cvmx_mio_rst_boot rst_boot; 459 rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT); 460 octeon_io_clock_rate = 50000000 * rst_boot.s.pnr_mul; 461 } else { 462 octeon_io_clock_rate = sysinfo->cpu_clock_hz; 463 } 464 465 /* 466 * Only enable the LED controller if we're running on a CN38XX, CN58XX, 467 * or CN56XX. The CN30XX and CN31XX don't have an LED controller. 468 */ 469 if (!octeon_is_simulation() && 470 octeon_has_feature(OCTEON_FEATURE_LED_CONTROLLER)) { 471 cvmx_write_csr(CVMX_LED_EN, 0); 472 cvmx_write_csr(CVMX_LED_PRT, 0); 473 cvmx_write_csr(CVMX_LED_DBG, 0); 474 cvmx_write_csr(CVMX_LED_PRT_FMT, 0); 475 cvmx_write_csr(CVMX_LED_UDD_CNTX(0), 32); 476 cvmx_write_csr(CVMX_LED_UDD_CNTX(1), 32); 477 cvmx_write_csr(CVMX_LED_UDD_DATX(0), 0); 478 cvmx_write_csr(CVMX_LED_UDD_DATX(1), 0); 479 cvmx_write_csr(CVMX_LED_EN, 1); 480 } 481 #ifdef CONFIG_CAVIUM_RESERVE32 482 /* 483 * We need to temporarily allocate all memory in the reserve32 484 * region. This makes sure the kernel doesn't allocate this 485 * memory when it is getting memory from the 486 * bootloader. Later, after the memory allocations are 487 * complete, the reserve32 will be freed. 488 * 489 * Allocate memory for RESERVED32 aligned on 2MB boundary. This 490 * is in case we later use hugetlb entries with it. 491 */ 492 addr = cvmx_bootmem_phy_named_block_alloc(CONFIG_CAVIUM_RESERVE32 << 20, 493 0, 0, 2 << 20, 494 "CAVIUM_RESERVE32", 0); 495 if (addr < 0) 496 pr_err("Failed to allocate CAVIUM_RESERVE32 memory area\n"); 497 else 498 octeon_reserve32_memory = addr; 499 #endif 500 501 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2 502 if (cvmx_read_csr(CVMX_L2D_FUS3) & (3ull << 34)) { 503 pr_info("Skipping L2 locking due to reduced L2 cache size\n"); 504 } else { 505 uint32_t ebase = read_c0_ebase() & 0x3ffff000; 506 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_TLB 507 /* TLB refill */ 508 cvmx_l2c_lock_mem_region(ebase, 0x100); 509 #endif 510 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_EXCEPTION 511 /* General exception */ 512 cvmx_l2c_lock_mem_region(ebase + 0x180, 0x80); 513 #endif 514 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT 515 /* Interrupt handler */ 516 cvmx_l2c_lock_mem_region(ebase + 0x200, 0x80); 517 #endif 518 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_INTERRUPT 519 cvmx_l2c_lock_mem_region(__pa_symbol(handle_int), 0x100); 520 cvmx_l2c_lock_mem_region(__pa_symbol(plat_irq_dispatch), 0x80); 521 #endif 522 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_MEMCPY 523 cvmx_l2c_lock_mem_region(__pa_symbol(memcpy), 0x480); 524 #endif 525 } 526 #endif 527 528 octeon_check_cpu_bist(); 529 530 octeon_uart = octeon_get_boot_uart(); 531 532 #ifdef CONFIG_SMP 533 octeon_write_lcd("LinuxSMP"); 534 #else 535 octeon_write_lcd("Linux"); 536 #endif 537 538 #ifdef CONFIG_CAVIUM_GDB 539 /* 540 * When debugging the linux kernel, force the cores to enter 541 * the debug exception handler to break in. 542 */ 543 if (octeon_get_boot_debug_flag()) { 544 cvmx_write_csr(CVMX_CIU_DINT, 1 << cvmx_get_core_num()); 545 cvmx_read_csr(CVMX_CIU_DINT); 546 } 547 #endif 548 549 /* 550 * BIST should always be enabled when doing a soft reset. L2 551 * Cache locking for instance is not cleared unless BIST is 552 * enabled. Unfortunately due to a chip errata G-200 for 553 * Cn38XX and CN31XX, BIST msut be disabled on these parts. 554 */ 555 if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2) || 556 OCTEON_IS_MODEL(OCTEON_CN31XX)) 557 cvmx_write_csr(CVMX_CIU_SOFT_BIST, 0); 558 else 559 cvmx_write_csr(CVMX_CIU_SOFT_BIST, 1); 560 561 /* Default to 64MB in the simulator to speed things up */ 562 if (octeon_is_simulation()) 563 MAX_MEMORY = 64ull << 20; 564 565 arcs_cmdline[0] = 0; 566 argc = octeon_boot_desc_ptr->argc; 567 for (i = 0; i < argc; i++) { 568 const char *arg = 569 cvmx_phys_to_ptr(octeon_boot_desc_ptr->argv[i]); 570 if ((strncmp(arg, "MEM=", 4) == 0) || 571 (strncmp(arg, "mem=", 4) == 0)) { 572 sscanf(arg + 4, "%llu", &MAX_MEMORY); 573 MAX_MEMORY <<= 20; 574 if (MAX_MEMORY == 0) 575 MAX_MEMORY = 32ull << 30; 576 } else if (strcmp(arg, "ecc_verbose") == 0) { 577 #ifdef CONFIG_CAVIUM_REPORT_SINGLE_BIT_ECC 578 __cvmx_interrupt_ecc_report_single_bit_errors = 1; 579 pr_notice("Reporting of single bit ECC errors is " 580 "turned on\n"); 581 #endif 582 } else if (strlen(arcs_cmdline) + strlen(arg) + 1 < 583 sizeof(arcs_cmdline) - 1) { 584 strcat(arcs_cmdline, " "); 585 strcat(arcs_cmdline, arg); 586 } 587 } 588 589 if (strstr(arcs_cmdline, "console=") == NULL) { 590 #ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL 591 strcat(arcs_cmdline, " console=ttyS0,115200"); 592 #else 593 if (octeon_uart == 1) 594 strcat(arcs_cmdline, " console=ttyS1,115200"); 595 else 596 strcat(arcs_cmdline, " console=ttyS0,115200"); 597 #endif 598 } 599 600 if (octeon_is_simulation()) { 601 /* 602 * The simulator uses a mtdram device pre filled with 603 * the filesystem. Also specify the calibration delay 604 * to avoid calculating it every time. 605 */ 606 strcat(arcs_cmdline, " rw root=1f00 slram=root,0x40000000,+1073741824"); 607 } 608 609 mips_hpt_frequency = octeon_get_clock_rate(); 610 611 octeon_init_cvmcount(); 612 octeon_setup_delays(); 613 614 _machine_restart = octeon_restart; 615 _machine_halt = octeon_halt; 616 617 octeon_user_io_init(); 618 register_smp_ops(&octeon_smp_ops); 619 } 620 621 /* Exclude a single page from the regions obtained in plat_mem_setup. */ 622 static __init void memory_exclude_page(u64 addr, u64 *mem, u64 *size) 623 { 624 if (addr > *mem && addr < *mem + *size) { 625 u64 inc = addr - *mem; 626 add_memory_region(*mem, inc, BOOT_MEM_RAM); 627 *mem += inc; 628 *size -= inc; 629 } 630 631 if (addr == *mem && *size > PAGE_SIZE) { 632 *mem += PAGE_SIZE; 633 *size -= PAGE_SIZE; 634 } 635 } 636 637 void __init plat_mem_setup(void) 638 { 639 uint64_t mem_alloc_size; 640 uint64_t total; 641 int64_t memory; 642 643 total = 0; 644 645 /* First add the init memory we will be returning. */ 646 memory = __pa_symbol(&__init_begin) & PAGE_MASK; 647 mem_alloc_size = (__pa_symbol(&__init_end) & PAGE_MASK) - memory; 648 if (mem_alloc_size > 0) { 649 add_memory_region(memory, mem_alloc_size, BOOT_MEM_RAM); 650 total += mem_alloc_size; 651 } 652 653 /* 654 * The Mips memory init uses the first memory location for 655 * some memory vectors. When SPARSEMEM is in use, it doesn't 656 * verify that the size is big enough for the final 657 * vectors. Making the smallest chuck 4MB seems to be enough 658 * to consistently work. 659 */ 660 mem_alloc_size = 4 << 20; 661 if (mem_alloc_size > MAX_MEMORY) 662 mem_alloc_size = MAX_MEMORY; 663 664 /* 665 * When allocating memory, we want incrementing addresses from 666 * bootmem_alloc so the code in add_memory_region can merge 667 * regions next to each other. 668 */ 669 cvmx_bootmem_lock(); 670 while ((boot_mem_map.nr_map < BOOT_MEM_MAP_MAX) 671 && (total < MAX_MEMORY)) { 672 #if defined(CONFIG_64BIT) || defined(CONFIG_64BIT_PHYS_ADDR) 673 memory = cvmx_bootmem_phy_alloc(mem_alloc_size, 674 __pa_symbol(&__init_end), -1, 675 0x100000, 676 CVMX_BOOTMEM_FLAG_NO_LOCKING); 677 #elif defined(CONFIG_HIGHMEM) 678 memory = cvmx_bootmem_phy_alloc(mem_alloc_size, 0, 1ull << 31, 679 0x100000, 680 CVMX_BOOTMEM_FLAG_NO_LOCKING); 681 #else 682 memory = cvmx_bootmem_phy_alloc(mem_alloc_size, 0, 512 << 20, 683 0x100000, 684 CVMX_BOOTMEM_FLAG_NO_LOCKING); 685 #endif 686 if (memory >= 0) { 687 u64 size = mem_alloc_size; 688 689 /* 690 * exclude a page at the beginning and end of 691 * the 256MB PCIe 'hole' so the kernel will not 692 * try to allocate multi-page buffers that 693 * span the discontinuity. 694 */ 695 memory_exclude_page(CVMX_PCIE_BAR1_PHYS_BASE, 696 &memory, &size); 697 memory_exclude_page(CVMX_PCIE_BAR1_PHYS_BASE + 698 CVMX_PCIE_BAR1_PHYS_SIZE, 699 &memory, &size); 700 701 /* 702 * This function automatically merges address 703 * regions next to each other if they are 704 * received in incrementing order. 705 */ 706 if (size) 707 add_memory_region(memory, size, BOOT_MEM_RAM); 708 total += mem_alloc_size; 709 } else { 710 break; 711 } 712 } 713 cvmx_bootmem_unlock(); 714 715 #ifdef CONFIG_CAVIUM_RESERVE32 716 /* 717 * Now that we've allocated the kernel memory it is safe to 718 * free the reserved region. We free it here so that builtin 719 * drivers can use the memory. 720 */ 721 if (octeon_reserve32_memory) 722 cvmx_bootmem_free_named("CAVIUM_RESERVE32"); 723 #endif /* CONFIG_CAVIUM_RESERVE32 */ 724 725 if (total == 0) 726 panic("Unable to allocate memory from " 727 "cvmx_bootmem_phy_alloc\n"); 728 } 729 730 /* 731 * Emit one character to the boot UART. Exported for use by the 732 * watchdog timer. 733 */ 734 int prom_putchar(char c) 735 { 736 uint64_t lsrval; 737 738 /* Spin until there is room */ 739 do { 740 lsrval = cvmx_read_csr(CVMX_MIO_UARTX_LSR(octeon_uart)); 741 } while ((lsrval & 0x20) == 0); 742 743 /* Write the byte */ 744 cvmx_write_csr(CVMX_MIO_UARTX_THR(octeon_uart), c & 0xffull); 745 return 1; 746 } 747 EXPORT_SYMBOL(prom_putchar); 748 749 void prom_free_prom_memory(void) 750 { 751 if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X)) { 752 /* Check for presence of Core-14449 fix. */ 753 u32 insn; 754 u32 *foo; 755 756 foo = &insn; 757 758 asm volatile("# before" : : : "memory"); 759 prefetch(foo); 760 asm volatile( 761 ".set push\n\t" 762 ".set noreorder\n\t" 763 "bal 1f\n\t" 764 "nop\n" 765 "1:\tlw %0,-12($31)\n\t" 766 ".set pop\n\t" 767 : "=r" (insn) : : "$31", "memory"); 768 769 if ((insn >> 26) != 0x33) 770 panic("No PREF instruction at Core-14449 probe point.\n"); 771 772 if (((insn >> 16) & 0x1f) != 28) 773 panic("Core-14449 WAR not in place (%04x).\n" 774 "Please build kernel with proper options (CONFIG_CAVIUM_CN63XXP1).\n", insn); 775 } 776 #ifdef CONFIG_CAVIUM_DECODE_RSL 777 cvmx_interrupt_rsl_enable(); 778 779 /* Add an interrupt handler for general failures. */ 780 if (request_irq(OCTEON_IRQ_RML, octeon_rlm_interrupt, IRQF_SHARED, 781 "RML/RSL", octeon_rlm_interrupt)) { 782 panic("Unable to request_irq(OCTEON_IRQ_RML)\n"); 783 } 784 #endif 785 } 786