1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2004-2007 Cavium Networks 7 * Copyright (C) 2008 Wind River Systems 8 */ 9 #include <linux/init.h> 10 #include <linux/console.h> 11 #include <linux/delay.h> 12 #include <linux/export.h> 13 #include <linux/interrupt.h> 14 #include <linux/io.h> 15 #include <linux/serial.h> 16 #include <linux/smp.h> 17 #include <linux/types.h> 18 #include <linux/string.h> /* for memset */ 19 #include <linux/tty.h> 20 #include <linux/time.h> 21 #include <linux/platform_device.h> 22 #include <linux/serial_core.h> 23 #include <linux/serial_8250.h> 24 #include <linux/of_fdt.h> 25 #include <linux/libfdt.h> 26 27 #include <asm/processor.h> 28 #include <asm/reboot.h> 29 #include <asm/smp-ops.h> 30 #include <asm/irq_cpu.h> 31 #include <asm/mipsregs.h> 32 #include <asm/bootinfo.h> 33 #include <asm/sections.h> 34 #include <asm/time.h> 35 36 #include <asm/octeon/octeon.h> 37 #include <asm/octeon/pci-octeon.h> 38 #include <asm/octeon/cvmx-mio-defs.h> 39 40 #ifdef CONFIG_CAVIUM_DECODE_RSL 41 extern void cvmx_interrupt_rsl_decode(void); 42 extern int __cvmx_interrupt_ecc_report_single_bit_errors; 43 extern void cvmx_interrupt_rsl_enable(void); 44 #endif 45 46 extern struct plat_smp_ops octeon_smp_ops; 47 48 #ifdef CONFIG_PCI 49 extern void pci_console_init(const char *arg); 50 #endif 51 52 static unsigned long long MAX_MEMORY = 512ull << 20; 53 54 struct octeon_boot_descriptor *octeon_boot_desc_ptr; 55 56 struct cvmx_bootinfo *octeon_bootinfo; 57 EXPORT_SYMBOL(octeon_bootinfo); 58 59 #ifdef CONFIG_CAVIUM_RESERVE32 60 uint64_t octeon_reserve32_memory; 61 EXPORT_SYMBOL(octeon_reserve32_memory); 62 #endif 63 64 static int octeon_uart; 65 66 extern asmlinkage void handle_int(void); 67 extern asmlinkage void plat_irq_dispatch(void); 68 69 /** 70 * Return non zero if we are currently running in the Octeon simulator 71 * 72 * Returns 73 */ 74 int octeon_is_simulation(void) 75 { 76 return octeon_bootinfo->board_type == CVMX_BOARD_TYPE_SIM; 77 } 78 EXPORT_SYMBOL(octeon_is_simulation); 79 80 /** 81 * Return true if Octeon is in PCI Host mode. This means 82 * Linux can control the PCI bus. 83 * 84 * Returns Non zero if Octeon in host mode. 85 */ 86 int octeon_is_pci_host(void) 87 { 88 #ifdef CONFIG_PCI 89 return octeon_bootinfo->config_flags & CVMX_BOOTINFO_CFG_FLAG_PCI_HOST; 90 #else 91 return 0; 92 #endif 93 } 94 95 /** 96 * Get the clock rate of Octeon 97 * 98 * Returns Clock rate in HZ 99 */ 100 uint64_t octeon_get_clock_rate(void) 101 { 102 struct cvmx_sysinfo *sysinfo = cvmx_sysinfo_get(); 103 104 return sysinfo->cpu_clock_hz; 105 } 106 EXPORT_SYMBOL(octeon_get_clock_rate); 107 108 static u64 octeon_io_clock_rate; 109 110 u64 octeon_get_io_clock_rate(void) 111 { 112 return octeon_io_clock_rate; 113 } 114 EXPORT_SYMBOL(octeon_get_io_clock_rate); 115 116 117 /** 118 * Write to the LCD display connected to the bootbus. This display 119 * exists on most Cavium evaluation boards. If it doesn't exist, then 120 * this function doesn't do anything. 121 * 122 * @s: String to write 123 */ 124 void octeon_write_lcd(const char *s) 125 { 126 if (octeon_bootinfo->led_display_base_addr) { 127 void __iomem *lcd_address = 128 ioremap_nocache(octeon_bootinfo->led_display_base_addr, 129 8); 130 int i; 131 for (i = 0; i < 8; i++, s++) { 132 if (*s) 133 iowrite8(*s, lcd_address + i); 134 else 135 iowrite8(' ', lcd_address + i); 136 } 137 iounmap(lcd_address); 138 } 139 } 140 141 /** 142 * Return the console uart passed by the bootloader 143 * 144 * Returns uart (0 or 1) 145 */ 146 int octeon_get_boot_uart(void) 147 { 148 int uart; 149 #ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL 150 uart = 1; 151 #else 152 uart = (octeon_boot_desc_ptr->flags & OCTEON_BL_FLAG_CONSOLE_UART1) ? 153 1 : 0; 154 #endif 155 return uart; 156 } 157 158 /** 159 * Get the coremask Linux was booted on. 160 * 161 * Returns Core mask 162 */ 163 int octeon_get_boot_coremask(void) 164 { 165 return octeon_boot_desc_ptr->core_mask; 166 } 167 168 /** 169 * Check the hardware BIST results for a CPU 170 */ 171 void octeon_check_cpu_bist(void) 172 { 173 const int coreid = cvmx_get_core_num(); 174 unsigned long long mask; 175 unsigned long long bist_val; 176 177 /* Check BIST results for COP0 registers */ 178 mask = 0x1f00000000ull; 179 bist_val = read_octeon_c0_icacheerr(); 180 if (bist_val & mask) 181 pr_err("Core%d BIST Failure: CacheErr(icache) = 0x%llx\n", 182 coreid, bist_val); 183 184 bist_val = read_octeon_c0_dcacheerr(); 185 if (bist_val & 1) 186 pr_err("Core%d L1 Dcache parity error: " 187 "CacheErr(dcache) = 0x%llx\n", 188 coreid, bist_val); 189 190 mask = 0xfc00000000000000ull; 191 bist_val = read_c0_cvmmemctl(); 192 if (bist_val & mask) 193 pr_err("Core%d BIST Failure: COP0_CVM_MEM_CTL = 0x%llx\n", 194 coreid, bist_val); 195 196 write_octeon_c0_dcacheerr(0); 197 } 198 199 /** 200 * Reboot Octeon 201 * 202 * @command: Command to pass to the bootloader. Currently ignored. 203 */ 204 static void octeon_restart(char *command) 205 { 206 /* Disable all watchdogs before soft reset. They don't get cleared */ 207 #ifdef CONFIG_SMP 208 int cpu; 209 for_each_online_cpu(cpu) 210 cvmx_write_csr(CVMX_CIU_WDOGX(cpu_logical_map(cpu)), 0); 211 #else 212 cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0); 213 #endif 214 215 mb(); 216 while (1) 217 cvmx_write_csr(CVMX_CIU_SOFT_RST, 1); 218 } 219 220 221 /** 222 * Permanently stop a core. 223 * 224 * @arg: Ignored. 225 */ 226 static void octeon_kill_core(void *arg) 227 { 228 mb(); 229 if (octeon_is_simulation()) { 230 /* The simulator needs the watchdog to stop for dead cores */ 231 cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0); 232 /* A break instruction causes the simulator stop a core */ 233 asm volatile ("sync\nbreak"); 234 } 235 } 236 237 238 /** 239 * Halt the system 240 */ 241 static void octeon_halt(void) 242 { 243 smp_call_function(octeon_kill_core, NULL, 0); 244 245 switch (octeon_bootinfo->board_type) { 246 case CVMX_BOARD_TYPE_NAO38: 247 /* Driving a 1 to GPIO 12 shuts off this board */ 248 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(12), 1); 249 cvmx_write_csr(CVMX_GPIO_TX_SET, 0x1000); 250 break; 251 default: 252 octeon_write_lcd("PowerOff"); 253 break; 254 } 255 256 octeon_kill_core(NULL); 257 } 258 259 /** 260 * Handle all the error condition interrupts that might occur. 261 * 262 */ 263 #ifdef CONFIG_CAVIUM_DECODE_RSL 264 static irqreturn_t octeon_rlm_interrupt(int cpl, void *dev_id) 265 { 266 cvmx_interrupt_rsl_decode(); 267 return IRQ_HANDLED; 268 } 269 #endif 270 271 /** 272 * Return a string representing the system type 273 * 274 * Returns 275 */ 276 const char *octeon_board_type_string(void) 277 { 278 static char name[80]; 279 sprintf(name, "%s (%s)", 280 cvmx_board_type_to_string(octeon_bootinfo->board_type), 281 octeon_model_get_string(read_c0_prid())); 282 return name; 283 } 284 285 const char *get_system_type(void) 286 __attribute__ ((alias("octeon_board_type_string"))); 287 288 void octeon_user_io_init(void) 289 { 290 union octeon_cvmemctl cvmmemctl; 291 union cvmx_iob_fau_timeout fau_timeout; 292 union cvmx_pow_nw_tim nm_tim; 293 294 /* Get the current settings for CP0_CVMMEMCTL_REG */ 295 cvmmemctl.u64 = read_c0_cvmmemctl(); 296 /* R/W If set, marked write-buffer entries time out the same 297 * as as other entries; if clear, marked write-buffer entries 298 * use the maximum timeout. */ 299 cvmmemctl.s.dismarkwblongto = 1; 300 /* R/W If set, a merged store does not clear the write-buffer 301 * entry timeout state. */ 302 cvmmemctl.s.dismrgclrwbto = 0; 303 /* R/W Two bits that are the MSBs of the resultant CVMSEG LM 304 * word location for an IOBDMA. The other 8 bits come from the 305 * SCRADDR field of the IOBDMA. */ 306 cvmmemctl.s.iobdmascrmsb = 0; 307 /* R/W If set, SYNCWS and SYNCS only order marked stores; if 308 * clear, SYNCWS and SYNCS only order unmarked 309 * stores. SYNCWSMARKED has no effect when DISSYNCWS is 310 * set. */ 311 cvmmemctl.s.syncwsmarked = 0; 312 /* R/W If set, SYNCWS acts as SYNCW and SYNCS acts as SYNC. */ 313 cvmmemctl.s.dissyncws = 0; 314 /* R/W If set, no stall happens on write buffer full. */ 315 if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2)) 316 cvmmemctl.s.diswbfst = 1; 317 else 318 cvmmemctl.s.diswbfst = 0; 319 /* R/W If set (and SX set), supervisor-level loads/stores can 320 * use XKPHYS addresses with <48>==0 */ 321 cvmmemctl.s.xkmemenas = 0; 322 323 /* R/W If set (and UX set), user-level loads/stores can use 324 * XKPHYS addresses with VA<48>==0 */ 325 cvmmemctl.s.xkmemenau = 0; 326 327 /* R/W If set (and SX set), supervisor-level loads/stores can 328 * use XKPHYS addresses with VA<48>==1 */ 329 cvmmemctl.s.xkioenas = 0; 330 331 /* R/W If set (and UX set), user-level loads/stores can use 332 * XKPHYS addresses with VA<48>==1 */ 333 cvmmemctl.s.xkioenau = 0; 334 335 /* R/W If set, all stores act as SYNCW (NOMERGE must be set 336 * when this is set) RW, reset to 0. */ 337 cvmmemctl.s.allsyncw = 0; 338 339 /* R/W If set, no stores merge, and all stores reach the 340 * coherent bus in order. */ 341 cvmmemctl.s.nomerge = 0; 342 /* R/W Selects the bit in the counter used for DID time-outs 0 343 * = 231, 1 = 230, 2 = 229, 3 = 214. Actual time-out is 344 * between 1x and 2x this interval. For example, with 345 * DIDTTO=3, expiration interval is between 16K and 32K. */ 346 cvmmemctl.s.didtto = 0; 347 /* R/W If set, the (mem) CSR clock never turns off. */ 348 cvmmemctl.s.csrckalwys = 0; 349 /* R/W If set, mclk never turns off. */ 350 cvmmemctl.s.mclkalwys = 0; 351 /* R/W Selects the bit in the counter used for write buffer 352 * flush time-outs (WBFLT+11) is the bit position in an 353 * internal counter used to determine expiration. The write 354 * buffer expires between 1x and 2x this interval. For 355 * example, with WBFLT = 0, a write buffer expires between 2K 356 * and 4K cycles after the write buffer entry is allocated. */ 357 cvmmemctl.s.wbfltime = 0; 358 /* R/W If set, do not put Istream in the L2 cache. */ 359 cvmmemctl.s.istrnol2 = 0; 360 361 /* 362 * R/W The write buffer threshold. As per erratum Core-14752 363 * for CN63XX, a sc/scd might fail if the write buffer is 364 * full. Lowering WBTHRESH greatly lowers the chances of the 365 * write buffer ever being full and triggering the erratum. 366 */ 367 if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X)) 368 cvmmemctl.s.wbthresh = 4; 369 else 370 cvmmemctl.s.wbthresh = 10; 371 372 /* R/W If set, CVMSEG is available for loads/stores in 373 * kernel/debug mode. */ 374 #if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0 375 cvmmemctl.s.cvmsegenak = 1; 376 #else 377 cvmmemctl.s.cvmsegenak = 0; 378 #endif 379 /* R/W If set, CVMSEG is available for loads/stores in 380 * supervisor mode. */ 381 cvmmemctl.s.cvmsegenas = 0; 382 /* R/W If set, CVMSEG is available for loads/stores in user 383 * mode. */ 384 cvmmemctl.s.cvmsegenau = 0; 385 /* R/W Size of local memory in cache blocks, 54 (6912 bytes) 386 * is max legal value. */ 387 cvmmemctl.s.lmemsz = CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE; 388 389 write_c0_cvmmemctl(cvmmemctl.u64); 390 391 if (smp_processor_id() == 0) 392 pr_notice("CVMSEG size: %d cache lines (%d bytes)\n", 393 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE, 394 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128); 395 396 /* Set a default for the hardware timeouts */ 397 fau_timeout.u64 = 0; 398 fau_timeout.s.tout_val = 0xfff; 399 /* Disable tagwait FAU timeout */ 400 fau_timeout.s.tout_enb = 0; 401 cvmx_write_csr(CVMX_IOB_FAU_TIMEOUT, fau_timeout.u64); 402 403 nm_tim.u64 = 0; 404 /* 4096 cycles */ 405 nm_tim.s.nw_tim = 3; 406 cvmx_write_csr(CVMX_POW_NW_TIM, nm_tim.u64); 407 408 write_octeon_c0_icacheerr(0); 409 write_c0_derraddr1(0); 410 } 411 412 /** 413 * Early entry point for arch setup 414 */ 415 void __init prom_init(void) 416 { 417 struct cvmx_sysinfo *sysinfo; 418 int i; 419 int argc; 420 #ifdef CONFIG_CAVIUM_RESERVE32 421 int64_t addr = -1; 422 #endif 423 /* 424 * The bootloader passes a pointer to the boot descriptor in 425 * $a3, this is available as fw_arg3. 426 */ 427 octeon_boot_desc_ptr = (struct octeon_boot_descriptor *)fw_arg3; 428 octeon_bootinfo = 429 cvmx_phys_to_ptr(octeon_boot_desc_ptr->cvmx_desc_vaddr); 430 cvmx_bootmem_init(cvmx_phys_to_ptr(octeon_bootinfo->phy_mem_desc_addr)); 431 432 sysinfo = cvmx_sysinfo_get(); 433 memset(sysinfo, 0, sizeof(*sysinfo)); 434 sysinfo->system_dram_size = octeon_bootinfo->dram_size << 20; 435 sysinfo->phy_mem_desc_ptr = 436 cvmx_phys_to_ptr(octeon_bootinfo->phy_mem_desc_addr); 437 sysinfo->core_mask = octeon_bootinfo->core_mask; 438 sysinfo->exception_base_addr = octeon_bootinfo->exception_base_addr; 439 sysinfo->cpu_clock_hz = octeon_bootinfo->eclock_hz; 440 sysinfo->dram_data_rate_hz = octeon_bootinfo->dclock_hz * 2; 441 sysinfo->board_type = octeon_bootinfo->board_type; 442 sysinfo->board_rev_major = octeon_bootinfo->board_rev_major; 443 sysinfo->board_rev_minor = octeon_bootinfo->board_rev_minor; 444 memcpy(sysinfo->mac_addr_base, octeon_bootinfo->mac_addr_base, 445 sizeof(sysinfo->mac_addr_base)); 446 sysinfo->mac_addr_count = octeon_bootinfo->mac_addr_count; 447 memcpy(sysinfo->board_serial_number, 448 octeon_bootinfo->board_serial_number, 449 sizeof(sysinfo->board_serial_number)); 450 sysinfo->compact_flash_common_base_addr = 451 octeon_bootinfo->compact_flash_common_base_addr; 452 sysinfo->compact_flash_attribute_base_addr = 453 octeon_bootinfo->compact_flash_attribute_base_addr; 454 sysinfo->led_display_base_addr = octeon_bootinfo->led_display_base_addr; 455 sysinfo->dfa_ref_clock_hz = octeon_bootinfo->dfa_ref_clock_hz; 456 sysinfo->bootloader_config_flags = octeon_bootinfo->config_flags; 457 458 if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) { 459 /* I/O clock runs at a different rate than the CPU. */ 460 union cvmx_mio_rst_boot rst_boot; 461 rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT); 462 octeon_io_clock_rate = 50000000 * rst_boot.s.pnr_mul; 463 } else { 464 octeon_io_clock_rate = sysinfo->cpu_clock_hz; 465 } 466 467 /* 468 * Only enable the LED controller if we're running on a CN38XX, CN58XX, 469 * or CN56XX. The CN30XX and CN31XX don't have an LED controller. 470 */ 471 if (!octeon_is_simulation() && 472 octeon_has_feature(OCTEON_FEATURE_LED_CONTROLLER)) { 473 cvmx_write_csr(CVMX_LED_EN, 0); 474 cvmx_write_csr(CVMX_LED_PRT, 0); 475 cvmx_write_csr(CVMX_LED_DBG, 0); 476 cvmx_write_csr(CVMX_LED_PRT_FMT, 0); 477 cvmx_write_csr(CVMX_LED_UDD_CNTX(0), 32); 478 cvmx_write_csr(CVMX_LED_UDD_CNTX(1), 32); 479 cvmx_write_csr(CVMX_LED_UDD_DATX(0), 0); 480 cvmx_write_csr(CVMX_LED_UDD_DATX(1), 0); 481 cvmx_write_csr(CVMX_LED_EN, 1); 482 } 483 #ifdef CONFIG_CAVIUM_RESERVE32 484 /* 485 * We need to temporarily allocate all memory in the reserve32 486 * region. This makes sure the kernel doesn't allocate this 487 * memory when it is getting memory from the 488 * bootloader. Later, after the memory allocations are 489 * complete, the reserve32 will be freed. 490 * 491 * Allocate memory for RESERVED32 aligned on 2MB boundary. This 492 * is in case we later use hugetlb entries with it. 493 */ 494 addr = cvmx_bootmem_phy_named_block_alloc(CONFIG_CAVIUM_RESERVE32 << 20, 495 0, 0, 2 << 20, 496 "CAVIUM_RESERVE32", 0); 497 if (addr < 0) 498 pr_err("Failed to allocate CAVIUM_RESERVE32 memory area\n"); 499 else 500 octeon_reserve32_memory = addr; 501 #endif 502 503 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2 504 if (cvmx_read_csr(CVMX_L2D_FUS3) & (3ull << 34)) { 505 pr_info("Skipping L2 locking due to reduced L2 cache size\n"); 506 } else { 507 uint32_t ebase = read_c0_ebase() & 0x3ffff000; 508 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_TLB 509 /* TLB refill */ 510 cvmx_l2c_lock_mem_region(ebase, 0x100); 511 #endif 512 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_EXCEPTION 513 /* General exception */ 514 cvmx_l2c_lock_mem_region(ebase + 0x180, 0x80); 515 #endif 516 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT 517 /* Interrupt handler */ 518 cvmx_l2c_lock_mem_region(ebase + 0x200, 0x80); 519 #endif 520 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_INTERRUPT 521 cvmx_l2c_lock_mem_region(__pa_symbol(handle_int), 0x100); 522 cvmx_l2c_lock_mem_region(__pa_symbol(plat_irq_dispatch), 0x80); 523 #endif 524 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_MEMCPY 525 cvmx_l2c_lock_mem_region(__pa_symbol(memcpy), 0x480); 526 #endif 527 } 528 #endif 529 530 octeon_check_cpu_bist(); 531 532 octeon_uart = octeon_get_boot_uart(); 533 534 #ifdef CONFIG_SMP 535 octeon_write_lcd("LinuxSMP"); 536 #else 537 octeon_write_lcd("Linux"); 538 #endif 539 540 #ifdef CONFIG_CAVIUM_GDB 541 /* 542 * When debugging the linux kernel, force the cores to enter 543 * the debug exception handler to break in. 544 */ 545 if (octeon_get_boot_debug_flag()) { 546 cvmx_write_csr(CVMX_CIU_DINT, 1 << cvmx_get_core_num()); 547 cvmx_read_csr(CVMX_CIU_DINT); 548 } 549 #endif 550 551 /* 552 * BIST should always be enabled when doing a soft reset. L2 553 * Cache locking for instance is not cleared unless BIST is 554 * enabled. Unfortunately due to a chip errata G-200 for 555 * Cn38XX and CN31XX, BIST msut be disabled on these parts. 556 */ 557 if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2) || 558 OCTEON_IS_MODEL(OCTEON_CN31XX)) 559 cvmx_write_csr(CVMX_CIU_SOFT_BIST, 0); 560 else 561 cvmx_write_csr(CVMX_CIU_SOFT_BIST, 1); 562 563 /* Default to 64MB in the simulator to speed things up */ 564 if (octeon_is_simulation()) 565 MAX_MEMORY = 64ull << 20; 566 567 arcs_cmdline[0] = 0; 568 argc = octeon_boot_desc_ptr->argc; 569 for (i = 0; i < argc; i++) { 570 const char *arg = 571 cvmx_phys_to_ptr(octeon_boot_desc_ptr->argv[i]); 572 if ((strncmp(arg, "MEM=", 4) == 0) || 573 (strncmp(arg, "mem=", 4) == 0)) { 574 sscanf(arg + 4, "%llu", &MAX_MEMORY); 575 MAX_MEMORY <<= 20; 576 if (MAX_MEMORY == 0) 577 MAX_MEMORY = 32ull << 30; 578 } else if (strcmp(arg, "ecc_verbose") == 0) { 579 #ifdef CONFIG_CAVIUM_REPORT_SINGLE_BIT_ECC 580 __cvmx_interrupt_ecc_report_single_bit_errors = 1; 581 pr_notice("Reporting of single bit ECC errors is " 582 "turned on\n"); 583 #endif 584 } else if (strlen(arcs_cmdline) + strlen(arg) + 1 < 585 sizeof(arcs_cmdline) - 1) { 586 strcat(arcs_cmdline, " "); 587 strcat(arcs_cmdline, arg); 588 } 589 } 590 591 if (strstr(arcs_cmdline, "console=") == NULL) { 592 #ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL 593 strcat(arcs_cmdline, " console=ttyS0,115200"); 594 #else 595 if (octeon_uart == 1) 596 strcat(arcs_cmdline, " console=ttyS1,115200"); 597 else 598 strcat(arcs_cmdline, " console=ttyS0,115200"); 599 #endif 600 } 601 602 if (octeon_is_simulation()) { 603 /* 604 * The simulator uses a mtdram device pre filled with 605 * the filesystem. Also specify the calibration delay 606 * to avoid calculating it every time. 607 */ 608 strcat(arcs_cmdline, " rw root=1f00 slram=root,0x40000000,+1073741824"); 609 } 610 611 mips_hpt_frequency = octeon_get_clock_rate(); 612 613 octeon_init_cvmcount(); 614 octeon_setup_delays(); 615 616 _machine_restart = octeon_restart; 617 _machine_halt = octeon_halt; 618 619 octeon_user_io_init(); 620 register_smp_ops(&octeon_smp_ops); 621 } 622 623 /* Exclude a single page from the regions obtained in plat_mem_setup. */ 624 static __init void memory_exclude_page(u64 addr, u64 *mem, u64 *size) 625 { 626 if (addr > *mem && addr < *mem + *size) { 627 u64 inc = addr - *mem; 628 add_memory_region(*mem, inc, BOOT_MEM_RAM); 629 *mem += inc; 630 *size -= inc; 631 } 632 633 if (addr == *mem && *size > PAGE_SIZE) { 634 *mem += PAGE_SIZE; 635 *size -= PAGE_SIZE; 636 } 637 } 638 639 void __init plat_mem_setup(void) 640 { 641 uint64_t mem_alloc_size; 642 uint64_t total; 643 int64_t memory; 644 645 total = 0; 646 647 /* 648 * The Mips memory init uses the first memory location for 649 * some memory vectors. When SPARSEMEM is in use, it doesn't 650 * verify that the size is big enough for the final 651 * vectors. Making the smallest chuck 4MB seems to be enough 652 * to consistently work. 653 */ 654 mem_alloc_size = 4 << 20; 655 if (mem_alloc_size > MAX_MEMORY) 656 mem_alloc_size = MAX_MEMORY; 657 658 /* 659 * When allocating memory, we want incrementing addresses from 660 * bootmem_alloc so the code in add_memory_region can merge 661 * regions next to each other. 662 */ 663 cvmx_bootmem_lock(); 664 while ((boot_mem_map.nr_map < BOOT_MEM_MAP_MAX) 665 && (total < MAX_MEMORY)) { 666 #if defined(CONFIG_64BIT) || defined(CONFIG_64BIT_PHYS_ADDR) 667 memory = cvmx_bootmem_phy_alloc(mem_alloc_size, 668 __pa_symbol(&__init_end), -1, 669 0x100000, 670 CVMX_BOOTMEM_FLAG_NO_LOCKING); 671 #elif defined(CONFIG_HIGHMEM) 672 memory = cvmx_bootmem_phy_alloc(mem_alloc_size, 0, 1ull << 31, 673 0x100000, 674 CVMX_BOOTMEM_FLAG_NO_LOCKING); 675 #else 676 memory = cvmx_bootmem_phy_alloc(mem_alloc_size, 0, 512 << 20, 677 0x100000, 678 CVMX_BOOTMEM_FLAG_NO_LOCKING); 679 #endif 680 if (memory >= 0) { 681 u64 size = mem_alloc_size; 682 683 /* 684 * exclude a page at the beginning and end of 685 * the 256MB PCIe 'hole' so the kernel will not 686 * try to allocate multi-page buffers that 687 * span the discontinuity. 688 */ 689 memory_exclude_page(CVMX_PCIE_BAR1_PHYS_BASE, 690 &memory, &size); 691 memory_exclude_page(CVMX_PCIE_BAR1_PHYS_BASE + 692 CVMX_PCIE_BAR1_PHYS_SIZE, 693 &memory, &size); 694 695 /* 696 * This function automatically merges address 697 * regions next to each other if they are 698 * received in incrementing order. 699 */ 700 if (size) 701 add_memory_region(memory, size, BOOT_MEM_RAM); 702 total += mem_alloc_size; 703 } else { 704 break; 705 } 706 } 707 cvmx_bootmem_unlock(); 708 709 #ifdef CONFIG_CAVIUM_RESERVE32 710 /* 711 * Now that we've allocated the kernel memory it is safe to 712 * free the reserved region. We free it here so that builtin 713 * drivers can use the memory. 714 */ 715 if (octeon_reserve32_memory) 716 cvmx_bootmem_free_named("CAVIUM_RESERVE32"); 717 #endif /* CONFIG_CAVIUM_RESERVE32 */ 718 719 if (total == 0) 720 panic("Unable to allocate memory from " 721 "cvmx_bootmem_phy_alloc\n"); 722 } 723 724 /* 725 * Emit one character to the boot UART. Exported for use by the 726 * watchdog timer. 727 */ 728 int prom_putchar(char c) 729 { 730 uint64_t lsrval; 731 732 /* Spin until there is room */ 733 do { 734 lsrval = cvmx_read_csr(CVMX_MIO_UARTX_LSR(octeon_uart)); 735 } while ((lsrval & 0x20) == 0); 736 737 /* Write the byte */ 738 cvmx_write_csr(CVMX_MIO_UARTX_THR(octeon_uart), c & 0xffull); 739 return 1; 740 } 741 EXPORT_SYMBOL(prom_putchar); 742 743 void prom_free_prom_memory(void) 744 { 745 if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X)) { 746 /* Check for presence of Core-14449 fix. */ 747 u32 insn; 748 u32 *foo; 749 750 foo = &insn; 751 752 asm volatile("# before" : : : "memory"); 753 prefetch(foo); 754 asm volatile( 755 ".set push\n\t" 756 ".set noreorder\n\t" 757 "bal 1f\n\t" 758 "nop\n" 759 "1:\tlw %0,-12($31)\n\t" 760 ".set pop\n\t" 761 : "=r" (insn) : : "$31", "memory"); 762 763 if ((insn >> 26) != 0x33) 764 panic("No PREF instruction at Core-14449 probe point."); 765 766 if (((insn >> 16) & 0x1f) != 28) 767 panic("Core-14449 WAR not in place (%04x).\n" 768 "Please build kernel with proper options (CONFIG_CAVIUM_CN63XXP1).", insn); 769 } 770 #ifdef CONFIG_CAVIUM_DECODE_RSL 771 cvmx_interrupt_rsl_enable(); 772 773 /* Add an interrupt handler for general failures. */ 774 if (request_irq(OCTEON_IRQ_RML, octeon_rlm_interrupt, IRQF_SHARED, 775 "RML/RSL", octeon_rlm_interrupt)) { 776 panic("Unable to request_irq(OCTEON_IRQ_RML)"); 777 } 778 #endif 779 } 780 781 int octeon_prune_device_tree(void); 782 783 extern const char __dtb_octeon_3xxx_begin; 784 extern const char __dtb_octeon_3xxx_end; 785 extern const char __dtb_octeon_68xx_begin; 786 extern const char __dtb_octeon_68xx_end; 787 void __init device_tree_init(void) 788 { 789 int dt_size; 790 struct boot_param_header *fdt; 791 bool do_prune; 792 793 if (octeon_bootinfo->minor_version >= 3 && octeon_bootinfo->fdt_addr) { 794 fdt = phys_to_virt(octeon_bootinfo->fdt_addr); 795 if (fdt_check_header(fdt)) 796 panic("Corrupt Device Tree passed to kernel."); 797 dt_size = be32_to_cpu(fdt->totalsize); 798 do_prune = false; 799 } else if (OCTEON_IS_MODEL(OCTEON_CN68XX)) { 800 fdt = (struct boot_param_header *)&__dtb_octeon_68xx_begin; 801 dt_size = &__dtb_octeon_68xx_end - &__dtb_octeon_68xx_begin; 802 do_prune = true; 803 } else { 804 fdt = (struct boot_param_header *)&__dtb_octeon_3xxx_begin; 805 dt_size = &__dtb_octeon_3xxx_end - &__dtb_octeon_3xxx_begin; 806 do_prune = true; 807 } 808 809 /* Copy the default tree from init memory. */ 810 initial_boot_params = early_init_dt_alloc_memory_arch(dt_size, 8); 811 if (initial_boot_params == NULL) 812 panic("Could not allocate initial_boot_params\n"); 813 memcpy(initial_boot_params, fdt, dt_size); 814 815 if (do_prune) { 816 octeon_prune_device_tree(); 817 pr_info("Using internal Device Tree.\n"); 818 } else { 819 pr_info("Using passed Device Tree.\n"); 820 } 821 unflatten_device_tree(); 822 } 823