1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2004-2007 Cavium Networks 7 * Copyright (C) 2008 Wind River Systems 8 */ 9 #include <linux/init.h> 10 #include <linux/console.h> 11 #include <linux/delay.h> 12 #include <linux/interrupt.h> 13 #include <linux/io.h> 14 #include <linux/serial.h> 15 #include <linux/smp.h> 16 #include <linux/types.h> 17 #include <linux/string.h> /* for memset */ 18 #include <linux/tty.h> 19 #include <linux/time.h> 20 #include <linux/platform_device.h> 21 #include <linux/serial_core.h> 22 #include <linux/serial_8250.h> 23 24 #include <asm/processor.h> 25 #include <asm/reboot.h> 26 #include <asm/smp-ops.h> 27 #include <asm/irq_cpu.h> 28 #include <asm/mipsregs.h> 29 #include <asm/bootinfo.h> 30 #include <asm/sections.h> 31 #include <asm/time.h> 32 33 #include <asm/octeon/octeon.h> 34 #include <asm/octeon/pci-octeon.h> 35 #include <asm/octeon/cvmx-mio-defs.h> 36 37 #ifdef CONFIG_CAVIUM_DECODE_RSL 38 extern void cvmx_interrupt_rsl_decode(void); 39 extern int __cvmx_interrupt_ecc_report_single_bit_errors; 40 extern void cvmx_interrupt_rsl_enable(void); 41 #endif 42 43 extern struct plat_smp_ops octeon_smp_ops; 44 45 #ifdef CONFIG_PCI 46 extern void pci_console_init(const char *arg); 47 #endif 48 49 static unsigned long long MAX_MEMORY = 512ull << 20; 50 51 struct octeon_boot_descriptor *octeon_boot_desc_ptr; 52 53 struct cvmx_bootinfo *octeon_bootinfo; 54 EXPORT_SYMBOL(octeon_bootinfo); 55 56 #ifdef CONFIG_CAVIUM_RESERVE32 57 uint64_t octeon_reserve32_memory; 58 EXPORT_SYMBOL(octeon_reserve32_memory); 59 #endif 60 61 static int octeon_uart; 62 63 extern asmlinkage void handle_int(void); 64 extern asmlinkage void plat_irq_dispatch(void); 65 66 /** 67 * Return non zero if we are currently running in the Octeon simulator 68 * 69 * Returns 70 */ 71 int octeon_is_simulation(void) 72 { 73 return octeon_bootinfo->board_type == CVMX_BOARD_TYPE_SIM; 74 } 75 EXPORT_SYMBOL(octeon_is_simulation); 76 77 /** 78 * Return true if Octeon is in PCI Host mode. This means 79 * Linux can control the PCI bus. 80 * 81 * Returns Non zero if Octeon in host mode. 82 */ 83 int octeon_is_pci_host(void) 84 { 85 #ifdef CONFIG_PCI 86 return octeon_bootinfo->config_flags & CVMX_BOOTINFO_CFG_FLAG_PCI_HOST; 87 #else 88 return 0; 89 #endif 90 } 91 92 /** 93 * Get the clock rate of Octeon 94 * 95 * Returns Clock rate in HZ 96 */ 97 uint64_t octeon_get_clock_rate(void) 98 { 99 struct cvmx_sysinfo *sysinfo = cvmx_sysinfo_get(); 100 101 return sysinfo->cpu_clock_hz; 102 } 103 EXPORT_SYMBOL(octeon_get_clock_rate); 104 105 static u64 octeon_io_clock_rate; 106 107 u64 octeon_get_io_clock_rate(void) 108 { 109 return octeon_io_clock_rate; 110 } 111 EXPORT_SYMBOL(octeon_get_io_clock_rate); 112 113 114 /** 115 * Write to the LCD display connected to the bootbus. This display 116 * exists on most Cavium evaluation boards. If it doesn't exist, then 117 * this function doesn't do anything. 118 * 119 * @s: String to write 120 */ 121 void octeon_write_lcd(const char *s) 122 { 123 if (octeon_bootinfo->led_display_base_addr) { 124 void __iomem *lcd_address = 125 ioremap_nocache(octeon_bootinfo->led_display_base_addr, 126 8); 127 int i; 128 for (i = 0; i < 8; i++, s++) { 129 if (*s) 130 iowrite8(*s, lcd_address + i); 131 else 132 iowrite8(' ', lcd_address + i); 133 } 134 iounmap(lcd_address); 135 } 136 } 137 138 /** 139 * Return the console uart passed by the bootloader 140 * 141 * Returns uart (0 or 1) 142 */ 143 int octeon_get_boot_uart(void) 144 { 145 int uart; 146 #ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL 147 uart = 1; 148 #else 149 uart = (octeon_boot_desc_ptr->flags & OCTEON_BL_FLAG_CONSOLE_UART1) ? 150 1 : 0; 151 #endif 152 return uart; 153 } 154 155 /** 156 * Get the coremask Linux was booted on. 157 * 158 * Returns Core mask 159 */ 160 int octeon_get_boot_coremask(void) 161 { 162 return octeon_boot_desc_ptr->core_mask; 163 } 164 165 /** 166 * Check the hardware BIST results for a CPU 167 */ 168 void octeon_check_cpu_bist(void) 169 { 170 const int coreid = cvmx_get_core_num(); 171 unsigned long long mask; 172 unsigned long long bist_val; 173 174 /* Check BIST results for COP0 registers */ 175 mask = 0x1f00000000ull; 176 bist_val = read_octeon_c0_icacheerr(); 177 if (bist_val & mask) 178 pr_err("Core%d BIST Failure: CacheErr(icache) = 0x%llx\n", 179 coreid, bist_val); 180 181 bist_val = read_octeon_c0_dcacheerr(); 182 if (bist_val & 1) 183 pr_err("Core%d L1 Dcache parity error: " 184 "CacheErr(dcache) = 0x%llx\n", 185 coreid, bist_val); 186 187 mask = 0xfc00000000000000ull; 188 bist_val = read_c0_cvmmemctl(); 189 if (bist_val & mask) 190 pr_err("Core%d BIST Failure: COP0_CVM_MEM_CTL = 0x%llx\n", 191 coreid, bist_val); 192 193 write_octeon_c0_dcacheerr(0); 194 } 195 196 /** 197 * Reboot Octeon 198 * 199 * @command: Command to pass to the bootloader. Currently ignored. 200 */ 201 static void octeon_restart(char *command) 202 { 203 /* Disable all watchdogs before soft reset. They don't get cleared */ 204 #ifdef CONFIG_SMP 205 int cpu; 206 for_each_online_cpu(cpu) 207 cvmx_write_csr(CVMX_CIU_WDOGX(cpu_logical_map(cpu)), 0); 208 #else 209 cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0); 210 #endif 211 212 mb(); 213 while (1) 214 cvmx_write_csr(CVMX_CIU_SOFT_RST, 1); 215 } 216 217 218 /** 219 * Permanently stop a core. 220 * 221 * @arg: Ignored. 222 */ 223 static void octeon_kill_core(void *arg) 224 { 225 mb(); 226 if (octeon_is_simulation()) { 227 /* The simulator needs the watchdog to stop for dead cores */ 228 cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0); 229 /* A break instruction causes the simulator stop a core */ 230 asm volatile ("sync\nbreak"); 231 } 232 } 233 234 235 /** 236 * Halt the system 237 */ 238 static void octeon_halt(void) 239 { 240 smp_call_function(octeon_kill_core, NULL, 0); 241 242 switch (octeon_bootinfo->board_type) { 243 case CVMX_BOARD_TYPE_NAO38: 244 /* Driving a 1 to GPIO 12 shuts off this board */ 245 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(12), 1); 246 cvmx_write_csr(CVMX_GPIO_TX_SET, 0x1000); 247 break; 248 default: 249 octeon_write_lcd("PowerOff"); 250 break; 251 } 252 253 octeon_kill_core(NULL); 254 } 255 256 /** 257 * Handle all the error condition interrupts that might occur. 258 * 259 */ 260 #ifdef CONFIG_CAVIUM_DECODE_RSL 261 static irqreturn_t octeon_rlm_interrupt(int cpl, void *dev_id) 262 { 263 cvmx_interrupt_rsl_decode(); 264 return IRQ_HANDLED; 265 } 266 #endif 267 268 /** 269 * Return a string representing the system type 270 * 271 * Returns 272 */ 273 const char *octeon_board_type_string(void) 274 { 275 static char name[80]; 276 sprintf(name, "%s (%s)", 277 cvmx_board_type_to_string(octeon_bootinfo->board_type), 278 octeon_model_get_string(read_c0_prid())); 279 return name; 280 } 281 282 const char *get_system_type(void) 283 __attribute__ ((alias("octeon_board_type_string"))); 284 285 void octeon_user_io_init(void) 286 { 287 union octeon_cvmemctl cvmmemctl; 288 union cvmx_iob_fau_timeout fau_timeout; 289 union cvmx_pow_nw_tim nm_tim; 290 291 /* Get the current settings for CP0_CVMMEMCTL_REG */ 292 cvmmemctl.u64 = read_c0_cvmmemctl(); 293 /* R/W If set, marked write-buffer entries time out the same 294 * as as other entries; if clear, marked write-buffer entries 295 * use the maximum timeout. */ 296 cvmmemctl.s.dismarkwblongto = 1; 297 /* R/W If set, a merged store does not clear the write-buffer 298 * entry timeout state. */ 299 cvmmemctl.s.dismrgclrwbto = 0; 300 /* R/W Two bits that are the MSBs of the resultant CVMSEG LM 301 * word location for an IOBDMA. The other 8 bits come from the 302 * SCRADDR field of the IOBDMA. */ 303 cvmmemctl.s.iobdmascrmsb = 0; 304 /* R/W If set, SYNCWS and SYNCS only order marked stores; if 305 * clear, SYNCWS and SYNCS only order unmarked 306 * stores. SYNCWSMARKED has no effect when DISSYNCWS is 307 * set. */ 308 cvmmemctl.s.syncwsmarked = 0; 309 /* R/W If set, SYNCWS acts as SYNCW and SYNCS acts as SYNC. */ 310 cvmmemctl.s.dissyncws = 0; 311 /* R/W If set, no stall happens on write buffer full. */ 312 if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2)) 313 cvmmemctl.s.diswbfst = 1; 314 else 315 cvmmemctl.s.diswbfst = 0; 316 /* R/W If set (and SX set), supervisor-level loads/stores can 317 * use XKPHYS addresses with <48>==0 */ 318 cvmmemctl.s.xkmemenas = 0; 319 320 /* R/W If set (and UX set), user-level loads/stores can use 321 * XKPHYS addresses with VA<48>==0 */ 322 cvmmemctl.s.xkmemenau = 0; 323 324 /* R/W If set (and SX set), supervisor-level loads/stores can 325 * use XKPHYS addresses with VA<48>==1 */ 326 cvmmemctl.s.xkioenas = 0; 327 328 /* R/W If set (and UX set), user-level loads/stores can use 329 * XKPHYS addresses with VA<48>==1 */ 330 cvmmemctl.s.xkioenau = 0; 331 332 /* R/W If set, all stores act as SYNCW (NOMERGE must be set 333 * when this is set) RW, reset to 0. */ 334 cvmmemctl.s.allsyncw = 0; 335 336 /* R/W If set, no stores merge, and all stores reach the 337 * coherent bus in order. */ 338 cvmmemctl.s.nomerge = 0; 339 /* R/W Selects the bit in the counter used for DID time-outs 0 340 * = 231, 1 = 230, 2 = 229, 3 = 214. Actual time-out is 341 * between 1x and 2x this interval. For example, with 342 * DIDTTO=3, expiration interval is between 16K and 32K. */ 343 cvmmemctl.s.didtto = 0; 344 /* R/W If set, the (mem) CSR clock never turns off. */ 345 cvmmemctl.s.csrckalwys = 0; 346 /* R/W If set, mclk never turns off. */ 347 cvmmemctl.s.mclkalwys = 0; 348 /* R/W Selects the bit in the counter used for write buffer 349 * flush time-outs (WBFLT+11) is the bit position in an 350 * internal counter used to determine expiration. The write 351 * buffer expires between 1x and 2x this interval. For 352 * example, with WBFLT = 0, a write buffer expires between 2K 353 * and 4K cycles after the write buffer entry is allocated. */ 354 cvmmemctl.s.wbfltime = 0; 355 /* R/W If set, do not put Istream in the L2 cache. */ 356 cvmmemctl.s.istrnol2 = 0; 357 358 /* 359 * R/W The write buffer threshold. As per erratum Core-14752 360 * for CN63XX, a sc/scd might fail if the write buffer is 361 * full. Lowering WBTHRESH greatly lowers the chances of the 362 * write buffer ever being full and triggering the erratum. 363 */ 364 if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X)) 365 cvmmemctl.s.wbthresh = 4; 366 else 367 cvmmemctl.s.wbthresh = 10; 368 369 /* R/W If set, CVMSEG is available for loads/stores in 370 * kernel/debug mode. */ 371 #if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0 372 cvmmemctl.s.cvmsegenak = 1; 373 #else 374 cvmmemctl.s.cvmsegenak = 0; 375 #endif 376 /* R/W If set, CVMSEG is available for loads/stores in 377 * supervisor mode. */ 378 cvmmemctl.s.cvmsegenas = 0; 379 /* R/W If set, CVMSEG is available for loads/stores in user 380 * mode. */ 381 cvmmemctl.s.cvmsegenau = 0; 382 /* R/W Size of local memory in cache blocks, 54 (6912 bytes) 383 * is max legal value. */ 384 cvmmemctl.s.lmemsz = CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE; 385 386 write_c0_cvmmemctl(cvmmemctl.u64); 387 388 if (smp_processor_id() == 0) 389 pr_notice("CVMSEG size: %d cache lines (%d bytes)\n", 390 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE, 391 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128); 392 393 /* Set a default for the hardware timeouts */ 394 fau_timeout.u64 = 0; 395 fau_timeout.s.tout_val = 0xfff; 396 /* Disable tagwait FAU timeout */ 397 fau_timeout.s.tout_enb = 0; 398 cvmx_write_csr(CVMX_IOB_FAU_TIMEOUT, fau_timeout.u64); 399 400 nm_tim.u64 = 0; 401 /* 4096 cycles */ 402 nm_tim.s.nw_tim = 3; 403 cvmx_write_csr(CVMX_POW_NW_TIM, nm_tim.u64); 404 405 write_octeon_c0_icacheerr(0); 406 write_c0_derraddr1(0); 407 } 408 409 /** 410 * Early entry point for arch setup 411 */ 412 void __init prom_init(void) 413 { 414 struct cvmx_sysinfo *sysinfo; 415 int i; 416 int argc; 417 #ifdef CONFIG_CAVIUM_RESERVE32 418 int64_t addr = -1; 419 #endif 420 /* 421 * The bootloader passes a pointer to the boot descriptor in 422 * $a3, this is available as fw_arg3. 423 */ 424 octeon_boot_desc_ptr = (struct octeon_boot_descriptor *)fw_arg3; 425 octeon_bootinfo = 426 cvmx_phys_to_ptr(octeon_boot_desc_ptr->cvmx_desc_vaddr); 427 cvmx_bootmem_init(cvmx_phys_to_ptr(octeon_bootinfo->phy_mem_desc_addr)); 428 429 sysinfo = cvmx_sysinfo_get(); 430 memset(sysinfo, 0, sizeof(*sysinfo)); 431 sysinfo->system_dram_size = octeon_bootinfo->dram_size << 20; 432 sysinfo->phy_mem_desc_ptr = 433 cvmx_phys_to_ptr(octeon_bootinfo->phy_mem_desc_addr); 434 sysinfo->core_mask = octeon_bootinfo->core_mask; 435 sysinfo->exception_base_addr = octeon_bootinfo->exception_base_addr; 436 sysinfo->cpu_clock_hz = octeon_bootinfo->eclock_hz; 437 sysinfo->dram_data_rate_hz = octeon_bootinfo->dclock_hz * 2; 438 sysinfo->board_type = octeon_bootinfo->board_type; 439 sysinfo->board_rev_major = octeon_bootinfo->board_rev_major; 440 sysinfo->board_rev_minor = octeon_bootinfo->board_rev_minor; 441 memcpy(sysinfo->mac_addr_base, octeon_bootinfo->mac_addr_base, 442 sizeof(sysinfo->mac_addr_base)); 443 sysinfo->mac_addr_count = octeon_bootinfo->mac_addr_count; 444 memcpy(sysinfo->board_serial_number, 445 octeon_bootinfo->board_serial_number, 446 sizeof(sysinfo->board_serial_number)); 447 sysinfo->compact_flash_common_base_addr = 448 octeon_bootinfo->compact_flash_common_base_addr; 449 sysinfo->compact_flash_attribute_base_addr = 450 octeon_bootinfo->compact_flash_attribute_base_addr; 451 sysinfo->led_display_base_addr = octeon_bootinfo->led_display_base_addr; 452 sysinfo->dfa_ref_clock_hz = octeon_bootinfo->dfa_ref_clock_hz; 453 sysinfo->bootloader_config_flags = octeon_bootinfo->config_flags; 454 455 if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) { 456 /* I/O clock runs at a different rate than the CPU. */ 457 union cvmx_mio_rst_boot rst_boot; 458 rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT); 459 octeon_io_clock_rate = 50000000 * rst_boot.s.pnr_mul; 460 } else { 461 octeon_io_clock_rate = sysinfo->cpu_clock_hz; 462 } 463 464 /* 465 * Only enable the LED controller if we're running on a CN38XX, CN58XX, 466 * or CN56XX. The CN30XX and CN31XX don't have an LED controller. 467 */ 468 if (!octeon_is_simulation() && 469 octeon_has_feature(OCTEON_FEATURE_LED_CONTROLLER)) { 470 cvmx_write_csr(CVMX_LED_EN, 0); 471 cvmx_write_csr(CVMX_LED_PRT, 0); 472 cvmx_write_csr(CVMX_LED_DBG, 0); 473 cvmx_write_csr(CVMX_LED_PRT_FMT, 0); 474 cvmx_write_csr(CVMX_LED_UDD_CNTX(0), 32); 475 cvmx_write_csr(CVMX_LED_UDD_CNTX(1), 32); 476 cvmx_write_csr(CVMX_LED_UDD_DATX(0), 0); 477 cvmx_write_csr(CVMX_LED_UDD_DATX(1), 0); 478 cvmx_write_csr(CVMX_LED_EN, 1); 479 } 480 #ifdef CONFIG_CAVIUM_RESERVE32 481 /* 482 * We need to temporarily allocate all memory in the reserve32 483 * region. This makes sure the kernel doesn't allocate this 484 * memory when it is getting memory from the 485 * bootloader. Later, after the memory allocations are 486 * complete, the reserve32 will be freed. 487 * 488 * Allocate memory for RESERVED32 aligned on 2MB boundary. This 489 * is in case we later use hugetlb entries with it. 490 */ 491 addr = cvmx_bootmem_phy_named_block_alloc(CONFIG_CAVIUM_RESERVE32 << 20, 492 0, 0, 2 << 20, 493 "CAVIUM_RESERVE32", 0); 494 if (addr < 0) 495 pr_err("Failed to allocate CAVIUM_RESERVE32 memory area\n"); 496 else 497 octeon_reserve32_memory = addr; 498 #endif 499 500 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2 501 if (cvmx_read_csr(CVMX_L2D_FUS3) & (3ull << 34)) { 502 pr_info("Skipping L2 locking due to reduced L2 cache size\n"); 503 } else { 504 uint32_t ebase = read_c0_ebase() & 0x3ffff000; 505 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_TLB 506 /* TLB refill */ 507 cvmx_l2c_lock_mem_region(ebase, 0x100); 508 #endif 509 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_EXCEPTION 510 /* General exception */ 511 cvmx_l2c_lock_mem_region(ebase + 0x180, 0x80); 512 #endif 513 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT 514 /* Interrupt handler */ 515 cvmx_l2c_lock_mem_region(ebase + 0x200, 0x80); 516 #endif 517 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_INTERRUPT 518 cvmx_l2c_lock_mem_region(__pa_symbol(handle_int), 0x100); 519 cvmx_l2c_lock_mem_region(__pa_symbol(plat_irq_dispatch), 0x80); 520 #endif 521 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_MEMCPY 522 cvmx_l2c_lock_mem_region(__pa_symbol(memcpy), 0x480); 523 #endif 524 } 525 #endif 526 527 octeon_check_cpu_bist(); 528 529 octeon_uart = octeon_get_boot_uart(); 530 531 #ifdef CONFIG_SMP 532 octeon_write_lcd("LinuxSMP"); 533 #else 534 octeon_write_lcd("Linux"); 535 #endif 536 537 #ifdef CONFIG_CAVIUM_GDB 538 /* 539 * When debugging the linux kernel, force the cores to enter 540 * the debug exception handler to break in. 541 */ 542 if (octeon_get_boot_debug_flag()) { 543 cvmx_write_csr(CVMX_CIU_DINT, 1 << cvmx_get_core_num()); 544 cvmx_read_csr(CVMX_CIU_DINT); 545 } 546 #endif 547 548 /* 549 * BIST should always be enabled when doing a soft reset. L2 550 * Cache locking for instance is not cleared unless BIST is 551 * enabled. Unfortunately due to a chip errata G-200 for 552 * Cn38XX and CN31XX, BIST msut be disabled on these parts. 553 */ 554 if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2) || 555 OCTEON_IS_MODEL(OCTEON_CN31XX)) 556 cvmx_write_csr(CVMX_CIU_SOFT_BIST, 0); 557 else 558 cvmx_write_csr(CVMX_CIU_SOFT_BIST, 1); 559 560 /* Default to 64MB in the simulator to speed things up */ 561 if (octeon_is_simulation()) 562 MAX_MEMORY = 64ull << 20; 563 564 arcs_cmdline[0] = 0; 565 argc = octeon_boot_desc_ptr->argc; 566 for (i = 0; i < argc; i++) { 567 const char *arg = 568 cvmx_phys_to_ptr(octeon_boot_desc_ptr->argv[i]); 569 if ((strncmp(arg, "MEM=", 4) == 0) || 570 (strncmp(arg, "mem=", 4) == 0)) { 571 sscanf(arg + 4, "%llu", &MAX_MEMORY); 572 MAX_MEMORY <<= 20; 573 if (MAX_MEMORY == 0) 574 MAX_MEMORY = 32ull << 30; 575 } else if (strcmp(arg, "ecc_verbose") == 0) { 576 #ifdef CONFIG_CAVIUM_REPORT_SINGLE_BIT_ECC 577 __cvmx_interrupt_ecc_report_single_bit_errors = 1; 578 pr_notice("Reporting of single bit ECC errors is " 579 "turned on\n"); 580 #endif 581 } else if (strlen(arcs_cmdline) + strlen(arg) + 1 < 582 sizeof(arcs_cmdline) - 1) { 583 strcat(arcs_cmdline, " "); 584 strcat(arcs_cmdline, arg); 585 } 586 } 587 588 if (strstr(arcs_cmdline, "console=") == NULL) { 589 #ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL 590 strcat(arcs_cmdline, " console=ttyS0,115200"); 591 #else 592 if (octeon_uart == 1) 593 strcat(arcs_cmdline, " console=ttyS1,115200"); 594 else 595 strcat(arcs_cmdline, " console=ttyS0,115200"); 596 #endif 597 } 598 599 if (octeon_is_simulation()) { 600 /* 601 * The simulator uses a mtdram device pre filled with 602 * the filesystem. Also specify the calibration delay 603 * to avoid calculating it every time. 604 */ 605 strcat(arcs_cmdline, " rw root=1f00 slram=root,0x40000000,+1073741824"); 606 } 607 608 mips_hpt_frequency = octeon_get_clock_rate(); 609 610 octeon_init_cvmcount(); 611 octeon_setup_delays(); 612 613 _machine_restart = octeon_restart; 614 _machine_halt = octeon_halt; 615 616 octeon_user_io_init(); 617 register_smp_ops(&octeon_smp_ops); 618 } 619 620 /* Exclude a single page from the regions obtained in plat_mem_setup. */ 621 static __init void memory_exclude_page(u64 addr, u64 *mem, u64 *size) 622 { 623 if (addr > *mem && addr < *mem + *size) { 624 u64 inc = addr - *mem; 625 add_memory_region(*mem, inc, BOOT_MEM_RAM); 626 *mem += inc; 627 *size -= inc; 628 } 629 630 if (addr == *mem && *size > PAGE_SIZE) { 631 *mem += PAGE_SIZE; 632 *size -= PAGE_SIZE; 633 } 634 } 635 636 void __init plat_mem_setup(void) 637 { 638 uint64_t mem_alloc_size; 639 uint64_t total; 640 int64_t memory; 641 642 total = 0; 643 644 /* 645 * The Mips memory init uses the first memory location for 646 * some memory vectors. When SPARSEMEM is in use, it doesn't 647 * verify that the size is big enough for the final 648 * vectors. Making the smallest chuck 4MB seems to be enough 649 * to consistently work. 650 */ 651 mem_alloc_size = 4 << 20; 652 if (mem_alloc_size > MAX_MEMORY) 653 mem_alloc_size = MAX_MEMORY; 654 655 /* 656 * When allocating memory, we want incrementing addresses from 657 * bootmem_alloc so the code in add_memory_region can merge 658 * regions next to each other. 659 */ 660 cvmx_bootmem_lock(); 661 while ((boot_mem_map.nr_map < BOOT_MEM_MAP_MAX) 662 && (total < MAX_MEMORY)) { 663 #if defined(CONFIG_64BIT) || defined(CONFIG_64BIT_PHYS_ADDR) 664 memory = cvmx_bootmem_phy_alloc(mem_alloc_size, 665 __pa_symbol(&__init_end), -1, 666 0x100000, 667 CVMX_BOOTMEM_FLAG_NO_LOCKING); 668 #elif defined(CONFIG_HIGHMEM) 669 memory = cvmx_bootmem_phy_alloc(mem_alloc_size, 0, 1ull << 31, 670 0x100000, 671 CVMX_BOOTMEM_FLAG_NO_LOCKING); 672 #else 673 memory = cvmx_bootmem_phy_alloc(mem_alloc_size, 0, 512 << 20, 674 0x100000, 675 CVMX_BOOTMEM_FLAG_NO_LOCKING); 676 #endif 677 if (memory >= 0) { 678 u64 size = mem_alloc_size; 679 680 /* 681 * exclude a page at the beginning and end of 682 * the 256MB PCIe 'hole' so the kernel will not 683 * try to allocate multi-page buffers that 684 * span the discontinuity. 685 */ 686 memory_exclude_page(CVMX_PCIE_BAR1_PHYS_BASE, 687 &memory, &size); 688 memory_exclude_page(CVMX_PCIE_BAR1_PHYS_BASE + 689 CVMX_PCIE_BAR1_PHYS_SIZE, 690 &memory, &size); 691 692 /* 693 * This function automatically merges address 694 * regions next to each other if they are 695 * received in incrementing order. 696 */ 697 if (size) 698 add_memory_region(memory, size, BOOT_MEM_RAM); 699 total += mem_alloc_size; 700 } else { 701 break; 702 } 703 } 704 cvmx_bootmem_unlock(); 705 706 #ifdef CONFIG_CAVIUM_RESERVE32 707 /* 708 * Now that we've allocated the kernel memory it is safe to 709 * free the reserved region. We free it here so that builtin 710 * drivers can use the memory. 711 */ 712 if (octeon_reserve32_memory) 713 cvmx_bootmem_free_named("CAVIUM_RESERVE32"); 714 #endif /* CONFIG_CAVIUM_RESERVE32 */ 715 716 if (total == 0) 717 panic("Unable to allocate memory from " 718 "cvmx_bootmem_phy_alloc\n"); 719 } 720 721 /* 722 * Emit one character to the boot UART. Exported for use by the 723 * watchdog timer. 724 */ 725 int prom_putchar(char c) 726 { 727 uint64_t lsrval; 728 729 /* Spin until there is room */ 730 do { 731 lsrval = cvmx_read_csr(CVMX_MIO_UARTX_LSR(octeon_uart)); 732 } while ((lsrval & 0x20) == 0); 733 734 /* Write the byte */ 735 cvmx_write_csr(CVMX_MIO_UARTX_THR(octeon_uart), c & 0xffull); 736 return 1; 737 } 738 EXPORT_SYMBOL(prom_putchar); 739 740 void prom_free_prom_memory(void) 741 { 742 if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X)) { 743 /* Check for presence of Core-14449 fix. */ 744 u32 insn; 745 u32 *foo; 746 747 foo = &insn; 748 749 asm volatile("# before" : : : "memory"); 750 prefetch(foo); 751 asm volatile( 752 ".set push\n\t" 753 ".set noreorder\n\t" 754 "bal 1f\n\t" 755 "nop\n" 756 "1:\tlw %0,-12($31)\n\t" 757 ".set pop\n\t" 758 : "=r" (insn) : : "$31", "memory"); 759 760 if ((insn >> 26) != 0x33) 761 panic("No PREF instruction at Core-14449 probe point."); 762 763 if (((insn >> 16) & 0x1f) != 28) 764 panic("Core-14449 WAR not in place (%04x).\n" 765 "Please build kernel with proper options (CONFIG_CAVIUM_CN63XXP1).", insn); 766 } 767 #ifdef CONFIG_CAVIUM_DECODE_RSL 768 cvmx_interrupt_rsl_enable(); 769 770 /* Add an interrupt handler for general failures. */ 771 if (request_irq(OCTEON_IRQ_RML, octeon_rlm_interrupt, IRQF_SHARED, 772 "RML/RSL", octeon_rlm_interrupt)) { 773 panic("Unable to request_irq(OCTEON_IRQ_RML)"); 774 } 775 #endif 776 } 777