1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2004-2007 Cavium Networks 7 * Copyright (C) 2008 Wind River Systems 8 */ 9 #include <linux/init.h> 10 #include <linux/console.h> 11 #include <linux/delay.h> 12 #include <linux/interrupt.h> 13 #include <linux/io.h> 14 #include <linux/serial.h> 15 #include <linux/smp.h> 16 #include <linux/types.h> 17 #include <linux/string.h> /* for memset */ 18 #include <linux/tty.h> 19 #include <linux/time.h> 20 #include <linux/platform_device.h> 21 #include <linux/serial_core.h> 22 #include <linux/serial_8250.h> 23 24 #include <asm/processor.h> 25 #include <asm/reboot.h> 26 #include <asm/smp-ops.h> 27 #include <asm/system.h> 28 #include <asm/irq_cpu.h> 29 #include <asm/mipsregs.h> 30 #include <asm/bootinfo.h> 31 #include <asm/sections.h> 32 #include <asm/time.h> 33 34 #include <asm/octeon/octeon.h> 35 36 #ifdef CONFIG_CAVIUM_DECODE_RSL 37 extern void cvmx_interrupt_rsl_decode(void); 38 extern int __cvmx_interrupt_ecc_report_single_bit_errors; 39 extern void cvmx_interrupt_rsl_enable(void); 40 #endif 41 42 extern struct plat_smp_ops octeon_smp_ops; 43 44 #ifdef CONFIG_PCI 45 extern void pci_console_init(const char *arg); 46 #endif 47 48 static unsigned long long MAX_MEMORY = 512ull << 20; 49 50 struct octeon_boot_descriptor *octeon_boot_desc_ptr; 51 52 struct cvmx_bootinfo *octeon_bootinfo; 53 EXPORT_SYMBOL(octeon_bootinfo); 54 55 #ifdef CONFIG_CAVIUM_RESERVE32 56 uint64_t octeon_reserve32_memory; 57 EXPORT_SYMBOL(octeon_reserve32_memory); 58 #endif 59 60 static int octeon_uart; 61 62 extern asmlinkage void handle_int(void); 63 extern asmlinkage void plat_irq_dispatch(void); 64 65 /** 66 * Return non zero if we are currently running in the Octeon simulator 67 * 68 * Returns 69 */ 70 int octeon_is_simulation(void) 71 { 72 return octeon_bootinfo->board_type == CVMX_BOARD_TYPE_SIM; 73 } 74 EXPORT_SYMBOL(octeon_is_simulation); 75 76 /** 77 * Return true if Octeon is in PCI Host mode. This means 78 * Linux can control the PCI bus. 79 * 80 * Returns Non zero if Octeon in host mode. 81 */ 82 int octeon_is_pci_host(void) 83 { 84 #ifdef CONFIG_PCI 85 return octeon_bootinfo->config_flags & CVMX_BOOTINFO_CFG_FLAG_PCI_HOST; 86 #else 87 return 0; 88 #endif 89 } 90 91 /** 92 * Get the clock rate of Octeon 93 * 94 * Returns Clock rate in HZ 95 */ 96 uint64_t octeon_get_clock_rate(void) 97 { 98 if (octeon_is_simulation()) 99 octeon_bootinfo->eclock_hz = 6000000; 100 return octeon_bootinfo->eclock_hz; 101 } 102 EXPORT_SYMBOL(octeon_get_clock_rate); 103 104 /** 105 * Write to the LCD display connected to the bootbus. This display 106 * exists on most Cavium evaluation boards. If it doesn't exist, then 107 * this function doesn't do anything. 108 * 109 * @s: String to write 110 */ 111 void octeon_write_lcd(const char *s) 112 { 113 if (octeon_bootinfo->led_display_base_addr) { 114 void __iomem *lcd_address = 115 ioremap_nocache(octeon_bootinfo->led_display_base_addr, 116 8); 117 int i; 118 for (i = 0; i < 8; i++, s++) { 119 if (*s) 120 iowrite8(*s, lcd_address + i); 121 else 122 iowrite8(' ', lcd_address + i); 123 } 124 iounmap(lcd_address); 125 } 126 } 127 128 /** 129 * Return the console uart passed by the bootloader 130 * 131 * Returns uart (0 or 1) 132 */ 133 int octeon_get_boot_uart(void) 134 { 135 int uart; 136 #ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL 137 uart = 1; 138 #else 139 uart = (octeon_boot_desc_ptr->flags & OCTEON_BL_FLAG_CONSOLE_UART1) ? 140 1 : 0; 141 #endif 142 return uart; 143 } 144 145 /** 146 * Get the coremask Linux was booted on. 147 * 148 * Returns Core mask 149 */ 150 int octeon_get_boot_coremask(void) 151 { 152 return octeon_boot_desc_ptr->core_mask; 153 } 154 155 /** 156 * Check the hardware BIST results for a CPU 157 */ 158 void octeon_check_cpu_bist(void) 159 { 160 const int coreid = cvmx_get_core_num(); 161 unsigned long long mask; 162 unsigned long long bist_val; 163 164 /* Check BIST results for COP0 registers */ 165 mask = 0x1f00000000ull; 166 bist_val = read_octeon_c0_icacheerr(); 167 if (bist_val & mask) 168 pr_err("Core%d BIST Failure: CacheErr(icache) = 0x%llx\n", 169 coreid, bist_val); 170 171 bist_val = read_octeon_c0_dcacheerr(); 172 if (bist_val & 1) 173 pr_err("Core%d L1 Dcache parity error: " 174 "CacheErr(dcache) = 0x%llx\n", 175 coreid, bist_val); 176 177 mask = 0xfc00000000000000ull; 178 bist_val = read_c0_cvmmemctl(); 179 if (bist_val & mask) 180 pr_err("Core%d BIST Failure: COP0_CVM_MEM_CTL = 0x%llx\n", 181 coreid, bist_val); 182 183 write_octeon_c0_dcacheerr(0); 184 } 185 186 /** 187 * Reboot Octeon 188 * 189 * @command: Command to pass to the bootloader. Currently ignored. 190 */ 191 static void octeon_restart(char *command) 192 { 193 /* Disable all watchdogs before soft reset. They don't get cleared */ 194 #ifdef CONFIG_SMP 195 int cpu; 196 for_each_online_cpu(cpu) 197 cvmx_write_csr(CVMX_CIU_WDOGX(cpu_logical_map(cpu)), 0); 198 #else 199 cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0); 200 #endif 201 202 mb(); 203 while (1) 204 cvmx_write_csr(CVMX_CIU_SOFT_RST, 1); 205 } 206 207 208 /** 209 * Permanently stop a core. 210 * 211 * @arg: Ignored. 212 */ 213 static void octeon_kill_core(void *arg) 214 { 215 mb(); 216 if (octeon_is_simulation()) { 217 /* The simulator needs the watchdog to stop for dead cores */ 218 cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0); 219 /* A break instruction causes the simulator stop a core */ 220 asm volatile ("sync\nbreak"); 221 } 222 } 223 224 225 /** 226 * Halt the system 227 */ 228 static void octeon_halt(void) 229 { 230 smp_call_function(octeon_kill_core, NULL, 0); 231 232 switch (octeon_bootinfo->board_type) { 233 case CVMX_BOARD_TYPE_NAO38: 234 /* Driving a 1 to GPIO 12 shuts off this board */ 235 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(12), 1); 236 cvmx_write_csr(CVMX_GPIO_TX_SET, 0x1000); 237 break; 238 default: 239 octeon_write_lcd("PowerOff"); 240 break; 241 } 242 243 octeon_kill_core(NULL); 244 } 245 246 /** 247 * Handle all the error condition interrupts that might occur. 248 * 249 */ 250 #ifdef CONFIG_CAVIUM_DECODE_RSL 251 static irqreturn_t octeon_rlm_interrupt(int cpl, void *dev_id) 252 { 253 cvmx_interrupt_rsl_decode(); 254 return IRQ_HANDLED; 255 } 256 #endif 257 258 /** 259 * Return a string representing the system type 260 * 261 * Returns 262 */ 263 const char *octeon_board_type_string(void) 264 { 265 static char name[80]; 266 sprintf(name, "%s (%s)", 267 cvmx_board_type_to_string(octeon_bootinfo->board_type), 268 octeon_model_get_string(read_c0_prid())); 269 return name; 270 } 271 272 const char *get_system_type(void) 273 __attribute__ ((alias("octeon_board_type_string"))); 274 275 void octeon_user_io_init(void) 276 { 277 union octeon_cvmemctl cvmmemctl; 278 union cvmx_iob_fau_timeout fau_timeout; 279 union cvmx_pow_nw_tim nm_tim; 280 uint64_t cvmctl; 281 282 /* Get the current settings for CP0_CVMMEMCTL_REG */ 283 cvmmemctl.u64 = read_c0_cvmmemctl(); 284 /* R/W If set, marked write-buffer entries time out the same 285 * as as other entries; if clear, marked write-buffer entries 286 * use the maximum timeout. */ 287 cvmmemctl.s.dismarkwblongto = 1; 288 /* R/W If set, a merged store does not clear the write-buffer 289 * entry timeout state. */ 290 cvmmemctl.s.dismrgclrwbto = 0; 291 /* R/W Two bits that are the MSBs of the resultant CVMSEG LM 292 * word location for an IOBDMA. The other 8 bits come from the 293 * SCRADDR field of the IOBDMA. */ 294 cvmmemctl.s.iobdmascrmsb = 0; 295 /* R/W If set, SYNCWS and SYNCS only order marked stores; if 296 * clear, SYNCWS and SYNCS only order unmarked 297 * stores. SYNCWSMARKED has no effect when DISSYNCWS is 298 * set. */ 299 cvmmemctl.s.syncwsmarked = 0; 300 /* R/W If set, SYNCWS acts as SYNCW and SYNCS acts as SYNC. */ 301 cvmmemctl.s.dissyncws = 0; 302 /* R/W If set, no stall happens on write buffer full. */ 303 if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2)) 304 cvmmemctl.s.diswbfst = 1; 305 else 306 cvmmemctl.s.diswbfst = 0; 307 /* R/W If set (and SX set), supervisor-level loads/stores can 308 * use XKPHYS addresses with <48>==0 */ 309 cvmmemctl.s.xkmemenas = 0; 310 311 /* R/W If set (and UX set), user-level loads/stores can use 312 * XKPHYS addresses with VA<48>==0 */ 313 cvmmemctl.s.xkmemenau = 0; 314 315 /* R/W If set (and SX set), supervisor-level loads/stores can 316 * use XKPHYS addresses with VA<48>==1 */ 317 cvmmemctl.s.xkioenas = 0; 318 319 /* R/W If set (and UX set), user-level loads/stores can use 320 * XKPHYS addresses with VA<48>==1 */ 321 cvmmemctl.s.xkioenau = 0; 322 323 /* R/W If set, all stores act as SYNCW (NOMERGE must be set 324 * when this is set) RW, reset to 0. */ 325 cvmmemctl.s.allsyncw = 0; 326 327 /* R/W If set, no stores merge, and all stores reach the 328 * coherent bus in order. */ 329 cvmmemctl.s.nomerge = 0; 330 /* R/W Selects the bit in the counter used for DID time-outs 0 331 * = 231, 1 = 230, 2 = 229, 3 = 214. Actual time-out is 332 * between 1x and 2x this interval. For example, with 333 * DIDTTO=3, expiration interval is between 16K and 32K. */ 334 cvmmemctl.s.didtto = 0; 335 /* R/W If set, the (mem) CSR clock never turns off. */ 336 cvmmemctl.s.csrckalwys = 0; 337 /* R/W If set, mclk never turns off. */ 338 cvmmemctl.s.mclkalwys = 0; 339 /* R/W Selects the bit in the counter used for write buffer 340 * flush time-outs (WBFLT+11) is the bit position in an 341 * internal counter used to determine expiration. The write 342 * buffer expires between 1x and 2x this interval. For 343 * example, with WBFLT = 0, a write buffer expires between 2K 344 * and 4K cycles after the write buffer entry is allocated. */ 345 cvmmemctl.s.wbfltime = 0; 346 /* R/W If set, do not put Istream in the L2 cache. */ 347 cvmmemctl.s.istrnol2 = 0; 348 /* R/W The write buffer threshold. */ 349 cvmmemctl.s.wbthresh = 10; 350 /* R/W If set, CVMSEG is available for loads/stores in 351 * kernel/debug mode. */ 352 #if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0 353 cvmmemctl.s.cvmsegenak = 1; 354 #else 355 cvmmemctl.s.cvmsegenak = 0; 356 #endif 357 /* R/W If set, CVMSEG is available for loads/stores in 358 * supervisor mode. */ 359 cvmmemctl.s.cvmsegenas = 0; 360 /* R/W If set, CVMSEG is available for loads/stores in user 361 * mode. */ 362 cvmmemctl.s.cvmsegenau = 0; 363 /* R/W Size of local memory in cache blocks, 54 (6912 bytes) 364 * is max legal value. */ 365 cvmmemctl.s.lmemsz = CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE; 366 367 368 if (smp_processor_id() == 0) 369 pr_notice("CVMSEG size: %d cache lines (%d bytes)\n", 370 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE, 371 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128); 372 373 write_c0_cvmmemctl(cvmmemctl.u64); 374 375 /* Move the performance counter interrupts to IRQ 6 */ 376 cvmctl = read_c0_cvmctl(); 377 cvmctl &= ~(7 << 7); 378 cvmctl |= 6 << 7; 379 write_c0_cvmctl(cvmctl); 380 381 /* Set a default for the hardware timeouts */ 382 fau_timeout.u64 = 0; 383 fau_timeout.s.tout_val = 0xfff; 384 /* Disable tagwait FAU timeout */ 385 fau_timeout.s.tout_enb = 0; 386 cvmx_write_csr(CVMX_IOB_FAU_TIMEOUT, fau_timeout.u64); 387 388 nm_tim.u64 = 0; 389 /* 4096 cycles */ 390 nm_tim.s.nw_tim = 3; 391 cvmx_write_csr(CVMX_POW_NW_TIM, nm_tim.u64); 392 393 write_octeon_c0_icacheerr(0); 394 write_c0_derraddr1(0); 395 } 396 397 /** 398 * Early entry point for arch setup 399 */ 400 void __init prom_init(void) 401 { 402 struct cvmx_sysinfo *sysinfo; 403 const int coreid = cvmx_get_core_num(); 404 int i; 405 int argc; 406 #ifdef CONFIG_CAVIUM_RESERVE32 407 int64_t addr = -1; 408 #endif 409 /* 410 * The bootloader passes a pointer to the boot descriptor in 411 * $a3, this is available as fw_arg3. 412 */ 413 octeon_boot_desc_ptr = (struct octeon_boot_descriptor *)fw_arg3; 414 octeon_bootinfo = 415 cvmx_phys_to_ptr(octeon_boot_desc_ptr->cvmx_desc_vaddr); 416 cvmx_bootmem_init(cvmx_phys_to_ptr(octeon_bootinfo->phy_mem_desc_addr)); 417 418 /* 419 * Only enable the LED controller if we're running on a CN38XX, CN58XX, 420 * or CN56XX. The CN30XX and CN31XX don't have an LED controller. 421 */ 422 if (!octeon_is_simulation() && 423 octeon_has_feature(OCTEON_FEATURE_LED_CONTROLLER)) { 424 cvmx_write_csr(CVMX_LED_EN, 0); 425 cvmx_write_csr(CVMX_LED_PRT, 0); 426 cvmx_write_csr(CVMX_LED_DBG, 0); 427 cvmx_write_csr(CVMX_LED_PRT_FMT, 0); 428 cvmx_write_csr(CVMX_LED_UDD_CNTX(0), 32); 429 cvmx_write_csr(CVMX_LED_UDD_CNTX(1), 32); 430 cvmx_write_csr(CVMX_LED_UDD_DATX(0), 0); 431 cvmx_write_csr(CVMX_LED_UDD_DATX(1), 0); 432 cvmx_write_csr(CVMX_LED_EN, 1); 433 } 434 #ifdef CONFIG_CAVIUM_RESERVE32 435 /* 436 * We need to temporarily allocate all memory in the reserve32 437 * region. This makes sure the kernel doesn't allocate this 438 * memory when it is getting memory from the 439 * bootloader. Later, after the memory allocations are 440 * complete, the reserve32 will be freed. 441 * 442 * Allocate memory for RESERVED32 aligned on 2MB boundary. This 443 * is in case we later use hugetlb entries with it. 444 */ 445 addr = cvmx_bootmem_phy_named_block_alloc(CONFIG_CAVIUM_RESERVE32 << 20, 446 0, 0, 2 << 20, 447 "CAVIUM_RESERVE32", 0); 448 if (addr < 0) 449 pr_err("Failed to allocate CAVIUM_RESERVE32 memory area\n"); 450 else 451 octeon_reserve32_memory = addr; 452 #endif 453 454 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2 455 if (cvmx_read_csr(CVMX_L2D_FUS3) & (3ull << 34)) { 456 pr_info("Skipping L2 locking due to reduced L2 cache size\n"); 457 } else { 458 uint32_t ebase = read_c0_ebase() & 0x3ffff000; 459 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_TLB 460 /* TLB refill */ 461 cvmx_l2c_lock_mem_region(ebase, 0x100); 462 #endif 463 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_EXCEPTION 464 /* General exception */ 465 cvmx_l2c_lock_mem_region(ebase + 0x180, 0x80); 466 #endif 467 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT 468 /* Interrupt handler */ 469 cvmx_l2c_lock_mem_region(ebase + 0x200, 0x80); 470 #endif 471 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_INTERRUPT 472 cvmx_l2c_lock_mem_region(__pa_symbol(handle_int), 0x100); 473 cvmx_l2c_lock_mem_region(__pa_symbol(plat_irq_dispatch), 0x80); 474 #endif 475 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_MEMCPY 476 cvmx_l2c_lock_mem_region(__pa_symbol(memcpy), 0x480); 477 #endif 478 } 479 #endif 480 481 sysinfo = cvmx_sysinfo_get(); 482 memset(sysinfo, 0, sizeof(*sysinfo)); 483 sysinfo->system_dram_size = octeon_bootinfo->dram_size << 20; 484 sysinfo->phy_mem_desc_ptr = 485 cvmx_phys_to_ptr(octeon_bootinfo->phy_mem_desc_addr); 486 sysinfo->core_mask = octeon_bootinfo->core_mask; 487 sysinfo->exception_base_addr = octeon_bootinfo->exception_base_addr; 488 sysinfo->cpu_clock_hz = octeon_bootinfo->eclock_hz; 489 sysinfo->dram_data_rate_hz = octeon_bootinfo->dclock_hz * 2; 490 sysinfo->board_type = octeon_bootinfo->board_type; 491 sysinfo->board_rev_major = octeon_bootinfo->board_rev_major; 492 sysinfo->board_rev_minor = octeon_bootinfo->board_rev_minor; 493 memcpy(sysinfo->mac_addr_base, octeon_bootinfo->mac_addr_base, 494 sizeof(sysinfo->mac_addr_base)); 495 sysinfo->mac_addr_count = octeon_bootinfo->mac_addr_count; 496 memcpy(sysinfo->board_serial_number, 497 octeon_bootinfo->board_serial_number, 498 sizeof(sysinfo->board_serial_number)); 499 sysinfo->compact_flash_common_base_addr = 500 octeon_bootinfo->compact_flash_common_base_addr; 501 sysinfo->compact_flash_attribute_base_addr = 502 octeon_bootinfo->compact_flash_attribute_base_addr; 503 sysinfo->led_display_base_addr = octeon_bootinfo->led_display_base_addr; 504 sysinfo->dfa_ref_clock_hz = octeon_bootinfo->dfa_ref_clock_hz; 505 sysinfo->bootloader_config_flags = octeon_bootinfo->config_flags; 506 507 508 octeon_check_cpu_bist(); 509 510 octeon_uart = octeon_get_boot_uart(); 511 512 /* 513 * Disable All CIU Interrupts. The ones we need will be 514 * enabled later. Read the SUM register so we know the write 515 * completed. 516 */ 517 cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2)), 0); 518 cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2 + 1)), 0); 519 cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2)), 0); 520 cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2 + 1)), 0); 521 cvmx_read_csr(CVMX_CIU_INTX_SUM0((coreid * 2))); 522 523 #ifdef CONFIG_SMP 524 octeon_write_lcd("LinuxSMP"); 525 #else 526 octeon_write_lcd("Linux"); 527 #endif 528 529 #ifdef CONFIG_CAVIUM_GDB 530 /* 531 * When debugging the linux kernel, force the cores to enter 532 * the debug exception handler to break in. 533 */ 534 if (octeon_get_boot_debug_flag()) { 535 cvmx_write_csr(CVMX_CIU_DINT, 1 << cvmx_get_core_num()); 536 cvmx_read_csr(CVMX_CIU_DINT); 537 } 538 #endif 539 540 /* 541 * BIST should always be enabled when doing a soft reset. L2 542 * Cache locking for instance is not cleared unless BIST is 543 * enabled. Unfortunately due to a chip errata G-200 for 544 * Cn38XX and CN31XX, BIST msut be disabled on these parts. 545 */ 546 if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2) || 547 OCTEON_IS_MODEL(OCTEON_CN31XX)) 548 cvmx_write_csr(CVMX_CIU_SOFT_BIST, 0); 549 else 550 cvmx_write_csr(CVMX_CIU_SOFT_BIST, 1); 551 552 /* Default to 64MB in the simulator to speed things up */ 553 if (octeon_is_simulation()) 554 MAX_MEMORY = 64ull << 20; 555 556 arcs_cmdline[0] = 0; 557 argc = octeon_boot_desc_ptr->argc; 558 for (i = 0; i < argc; i++) { 559 const char *arg = 560 cvmx_phys_to_ptr(octeon_boot_desc_ptr->argv[i]); 561 if ((strncmp(arg, "MEM=", 4) == 0) || 562 (strncmp(arg, "mem=", 4) == 0)) { 563 sscanf(arg + 4, "%llu", &MAX_MEMORY); 564 MAX_MEMORY <<= 20; 565 if (MAX_MEMORY == 0) 566 MAX_MEMORY = 32ull << 30; 567 } else if (strcmp(arg, "ecc_verbose") == 0) { 568 #ifdef CONFIG_CAVIUM_REPORT_SINGLE_BIT_ECC 569 __cvmx_interrupt_ecc_report_single_bit_errors = 1; 570 pr_notice("Reporting of single bit ECC errors is " 571 "turned on\n"); 572 #endif 573 } else if (strlen(arcs_cmdline) + strlen(arg) + 1 < 574 sizeof(arcs_cmdline) - 1) { 575 strcat(arcs_cmdline, " "); 576 strcat(arcs_cmdline, arg); 577 } 578 } 579 580 if (strstr(arcs_cmdline, "console=") == NULL) { 581 #ifdef CONFIG_GDB_CONSOLE 582 strcat(arcs_cmdline, " console=gdb"); 583 #else 584 #ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL 585 strcat(arcs_cmdline, " console=ttyS0,115200"); 586 #else 587 if (octeon_uart == 1) 588 strcat(arcs_cmdline, " console=ttyS1,115200"); 589 else 590 strcat(arcs_cmdline, " console=ttyS0,115200"); 591 #endif 592 #endif 593 } 594 595 if (octeon_is_simulation()) { 596 /* 597 * The simulator uses a mtdram device pre filled with 598 * the filesystem. Also specify the calibration delay 599 * to avoid calculating it every time. 600 */ 601 strcat(arcs_cmdline, " rw root=1f00" 602 " lpj=60176 slram=root,0x40000000,+1073741824"); 603 } 604 605 mips_hpt_frequency = octeon_get_clock_rate(); 606 607 octeon_init_cvmcount(); 608 609 _machine_restart = octeon_restart; 610 _machine_halt = octeon_halt; 611 612 octeon_user_io_init(); 613 register_smp_ops(&octeon_smp_ops); 614 } 615 616 void __init plat_mem_setup(void) 617 { 618 uint64_t mem_alloc_size; 619 uint64_t total; 620 int64_t memory; 621 622 total = 0; 623 624 /* First add the init memory we will be returning. */ 625 memory = __pa_symbol(&__init_begin) & PAGE_MASK; 626 mem_alloc_size = (__pa_symbol(&__init_end) & PAGE_MASK) - memory; 627 if (mem_alloc_size > 0) { 628 add_memory_region(memory, mem_alloc_size, BOOT_MEM_RAM); 629 total += mem_alloc_size; 630 } 631 632 /* 633 * The Mips memory init uses the first memory location for 634 * some memory vectors. When SPARSEMEM is in use, it doesn't 635 * verify that the size is big enough for the final 636 * vectors. Making the smallest chuck 4MB seems to be enough 637 * to consistantly work. 638 */ 639 mem_alloc_size = 4 << 20; 640 if (mem_alloc_size > MAX_MEMORY) 641 mem_alloc_size = MAX_MEMORY; 642 643 /* 644 * When allocating memory, we want incrementing addresses from 645 * bootmem_alloc so the code in add_memory_region can merge 646 * regions next to each other. 647 */ 648 cvmx_bootmem_lock(); 649 while ((boot_mem_map.nr_map < BOOT_MEM_MAP_MAX) 650 && (total < MAX_MEMORY)) { 651 #if defined(CONFIG_64BIT) || defined(CONFIG_64BIT_PHYS_ADDR) 652 memory = cvmx_bootmem_phy_alloc(mem_alloc_size, 653 __pa_symbol(&__init_end), -1, 654 0x100000, 655 CVMX_BOOTMEM_FLAG_NO_LOCKING); 656 #elif defined(CONFIG_HIGHMEM) 657 memory = cvmx_bootmem_phy_alloc(mem_alloc_size, 0, 1ull << 31, 658 0x100000, 659 CVMX_BOOTMEM_FLAG_NO_LOCKING); 660 #else 661 memory = cvmx_bootmem_phy_alloc(mem_alloc_size, 0, 512 << 20, 662 0x100000, 663 CVMX_BOOTMEM_FLAG_NO_LOCKING); 664 #endif 665 if (memory >= 0) { 666 /* 667 * This function automatically merges address 668 * regions next to each other if they are 669 * received in incrementing order. 670 */ 671 add_memory_region(memory, mem_alloc_size, BOOT_MEM_RAM); 672 total += mem_alloc_size; 673 } else { 674 break; 675 } 676 } 677 cvmx_bootmem_unlock(); 678 679 #ifdef CONFIG_CAVIUM_RESERVE32 680 /* 681 * Now that we've allocated the kernel memory it is safe to 682 * free the reserved region. We free it here so that builtin 683 * drivers can use the memory. 684 */ 685 if (octeon_reserve32_memory) 686 cvmx_bootmem_free_named("CAVIUM_RESERVE32"); 687 #endif /* CONFIG_CAVIUM_RESERVE32 */ 688 689 if (total == 0) 690 panic("Unable to allocate memory from " 691 "cvmx_bootmem_phy_alloc\n"); 692 } 693 694 695 int prom_putchar(char c) 696 { 697 uint64_t lsrval; 698 699 /* Spin until there is room */ 700 do { 701 lsrval = cvmx_read_csr(CVMX_MIO_UARTX_LSR(octeon_uart)); 702 } while ((lsrval & 0x20) == 0); 703 704 /* Write the byte */ 705 cvmx_write_csr(CVMX_MIO_UARTX_THR(octeon_uart), c & 0xffull); 706 return 1; 707 } 708 709 void prom_free_prom_memory(void) 710 { 711 #ifdef CONFIG_CAVIUM_DECODE_RSL 712 cvmx_interrupt_rsl_enable(); 713 714 /* Add an interrupt handler for general failures. */ 715 if (request_irq(OCTEON_IRQ_RML, octeon_rlm_interrupt, IRQF_SHARED, 716 "RML/RSL", octeon_rlm_interrupt)) { 717 panic("Unable to request_irq(OCTEON_IRQ_RML)\n"); 718 } 719 #endif 720 } 721