1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2004-2007 Cavium Networks 7 * Copyright (C) 2008, 2009 Wind River Systems 8 * written by Ralf Baechle <ralf@linux-mips.org> 9 */ 10 #include <linux/compiler.h> 11 #include <linux/vmalloc.h> 12 #include <linux/init.h> 13 #include <linux/kernel.h> 14 #include <linux/console.h> 15 #include <linux/delay.h> 16 #include <linux/export.h> 17 #include <linux/interrupt.h> 18 #include <linux/io.h> 19 #include <linux/serial.h> 20 #include <linux/smp.h> 21 #include <linux/types.h> 22 #include <linux/string.h> /* for memset */ 23 #include <linux/tty.h> 24 #include <linux/time.h> 25 #include <linux/platform_device.h> 26 #include <linux/serial_core.h> 27 #include <linux/serial_8250.h> 28 #include <linux/of_fdt.h> 29 #include <linux/libfdt.h> 30 #include <linux/kexec.h> 31 32 #include <asm/processor.h> 33 #include <asm/reboot.h> 34 #include <asm/smp-ops.h> 35 #include <asm/irq_cpu.h> 36 #include <asm/mipsregs.h> 37 #include <asm/bootinfo.h> 38 #include <asm/sections.h> 39 #include <asm/time.h> 40 41 #include <asm/octeon/octeon.h> 42 #include <asm/octeon/pci-octeon.h> 43 #include <asm/octeon/cvmx-rst-defs.h> 44 45 /* 46 * TRUE for devices having registers with little-endian byte 47 * order, FALSE for registers with native-endian byte order. 48 * PCI mandates little-endian, USB and SATA are configuraable, 49 * but we chose little-endian for these. 50 */ 51 const bool octeon_should_swizzle_table[256] = { 52 [0x00] = true, /* bootbus/CF */ 53 [0x1b] = true, /* PCI mmio window */ 54 [0x1c] = true, /* PCI mmio window */ 55 [0x1d] = true, /* PCI mmio window */ 56 [0x1e] = true, /* PCI mmio window */ 57 [0x68] = true, /* OCTEON III USB */ 58 [0x69] = true, /* OCTEON III USB */ 59 [0x6c] = true, /* OCTEON III SATA */ 60 [0x6f] = true, /* OCTEON II USB */ 61 }; 62 EXPORT_SYMBOL(octeon_should_swizzle_table); 63 64 #ifdef CONFIG_PCI 65 extern void pci_console_init(const char *arg); 66 #endif 67 68 static unsigned long long MAX_MEMORY = 512ull << 20; 69 70 DEFINE_SEMAPHORE(octeon_bootbus_sem); 71 EXPORT_SYMBOL(octeon_bootbus_sem); 72 73 struct octeon_boot_descriptor *octeon_boot_desc_ptr; 74 75 struct cvmx_bootinfo *octeon_bootinfo; 76 EXPORT_SYMBOL(octeon_bootinfo); 77 78 static unsigned long long RESERVE_LOW_MEM = 0ull; 79 #ifdef CONFIG_KEXEC 80 #ifdef CONFIG_SMP 81 /* 82 * Wait for relocation code is prepared and send 83 * secondary CPUs to spin until kernel is relocated. 84 */ 85 static void octeon_kexec_smp_down(void *ignored) 86 { 87 int cpu = smp_processor_id(); 88 89 local_irq_disable(); 90 set_cpu_online(cpu, false); 91 while (!atomic_read(&kexec_ready_to_reboot)) 92 cpu_relax(); 93 94 asm volatile ( 95 " sync \n" 96 " synci ($0) \n"); 97 98 relocated_kexec_smp_wait(NULL); 99 } 100 #endif 101 102 #define OCTEON_DDR0_BASE (0x0ULL) 103 #define OCTEON_DDR0_SIZE (0x010000000ULL) 104 #define OCTEON_DDR1_BASE (0x410000000ULL) 105 #define OCTEON_DDR1_SIZE (0x010000000ULL) 106 #define OCTEON_DDR2_BASE (0x020000000ULL) 107 #define OCTEON_DDR2_SIZE (0x3e0000000ULL) 108 #define OCTEON_MAX_PHY_MEM_SIZE (16*1024*1024*1024ULL) 109 110 static struct kimage *kimage_ptr; 111 112 static void kexec_bootmem_init(uint64_t mem_size, uint32_t low_reserved_bytes) 113 { 114 int64_t addr; 115 struct cvmx_bootmem_desc *bootmem_desc; 116 117 bootmem_desc = cvmx_bootmem_get_desc(); 118 119 if (mem_size > OCTEON_MAX_PHY_MEM_SIZE) { 120 mem_size = OCTEON_MAX_PHY_MEM_SIZE; 121 pr_err("Error: requested memory too large," 122 "truncating to maximum size\n"); 123 } 124 125 bootmem_desc->major_version = CVMX_BOOTMEM_DESC_MAJ_VER; 126 bootmem_desc->minor_version = CVMX_BOOTMEM_DESC_MIN_VER; 127 128 addr = (OCTEON_DDR0_BASE + RESERVE_LOW_MEM + low_reserved_bytes); 129 bootmem_desc->head_addr = 0; 130 131 if (mem_size <= OCTEON_DDR0_SIZE) { 132 __cvmx_bootmem_phy_free(addr, 133 mem_size - RESERVE_LOW_MEM - 134 low_reserved_bytes, 0); 135 return; 136 } 137 138 __cvmx_bootmem_phy_free(addr, 139 OCTEON_DDR0_SIZE - RESERVE_LOW_MEM - 140 low_reserved_bytes, 0); 141 142 mem_size -= OCTEON_DDR0_SIZE; 143 144 if (mem_size > OCTEON_DDR1_SIZE) { 145 __cvmx_bootmem_phy_free(OCTEON_DDR1_BASE, OCTEON_DDR1_SIZE, 0); 146 __cvmx_bootmem_phy_free(OCTEON_DDR2_BASE, 147 mem_size - OCTEON_DDR1_SIZE, 0); 148 } else 149 __cvmx_bootmem_phy_free(OCTEON_DDR1_BASE, mem_size, 0); 150 } 151 152 static int octeon_kexec_prepare(struct kimage *image) 153 { 154 int i; 155 char *bootloader = "kexec"; 156 157 octeon_boot_desc_ptr->argc = 0; 158 for (i = 0; i < image->nr_segments; i++) { 159 if (!strncmp(bootloader, (char *)image->segment[i].buf, 160 strlen(bootloader))) { 161 /* 162 * convert command line string to array 163 * of parameters (as bootloader does). 164 */ 165 int argc = 0, offt; 166 char *str = (char *)image->segment[i].buf; 167 char *ptr = strchr(str, ' '); 168 while (ptr && (OCTEON_ARGV_MAX_ARGS > argc)) { 169 *ptr = '\0'; 170 if (ptr[1] != ' ') { 171 offt = (int)(ptr - str + 1); 172 octeon_boot_desc_ptr->argv[argc] = 173 image->segment[i].mem + offt; 174 argc++; 175 } 176 ptr = strchr(ptr + 1, ' '); 177 } 178 octeon_boot_desc_ptr->argc = argc; 179 break; 180 } 181 } 182 183 /* 184 * Information about segments will be needed during pre-boot memory 185 * initialization. 186 */ 187 kimage_ptr = image; 188 return 0; 189 } 190 191 static void octeon_generic_shutdown(void) 192 { 193 int i; 194 #ifdef CONFIG_SMP 195 int cpu; 196 #endif 197 struct cvmx_bootmem_desc *bootmem_desc; 198 void *named_block_array_ptr; 199 200 bootmem_desc = cvmx_bootmem_get_desc(); 201 named_block_array_ptr = 202 cvmx_phys_to_ptr(bootmem_desc->named_block_array_addr); 203 204 #ifdef CONFIG_SMP 205 /* disable watchdogs */ 206 for_each_online_cpu(cpu) 207 cvmx_write_csr(CVMX_CIU_WDOGX(cpu_logical_map(cpu)), 0); 208 #else 209 cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0); 210 #endif 211 if (kimage_ptr != kexec_crash_image) { 212 memset(named_block_array_ptr, 213 0x0, 214 CVMX_BOOTMEM_NUM_NAMED_BLOCKS * 215 sizeof(struct cvmx_bootmem_named_block_desc)); 216 /* 217 * Mark all memory (except low 0x100000 bytes) as free. 218 * It is the same thing that bootloader does. 219 */ 220 kexec_bootmem_init(octeon_bootinfo->dram_size*1024ULL*1024ULL, 221 0x100000); 222 /* 223 * Allocate all segments to avoid their corruption during boot. 224 */ 225 for (i = 0; i < kimage_ptr->nr_segments; i++) 226 cvmx_bootmem_alloc_address( 227 kimage_ptr->segment[i].memsz + 2*PAGE_SIZE, 228 kimage_ptr->segment[i].mem - PAGE_SIZE, 229 PAGE_SIZE); 230 } else { 231 /* 232 * Do not mark all memory as free. Free only named sections 233 * leaving the rest of memory unchanged. 234 */ 235 struct cvmx_bootmem_named_block_desc *ptr = 236 (struct cvmx_bootmem_named_block_desc *) 237 named_block_array_ptr; 238 239 for (i = 0; i < bootmem_desc->named_block_num_blocks; i++) 240 if (ptr[i].size) 241 cvmx_bootmem_free_named(ptr[i].name); 242 } 243 kexec_args[2] = 1UL; /* running on octeon_main_processor */ 244 kexec_args[3] = (unsigned long)octeon_boot_desc_ptr; 245 #ifdef CONFIG_SMP 246 secondary_kexec_args[2] = 0UL; /* running on secondary cpu */ 247 secondary_kexec_args[3] = (unsigned long)octeon_boot_desc_ptr; 248 #endif 249 } 250 251 static void octeon_shutdown(void) 252 { 253 octeon_generic_shutdown(); 254 #ifdef CONFIG_SMP 255 smp_call_function(octeon_kexec_smp_down, NULL, 0); 256 smp_wmb(); 257 while (num_online_cpus() > 1) { 258 cpu_relax(); 259 mdelay(1); 260 } 261 #endif 262 } 263 264 static void octeon_crash_shutdown(struct pt_regs *regs) 265 { 266 octeon_generic_shutdown(); 267 default_machine_crash_shutdown(regs); 268 } 269 270 #endif /* CONFIG_KEXEC */ 271 272 #ifdef CONFIG_CAVIUM_RESERVE32 273 uint64_t octeon_reserve32_memory; 274 EXPORT_SYMBOL(octeon_reserve32_memory); 275 #endif 276 277 #ifdef CONFIG_KEXEC 278 /* crashkernel cmdline parameter is parsed _after_ memory setup 279 * we also parse it here (workaround for EHB5200) */ 280 static uint64_t crashk_size, crashk_base; 281 #endif 282 283 static int octeon_uart; 284 285 extern asmlinkage void handle_int(void); 286 287 /** 288 * Return non zero if we are currently running in the Octeon simulator 289 * 290 * Returns 291 */ 292 int octeon_is_simulation(void) 293 { 294 return octeon_bootinfo->board_type == CVMX_BOARD_TYPE_SIM; 295 } 296 EXPORT_SYMBOL(octeon_is_simulation); 297 298 /** 299 * Return true if Octeon is in PCI Host mode. This means 300 * Linux can control the PCI bus. 301 * 302 * Returns Non zero if Octeon in host mode. 303 */ 304 int octeon_is_pci_host(void) 305 { 306 #ifdef CONFIG_PCI 307 return octeon_bootinfo->config_flags & CVMX_BOOTINFO_CFG_FLAG_PCI_HOST; 308 #else 309 return 0; 310 #endif 311 } 312 313 /** 314 * Get the clock rate of Octeon 315 * 316 * Returns Clock rate in HZ 317 */ 318 uint64_t octeon_get_clock_rate(void) 319 { 320 struct cvmx_sysinfo *sysinfo = cvmx_sysinfo_get(); 321 322 return sysinfo->cpu_clock_hz; 323 } 324 EXPORT_SYMBOL(octeon_get_clock_rate); 325 326 static u64 octeon_io_clock_rate; 327 328 u64 octeon_get_io_clock_rate(void) 329 { 330 return octeon_io_clock_rate; 331 } 332 EXPORT_SYMBOL(octeon_get_io_clock_rate); 333 334 335 /** 336 * Write to the LCD display connected to the bootbus. This display 337 * exists on most Cavium evaluation boards. If it doesn't exist, then 338 * this function doesn't do anything. 339 * 340 * @s: String to write 341 */ 342 void octeon_write_lcd(const char *s) 343 { 344 if (octeon_bootinfo->led_display_base_addr) { 345 void __iomem *lcd_address = 346 ioremap_nocache(octeon_bootinfo->led_display_base_addr, 347 8); 348 int i; 349 for (i = 0; i < 8; i++, s++) { 350 if (*s) 351 iowrite8(*s, lcd_address + i); 352 else 353 iowrite8(' ', lcd_address + i); 354 } 355 iounmap(lcd_address); 356 } 357 } 358 359 /** 360 * Return the console uart passed by the bootloader 361 * 362 * Returns uart (0 or 1) 363 */ 364 int octeon_get_boot_uart(void) 365 { 366 int uart; 367 #ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL 368 uart = 1; 369 #else 370 uart = (octeon_boot_desc_ptr->flags & OCTEON_BL_FLAG_CONSOLE_UART1) ? 371 1 : 0; 372 #endif 373 return uart; 374 } 375 376 /** 377 * Get the coremask Linux was booted on. 378 * 379 * Returns Core mask 380 */ 381 int octeon_get_boot_coremask(void) 382 { 383 return octeon_boot_desc_ptr->core_mask; 384 } 385 386 /** 387 * Check the hardware BIST results for a CPU 388 */ 389 void octeon_check_cpu_bist(void) 390 { 391 const int coreid = cvmx_get_core_num(); 392 unsigned long long mask; 393 unsigned long long bist_val; 394 395 /* Check BIST results for COP0 registers */ 396 mask = 0x1f00000000ull; 397 bist_val = read_octeon_c0_icacheerr(); 398 if (bist_val & mask) 399 pr_err("Core%d BIST Failure: CacheErr(icache) = 0x%llx\n", 400 coreid, bist_val); 401 402 bist_val = read_octeon_c0_dcacheerr(); 403 if (bist_val & 1) 404 pr_err("Core%d L1 Dcache parity error: " 405 "CacheErr(dcache) = 0x%llx\n", 406 coreid, bist_val); 407 408 mask = 0xfc00000000000000ull; 409 bist_val = read_c0_cvmmemctl(); 410 if (bist_val & mask) 411 pr_err("Core%d BIST Failure: COP0_CVM_MEM_CTL = 0x%llx\n", 412 coreid, bist_val); 413 414 write_octeon_c0_dcacheerr(0); 415 } 416 417 /** 418 * Reboot Octeon 419 * 420 * @command: Command to pass to the bootloader. Currently ignored. 421 */ 422 static void octeon_restart(char *command) 423 { 424 /* Disable all watchdogs before soft reset. They don't get cleared */ 425 #ifdef CONFIG_SMP 426 int cpu; 427 for_each_online_cpu(cpu) 428 cvmx_write_csr(CVMX_CIU_WDOGX(cpu_logical_map(cpu)), 0); 429 #else 430 cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0); 431 #endif 432 433 mb(); 434 while (1) 435 if (OCTEON_IS_OCTEON3()) 436 cvmx_write_csr(CVMX_RST_SOFT_RST, 1); 437 else 438 cvmx_write_csr(CVMX_CIU_SOFT_RST, 1); 439 } 440 441 442 /** 443 * Permanently stop a core. 444 * 445 * @arg: Ignored. 446 */ 447 static void octeon_kill_core(void *arg) 448 { 449 if (octeon_is_simulation()) 450 /* A break instruction causes the simulator stop a core */ 451 asm volatile ("break" ::: "memory"); 452 453 local_irq_disable(); 454 /* Disable watchdog on this core. */ 455 cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0); 456 /* Spin in a low power mode. */ 457 while (true) 458 asm volatile ("wait" ::: "memory"); 459 } 460 461 462 /** 463 * Halt the system 464 */ 465 static void octeon_halt(void) 466 { 467 smp_call_function(octeon_kill_core, NULL, 0); 468 469 switch (octeon_bootinfo->board_type) { 470 case CVMX_BOARD_TYPE_NAO38: 471 /* Driving a 1 to GPIO 12 shuts off this board */ 472 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(12), 1); 473 cvmx_write_csr(CVMX_GPIO_TX_SET, 0x1000); 474 break; 475 default: 476 octeon_write_lcd("PowerOff"); 477 break; 478 } 479 480 octeon_kill_core(NULL); 481 } 482 483 static char __read_mostly octeon_system_type[80]; 484 485 static void __init init_octeon_system_type(void) 486 { 487 char const *board_type; 488 489 board_type = cvmx_board_type_to_string(octeon_bootinfo->board_type); 490 if (board_type == NULL) { 491 struct device_node *root; 492 int ret; 493 494 root = of_find_node_by_path("/"); 495 ret = of_property_read_string(root, "model", &board_type); 496 of_node_put(root); 497 if (ret) 498 board_type = "Unsupported Board"; 499 } 500 501 snprintf(octeon_system_type, sizeof(octeon_system_type), "%s (%s)", 502 board_type, octeon_model_get_string(read_c0_prid())); 503 } 504 505 /** 506 * Return a string representing the system type 507 * 508 * Returns 509 */ 510 const char *octeon_board_type_string(void) 511 { 512 return octeon_system_type; 513 } 514 515 const char *get_system_type(void) 516 __attribute__ ((alias("octeon_board_type_string"))); 517 518 void octeon_user_io_init(void) 519 { 520 union octeon_cvmemctl cvmmemctl; 521 522 /* Get the current settings for CP0_CVMMEMCTL_REG */ 523 cvmmemctl.u64 = read_c0_cvmmemctl(); 524 /* R/W If set, marked write-buffer entries time out the same 525 * as as other entries; if clear, marked write-buffer entries 526 * use the maximum timeout. */ 527 cvmmemctl.s.dismarkwblongto = 1; 528 /* R/W If set, a merged store does not clear the write-buffer 529 * entry timeout state. */ 530 cvmmemctl.s.dismrgclrwbto = 0; 531 /* R/W Two bits that are the MSBs of the resultant CVMSEG LM 532 * word location for an IOBDMA. The other 8 bits come from the 533 * SCRADDR field of the IOBDMA. */ 534 cvmmemctl.s.iobdmascrmsb = 0; 535 /* R/W If set, SYNCWS and SYNCS only order marked stores; if 536 * clear, SYNCWS and SYNCS only order unmarked 537 * stores. SYNCWSMARKED has no effect when DISSYNCWS is 538 * set. */ 539 cvmmemctl.s.syncwsmarked = 0; 540 /* R/W If set, SYNCWS acts as SYNCW and SYNCS acts as SYNC. */ 541 cvmmemctl.s.dissyncws = 0; 542 /* R/W If set, no stall happens on write buffer full. */ 543 if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2)) 544 cvmmemctl.s.diswbfst = 1; 545 else 546 cvmmemctl.s.diswbfst = 0; 547 /* R/W If set (and SX set), supervisor-level loads/stores can 548 * use XKPHYS addresses with <48>==0 */ 549 cvmmemctl.s.xkmemenas = 0; 550 551 /* R/W If set (and UX set), user-level loads/stores can use 552 * XKPHYS addresses with VA<48>==0 */ 553 cvmmemctl.s.xkmemenau = 0; 554 555 /* R/W If set (and SX set), supervisor-level loads/stores can 556 * use XKPHYS addresses with VA<48>==1 */ 557 cvmmemctl.s.xkioenas = 0; 558 559 /* R/W If set (and UX set), user-level loads/stores can use 560 * XKPHYS addresses with VA<48>==1 */ 561 cvmmemctl.s.xkioenau = 0; 562 563 /* R/W If set, all stores act as SYNCW (NOMERGE must be set 564 * when this is set) RW, reset to 0. */ 565 cvmmemctl.s.allsyncw = 0; 566 567 /* R/W If set, no stores merge, and all stores reach the 568 * coherent bus in order. */ 569 cvmmemctl.s.nomerge = 0; 570 /* R/W Selects the bit in the counter used for DID time-outs 0 571 * = 231, 1 = 230, 2 = 229, 3 = 214. Actual time-out is 572 * between 1x and 2x this interval. For example, with 573 * DIDTTO=3, expiration interval is between 16K and 32K. */ 574 cvmmemctl.s.didtto = 0; 575 /* R/W If set, the (mem) CSR clock never turns off. */ 576 cvmmemctl.s.csrckalwys = 0; 577 /* R/W If set, mclk never turns off. */ 578 cvmmemctl.s.mclkalwys = 0; 579 /* R/W Selects the bit in the counter used for write buffer 580 * flush time-outs (WBFLT+11) is the bit position in an 581 * internal counter used to determine expiration. The write 582 * buffer expires between 1x and 2x this interval. For 583 * example, with WBFLT = 0, a write buffer expires between 2K 584 * and 4K cycles after the write buffer entry is allocated. */ 585 cvmmemctl.s.wbfltime = 0; 586 /* R/W If set, do not put Istream in the L2 cache. */ 587 cvmmemctl.s.istrnol2 = 0; 588 589 /* 590 * R/W The write buffer threshold. As per erratum Core-14752 591 * for CN63XX, a sc/scd might fail if the write buffer is 592 * full. Lowering WBTHRESH greatly lowers the chances of the 593 * write buffer ever being full and triggering the erratum. 594 */ 595 if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X)) 596 cvmmemctl.s.wbthresh = 4; 597 else 598 cvmmemctl.s.wbthresh = 10; 599 600 /* R/W If set, CVMSEG is available for loads/stores in 601 * kernel/debug mode. */ 602 #if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0 603 cvmmemctl.s.cvmsegenak = 1; 604 #else 605 cvmmemctl.s.cvmsegenak = 0; 606 #endif 607 /* R/W If set, CVMSEG is available for loads/stores in 608 * supervisor mode. */ 609 cvmmemctl.s.cvmsegenas = 0; 610 /* R/W If set, CVMSEG is available for loads/stores in user 611 * mode. */ 612 cvmmemctl.s.cvmsegenau = 0; 613 614 write_c0_cvmmemctl(cvmmemctl.u64); 615 616 /* Setup of CVMSEG is done in kernel-entry-init.h */ 617 if (smp_processor_id() == 0) 618 pr_notice("CVMSEG size: %d cache lines (%d bytes)\n", 619 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE, 620 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128); 621 622 if (octeon_has_feature(OCTEON_FEATURE_FAU)) { 623 union cvmx_iob_fau_timeout fau_timeout; 624 625 /* Set a default for the hardware timeouts */ 626 fau_timeout.u64 = 0; 627 fau_timeout.s.tout_val = 0xfff; 628 /* Disable tagwait FAU timeout */ 629 fau_timeout.s.tout_enb = 0; 630 cvmx_write_csr(CVMX_IOB_FAU_TIMEOUT, fau_timeout.u64); 631 } 632 633 if ((!OCTEON_IS_MODEL(OCTEON_CN68XX) && 634 !OCTEON_IS_MODEL(OCTEON_CN7XXX)) || 635 OCTEON_IS_MODEL(OCTEON_CN70XX)) { 636 union cvmx_pow_nw_tim nm_tim; 637 638 nm_tim.u64 = 0; 639 /* 4096 cycles */ 640 nm_tim.s.nw_tim = 3; 641 cvmx_write_csr(CVMX_POW_NW_TIM, nm_tim.u64); 642 } 643 644 write_octeon_c0_icacheerr(0); 645 write_c0_derraddr1(0); 646 } 647 648 /** 649 * Early entry point for arch setup 650 */ 651 void __init prom_init(void) 652 { 653 struct cvmx_sysinfo *sysinfo; 654 const char *arg; 655 char *p; 656 int i; 657 u64 t; 658 int argc; 659 #ifdef CONFIG_CAVIUM_RESERVE32 660 int64_t addr = -1; 661 #endif 662 /* 663 * The bootloader passes a pointer to the boot descriptor in 664 * $a3, this is available as fw_arg3. 665 */ 666 octeon_boot_desc_ptr = (struct octeon_boot_descriptor *)fw_arg3; 667 octeon_bootinfo = 668 cvmx_phys_to_ptr(octeon_boot_desc_ptr->cvmx_desc_vaddr); 669 cvmx_bootmem_init(cvmx_phys_to_ptr(octeon_bootinfo->phy_mem_desc_addr)); 670 671 sysinfo = cvmx_sysinfo_get(); 672 memset(sysinfo, 0, sizeof(*sysinfo)); 673 sysinfo->system_dram_size = octeon_bootinfo->dram_size << 20; 674 sysinfo->phy_mem_desc_addr = (u64)phys_to_virt(octeon_bootinfo->phy_mem_desc_addr); 675 676 if ((octeon_bootinfo->major_version > 1) || 677 (octeon_bootinfo->major_version == 1 && 678 octeon_bootinfo->minor_version >= 4)) 679 cvmx_coremask_copy(&sysinfo->core_mask, 680 &octeon_bootinfo->ext_core_mask); 681 else 682 cvmx_coremask_set64(&sysinfo->core_mask, 683 octeon_bootinfo->core_mask); 684 685 /* Some broken u-boot pass garbage in upper bits, clear them out */ 686 if (!OCTEON_IS_MODEL(OCTEON_CN78XX)) 687 for (i = 512; i < 1024; i++) 688 cvmx_coremask_clear_core(&sysinfo->core_mask, i); 689 690 sysinfo->exception_base_addr = octeon_bootinfo->exception_base_addr; 691 sysinfo->cpu_clock_hz = octeon_bootinfo->eclock_hz; 692 sysinfo->dram_data_rate_hz = octeon_bootinfo->dclock_hz * 2; 693 sysinfo->board_type = octeon_bootinfo->board_type; 694 sysinfo->board_rev_major = octeon_bootinfo->board_rev_major; 695 sysinfo->board_rev_minor = octeon_bootinfo->board_rev_minor; 696 memcpy(sysinfo->mac_addr_base, octeon_bootinfo->mac_addr_base, 697 sizeof(sysinfo->mac_addr_base)); 698 sysinfo->mac_addr_count = octeon_bootinfo->mac_addr_count; 699 memcpy(sysinfo->board_serial_number, 700 octeon_bootinfo->board_serial_number, 701 sizeof(sysinfo->board_serial_number)); 702 sysinfo->compact_flash_common_base_addr = 703 octeon_bootinfo->compact_flash_common_base_addr; 704 sysinfo->compact_flash_attribute_base_addr = 705 octeon_bootinfo->compact_flash_attribute_base_addr; 706 sysinfo->led_display_base_addr = octeon_bootinfo->led_display_base_addr; 707 sysinfo->dfa_ref_clock_hz = octeon_bootinfo->dfa_ref_clock_hz; 708 sysinfo->bootloader_config_flags = octeon_bootinfo->config_flags; 709 710 if (OCTEON_IS_OCTEON2()) { 711 /* I/O clock runs at a different rate than the CPU. */ 712 union cvmx_mio_rst_boot rst_boot; 713 rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT); 714 octeon_io_clock_rate = 50000000 * rst_boot.s.pnr_mul; 715 } else if (OCTEON_IS_OCTEON3()) { 716 /* I/O clock runs at a different rate than the CPU. */ 717 union cvmx_rst_boot rst_boot; 718 rst_boot.u64 = cvmx_read_csr(CVMX_RST_BOOT); 719 octeon_io_clock_rate = 50000000 * rst_boot.s.pnr_mul; 720 } else { 721 octeon_io_clock_rate = sysinfo->cpu_clock_hz; 722 } 723 724 t = read_c0_cvmctl(); 725 if ((t & (1ull << 27)) == 0) { 726 /* 727 * Setup the multiplier save/restore code if 728 * CvmCtl[NOMUL] clear. 729 */ 730 void *save; 731 void *save_end; 732 void *restore; 733 void *restore_end; 734 int save_len; 735 int restore_len; 736 int save_max = (char *)octeon_mult_save_end - 737 (char *)octeon_mult_save; 738 int restore_max = (char *)octeon_mult_restore_end - 739 (char *)octeon_mult_restore; 740 if (current_cpu_data.cputype == CPU_CAVIUM_OCTEON3) { 741 save = octeon_mult_save3; 742 save_end = octeon_mult_save3_end; 743 restore = octeon_mult_restore3; 744 restore_end = octeon_mult_restore3_end; 745 } else { 746 save = octeon_mult_save2; 747 save_end = octeon_mult_save2_end; 748 restore = octeon_mult_restore2; 749 restore_end = octeon_mult_restore2_end; 750 } 751 save_len = (char *)save_end - (char *)save; 752 restore_len = (char *)restore_end - (char *)restore; 753 if (!WARN_ON(save_len > save_max || 754 restore_len > restore_max)) { 755 memcpy(octeon_mult_save, save, save_len); 756 memcpy(octeon_mult_restore, restore, restore_len); 757 } 758 } 759 760 /* 761 * Only enable the LED controller if we're running on a CN38XX, CN58XX, 762 * or CN56XX. The CN30XX and CN31XX don't have an LED controller. 763 */ 764 if (!octeon_is_simulation() && 765 octeon_has_feature(OCTEON_FEATURE_LED_CONTROLLER)) { 766 cvmx_write_csr(CVMX_LED_EN, 0); 767 cvmx_write_csr(CVMX_LED_PRT, 0); 768 cvmx_write_csr(CVMX_LED_DBG, 0); 769 cvmx_write_csr(CVMX_LED_PRT_FMT, 0); 770 cvmx_write_csr(CVMX_LED_UDD_CNTX(0), 32); 771 cvmx_write_csr(CVMX_LED_UDD_CNTX(1), 32); 772 cvmx_write_csr(CVMX_LED_UDD_DATX(0), 0); 773 cvmx_write_csr(CVMX_LED_UDD_DATX(1), 0); 774 cvmx_write_csr(CVMX_LED_EN, 1); 775 } 776 #ifdef CONFIG_CAVIUM_RESERVE32 777 /* 778 * We need to temporarily allocate all memory in the reserve32 779 * region. This makes sure the kernel doesn't allocate this 780 * memory when it is getting memory from the 781 * bootloader. Later, after the memory allocations are 782 * complete, the reserve32 will be freed. 783 * 784 * Allocate memory for RESERVED32 aligned on 2MB boundary. This 785 * is in case we later use hugetlb entries with it. 786 */ 787 addr = cvmx_bootmem_phy_named_block_alloc(CONFIG_CAVIUM_RESERVE32 << 20, 788 0, 0, 2 << 20, 789 "CAVIUM_RESERVE32", 0); 790 if (addr < 0) 791 pr_err("Failed to allocate CAVIUM_RESERVE32 memory area\n"); 792 else 793 octeon_reserve32_memory = addr; 794 #endif 795 796 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2 797 if (cvmx_read_csr(CVMX_L2D_FUS3) & (3ull << 34)) { 798 pr_info("Skipping L2 locking due to reduced L2 cache size\n"); 799 } else { 800 uint32_t __maybe_unused ebase = read_c0_ebase() & 0x3ffff000; 801 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_TLB 802 /* TLB refill */ 803 cvmx_l2c_lock_mem_region(ebase, 0x100); 804 #endif 805 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_EXCEPTION 806 /* General exception */ 807 cvmx_l2c_lock_mem_region(ebase + 0x180, 0x80); 808 #endif 809 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT 810 /* Interrupt handler */ 811 cvmx_l2c_lock_mem_region(ebase + 0x200, 0x80); 812 #endif 813 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_INTERRUPT 814 cvmx_l2c_lock_mem_region(__pa_symbol(handle_int), 0x100); 815 cvmx_l2c_lock_mem_region(__pa_symbol(plat_irq_dispatch), 0x80); 816 #endif 817 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_MEMCPY 818 cvmx_l2c_lock_mem_region(__pa_symbol(memcpy), 0x480); 819 #endif 820 } 821 #endif 822 823 octeon_check_cpu_bist(); 824 825 octeon_uart = octeon_get_boot_uart(); 826 827 #ifdef CONFIG_SMP 828 octeon_write_lcd("LinuxSMP"); 829 #else 830 octeon_write_lcd("Linux"); 831 #endif 832 833 octeon_setup_delays(); 834 835 /* 836 * BIST should always be enabled when doing a soft reset. L2 837 * Cache locking for instance is not cleared unless BIST is 838 * enabled. Unfortunately due to a chip errata G-200 for 839 * Cn38XX and CN31XX, BIST msut be disabled on these parts. 840 */ 841 if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2) || 842 OCTEON_IS_MODEL(OCTEON_CN31XX)) 843 cvmx_write_csr(CVMX_CIU_SOFT_BIST, 0); 844 else 845 cvmx_write_csr(CVMX_CIU_SOFT_BIST, 1); 846 847 /* Default to 64MB in the simulator to speed things up */ 848 if (octeon_is_simulation()) 849 MAX_MEMORY = 64ull << 20; 850 851 arg = strstr(arcs_cmdline, "mem="); 852 if (arg) { 853 MAX_MEMORY = memparse(arg + 4, &p); 854 if (MAX_MEMORY == 0) 855 MAX_MEMORY = 32ull << 30; 856 if (*p == '@') 857 RESERVE_LOW_MEM = memparse(p + 1, &p); 858 } 859 860 arcs_cmdline[0] = 0; 861 argc = octeon_boot_desc_ptr->argc; 862 for (i = 0; i < argc; i++) { 863 const char *arg = 864 cvmx_phys_to_ptr(octeon_boot_desc_ptr->argv[i]); 865 if ((strncmp(arg, "MEM=", 4) == 0) || 866 (strncmp(arg, "mem=", 4) == 0)) { 867 MAX_MEMORY = memparse(arg + 4, &p); 868 if (MAX_MEMORY == 0) 869 MAX_MEMORY = 32ull << 30; 870 if (*p == '@') 871 RESERVE_LOW_MEM = memparse(p + 1, &p); 872 #ifdef CONFIG_KEXEC 873 } else if (strncmp(arg, "crashkernel=", 12) == 0) { 874 crashk_size = memparse(arg+12, &p); 875 if (*p == '@') 876 crashk_base = memparse(p+1, &p); 877 strcat(arcs_cmdline, " "); 878 strcat(arcs_cmdline, arg); 879 /* 880 * To do: switch parsing to new style, something like: 881 * parse_crashkernel(arg, sysinfo->system_dram_size, 882 * &crashk_size, &crashk_base); 883 */ 884 #endif 885 } else if (strlen(arcs_cmdline) + strlen(arg) + 1 < 886 sizeof(arcs_cmdline) - 1) { 887 strcat(arcs_cmdline, " "); 888 strcat(arcs_cmdline, arg); 889 } 890 } 891 892 if (strstr(arcs_cmdline, "console=") == NULL) { 893 #ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL 894 strcat(arcs_cmdline, " console=ttyS0,115200"); 895 #else 896 if (octeon_uart == 1) 897 strcat(arcs_cmdline, " console=ttyS1,115200"); 898 else 899 strcat(arcs_cmdline, " console=ttyS0,115200"); 900 #endif 901 } 902 903 mips_hpt_frequency = octeon_get_clock_rate(); 904 905 octeon_init_cvmcount(); 906 907 _machine_restart = octeon_restart; 908 _machine_halt = octeon_halt; 909 910 #ifdef CONFIG_KEXEC 911 _machine_kexec_shutdown = octeon_shutdown; 912 _machine_crash_shutdown = octeon_crash_shutdown; 913 _machine_kexec_prepare = octeon_kexec_prepare; 914 #endif 915 916 octeon_user_io_init(); 917 octeon_setup_smp(); 918 } 919 920 /* Exclude a single page from the regions obtained in plat_mem_setup. */ 921 #ifndef CONFIG_CRASH_DUMP 922 static __init void memory_exclude_page(u64 addr, u64 *mem, u64 *size) 923 { 924 if (addr > *mem && addr < *mem + *size) { 925 u64 inc = addr - *mem; 926 add_memory_region(*mem, inc, BOOT_MEM_RAM); 927 *mem += inc; 928 *size -= inc; 929 } 930 931 if (addr == *mem && *size > PAGE_SIZE) { 932 *mem += PAGE_SIZE; 933 *size -= PAGE_SIZE; 934 } 935 } 936 #endif /* CONFIG_CRASH_DUMP */ 937 938 void __init plat_mem_setup(void) 939 { 940 uint64_t mem_alloc_size; 941 uint64_t total; 942 uint64_t crashk_end; 943 #ifndef CONFIG_CRASH_DUMP 944 int64_t memory; 945 uint64_t kernel_start; 946 uint64_t kernel_size; 947 #endif 948 949 total = 0; 950 crashk_end = 0; 951 952 /* 953 * The Mips memory init uses the first memory location for 954 * some memory vectors. When SPARSEMEM is in use, it doesn't 955 * verify that the size is big enough for the final 956 * vectors. Making the smallest chuck 4MB seems to be enough 957 * to consistently work. 958 */ 959 mem_alloc_size = 4 << 20; 960 if (mem_alloc_size > MAX_MEMORY) 961 mem_alloc_size = MAX_MEMORY; 962 963 /* Crashkernel ignores bootmem list. It relies on mem=X@Y option */ 964 #ifdef CONFIG_CRASH_DUMP 965 add_memory_region(RESERVE_LOW_MEM, MAX_MEMORY, BOOT_MEM_RAM); 966 total += MAX_MEMORY; 967 #else 968 #ifdef CONFIG_KEXEC 969 if (crashk_size > 0) { 970 add_memory_region(crashk_base, crashk_size, BOOT_MEM_RAM); 971 crashk_end = crashk_base + crashk_size; 972 } 973 #endif 974 /* 975 * When allocating memory, we want incrementing addresses from 976 * bootmem_alloc so the code in add_memory_region can merge 977 * regions next to each other. 978 */ 979 cvmx_bootmem_lock(); 980 while ((boot_mem_map.nr_map < BOOT_MEM_MAP_MAX) 981 && (total < MAX_MEMORY)) { 982 memory = cvmx_bootmem_phy_alloc(mem_alloc_size, 983 __pa_symbol(&_end), -1, 984 0x100000, 985 CVMX_BOOTMEM_FLAG_NO_LOCKING); 986 if (memory >= 0) { 987 u64 size = mem_alloc_size; 988 #ifdef CONFIG_KEXEC 989 uint64_t end; 990 #endif 991 992 /* 993 * exclude a page at the beginning and end of 994 * the 256MB PCIe 'hole' so the kernel will not 995 * try to allocate multi-page buffers that 996 * span the discontinuity. 997 */ 998 memory_exclude_page(CVMX_PCIE_BAR1_PHYS_BASE, 999 &memory, &size); 1000 memory_exclude_page(CVMX_PCIE_BAR1_PHYS_BASE + 1001 CVMX_PCIE_BAR1_PHYS_SIZE, 1002 &memory, &size); 1003 #ifdef CONFIG_KEXEC 1004 end = memory + mem_alloc_size; 1005 1006 /* 1007 * This function automatically merges address regions 1008 * next to each other if they are received in 1009 * incrementing order 1010 */ 1011 if (memory < crashk_base && end > crashk_end) { 1012 /* region is fully in */ 1013 add_memory_region(memory, 1014 crashk_base - memory, 1015 BOOT_MEM_RAM); 1016 total += crashk_base - memory; 1017 add_memory_region(crashk_end, 1018 end - crashk_end, 1019 BOOT_MEM_RAM); 1020 total += end - crashk_end; 1021 continue; 1022 } 1023 1024 if (memory >= crashk_base && end <= crashk_end) 1025 /* 1026 * Entire memory region is within the new 1027 * kernel's memory, ignore it. 1028 */ 1029 continue; 1030 1031 if (memory > crashk_base && memory < crashk_end && 1032 end > crashk_end) { 1033 /* 1034 * Overlap with the beginning of the region, 1035 * reserve the beginning. 1036 */ 1037 mem_alloc_size -= crashk_end - memory; 1038 memory = crashk_end; 1039 } else if (memory < crashk_base && end > crashk_base && 1040 end < crashk_end) 1041 /* 1042 * Overlap with the beginning of the region, 1043 * chop of end. 1044 */ 1045 mem_alloc_size -= end - crashk_base; 1046 #endif 1047 add_memory_region(memory, mem_alloc_size, BOOT_MEM_RAM); 1048 total += mem_alloc_size; 1049 /* Recovering mem_alloc_size */ 1050 mem_alloc_size = 4 << 20; 1051 } else { 1052 break; 1053 } 1054 } 1055 cvmx_bootmem_unlock(); 1056 /* Add the memory region for the kernel. */ 1057 kernel_start = (unsigned long) _text; 1058 kernel_size = _end - _text; 1059 1060 /* Adjust for physical offset. */ 1061 kernel_start &= ~0xffffffff80000000ULL; 1062 add_memory_region(kernel_start, kernel_size, BOOT_MEM_RAM); 1063 #endif /* CONFIG_CRASH_DUMP */ 1064 1065 #ifdef CONFIG_CAVIUM_RESERVE32 1066 /* 1067 * Now that we've allocated the kernel memory it is safe to 1068 * free the reserved region. We free it here so that builtin 1069 * drivers can use the memory. 1070 */ 1071 if (octeon_reserve32_memory) 1072 cvmx_bootmem_free_named("CAVIUM_RESERVE32"); 1073 #endif /* CONFIG_CAVIUM_RESERVE32 */ 1074 1075 if (total == 0) 1076 panic("Unable to allocate memory from " 1077 "cvmx_bootmem_phy_alloc"); 1078 } 1079 1080 /* 1081 * Emit one character to the boot UART. Exported for use by the 1082 * watchdog timer. 1083 */ 1084 int prom_putchar(char c) 1085 { 1086 uint64_t lsrval; 1087 1088 /* Spin until there is room */ 1089 do { 1090 lsrval = cvmx_read_csr(CVMX_MIO_UARTX_LSR(octeon_uart)); 1091 } while ((lsrval & 0x20) == 0); 1092 1093 /* Write the byte */ 1094 cvmx_write_csr(CVMX_MIO_UARTX_THR(octeon_uart), c & 0xffull); 1095 return 1; 1096 } 1097 EXPORT_SYMBOL(prom_putchar); 1098 1099 void __init prom_free_prom_memory(void) 1100 { 1101 if (CAVIUM_OCTEON_DCACHE_PREFETCH_WAR) { 1102 /* Check for presence of Core-14449 fix. */ 1103 u32 insn; 1104 u32 *foo; 1105 1106 foo = &insn; 1107 1108 asm volatile("# before" : : : "memory"); 1109 prefetch(foo); 1110 asm volatile( 1111 ".set push\n\t" 1112 ".set noreorder\n\t" 1113 "bal 1f\n\t" 1114 "nop\n" 1115 "1:\tlw %0,-12($31)\n\t" 1116 ".set pop\n\t" 1117 : "=r" (insn) : : "$31", "memory"); 1118 1119 if ((insn >> 26) != 0x33) 1120 panic("No PREF instruction at Core-14449 probe point."); 1121 1122 if (((insn >> 16) & 0x1f) != 28) 1123 panic("OCTEON II DCache prefetch workaround not in place (%04x).\n" 1124 "Please build kernel with proper options (CONFIG_CAVIUM_CN63XXP1).", 1125 insn); 1126 } 1127 } 1128 1129 void __init octeon_fill_mac_addresses(void); 1130 int octeon_prune_device_tree(void); 1131 1132 extern const char __appended_dtb; 1133 extern const char __dtb_octeon_3xxx_begin; 1134 extern const char __dtb_octeon_68xx_begin; 1135 void __init device_tree_init(void) 1136 { 1137 const void *fdt; 1138 bool do_prune; 1139 bool fill_mac; 1140 1141 #ifdef CONFIG_MIPS_ELF_APPENDED_DTB 1142 if (!fdt_check_header(&__appended_dtb)) { 1143 fdt = &__appended_dtb; 1144 do_prune = false; 1145 fill_mac = true; 1146 pr_info("Using appended Device Tree.\n"); 1147 } else 1148 #endif 1149 if (octeon_bootinfo->minor_version >= 3 && octeon_bootinfo->fdt_addr) { 1150 fdt = phys_to_virt(octeon_bootinfo->fdt_addr); 1151 if (fdt_check_header(fdt)) 1152 panic("Corrupt Device Tree passed to kernel."); 1153 do_prune = false; 1154 fill_mac = false; 1155 pr_info("Using passed Device Tree.\n"); 1156 } else if (OCTEON_IS_MODEL(OCTEON_CN68XX)) { 1157 fdt = &__dtb_octeon_68xx_begin; 1158 do_prune = true; 1159 fill_mac = true; 1160 } else { 1161 fdt = &__dtb_octeon_3xxx_begin; 1162 do_prune = true; 1163 fill_mac = true; 1164 } 1165 1166 initial_boot_params = (void *)fdt; 1167 1168 if (do_prune) { 1169 octeon_prune_device_tree(); 1170 pr_info("Using internal Device Tree.\n"); 1171 } 1172 if (fill_mac) 1173 octeon_fill_mac_addresses(); 1174 unflatten_and_copy_device_tree(); 1175 init_octeon_system_type(); 1176 } 1177 1178 static int __initdata disable_octeon_edac_p; 1179 1180 static int __init disable_octeon_edac(char *str) 1181 { 1182 disable_octeon_edac_p = 1; 1183 return 0; 1184 } 1185 early_param("disable_octeon_edac", disable_octeon_edac); 1186 1187 static char *edac_device_names[] = { 1188 "octeon_l2c_edac", 1189 "octeon_pc_edac", 1190 }; 1191 1192 static int __init edac_devinit(void) 1193 { 1194 struct platform_device *dev; 1195 int i, err = 0; 1196 int num_lmc; 1197 char *name; 1198 1199 if (disable_octeon_edac_p) 1200 return 0; 1201 1202 for (i = 0; i < ARRAY_SIZE(edac_device_names); i++) { 1203 name = edac_device_names[i]; 1204 dev = platform_device_register_simple(name, -1, NULL, 0); 1205 if (IS_ERR(dev)) { 1206 pr_err("Registration of %s failed!\n", name); 1207 err = PTR_ERR(dev); 1208 } 1209 } 1210 1211 num_lmc = OCTEON_IS_MODEL(OCTEON_CN68XX) ? 4 : 1212 (OCTEON_IS_MODEL(OCTEON_CN56XX) ? 2 : 1); 1213 for (i = 0; i < num_lmc; i++) { 1214 dev = platform_device_register_simple("octeon_lmc_edac", 1215 i, NULL, 0); 1216 if (IS_ERR(dev)) { 1217 pr_err("Registration of octeon_lmc_edac %d failed!\n", i); 1218 err = PTR_ERR(dev); 1219 } 1220 } 1221 1222 return err; 1223 } 1224 device_initcall(edac_devinit); 1225 1226 static void __initdata *octeon_dummy_iospace; 1227 1228 static int __init octeon_no_pci_init(void) 1229 { 1230 /* 1231 * Initially assume there is no PCI. The PCI/PCIe platform code will 1232 * later re-initialize these to correct values if they are present. 1233 */ 1234 octeon_dummy_iospace = vzalloc(IO_SPACE_LIMIT); 1235 set_io_port_base((unsigned long)octeon_dummy_iospace); 1236 ioport_resource.start = MAX_RESOURCE; 1237 ioport_resource.end = 0; 1238 return 0; 1239 } 1240 core_initcall(octeon_no_pci_init); 1241 1242 static int __init octeon_no_pci_release(void) 1243 { 1244 /* 1245 * Release the allocated memory if a real IO space is there. 1246 */ 1247 if ((unsigned long)octeon_dummy_iospace != mips_io_port_base) 1248 vfree(octeon_dummy_iospace); 1249 return 0; 1250 } 1251 late_initcall(octeon_no_pci_release); 1252