1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2004-2017 Cavium, Inc. 7 * Copyright (C) 2008 Wind River Systems 8 */ 9 10 #include <linux/etherdevice.h> 11 #include <linux/of.h> 12 #include <linux/of_platform.h> 13 #include <linux/of_fdt.h> 14 #include <linux/platform_device.h> 15 #include <linux/libfdt.h> 16 17 #include <asm/octeon/octeon.h> 18 #include <asm/octeon/cvmx-helper-board.h> 19 20 #ifdef CONFIG_USB 21 #include <linux/usb/ehci_def.h> 22 #include <linux/usb/ehci_pdriver.h> 23 #include <linux/usb/ohci_pdriver.h> 24 #include <asm/octeon/cvmx-uctlx-defs.h> 25 26 #define CVMX_UAHCX_EHCI_USBCMD (CVMX_ADD_IO_SEG(0x00016F0000000010ull)) 27 #define CVMX_UAHCX_OHCI_USBCMD (CVMX_ADD_IO_SEG(0x00016F0000000408ull)) 28 29 static DEFINE_MUTEX(octeon2_usb_clocks_mutex); 30 31 static int octeon2_usb_clock_start_cnt; 32 33 static int __init octeon2_usb_reset(void) 34 { 35 union cvmx_uctlx_clk_rst_ctl clk_rst_ctl; 36 u32 ucmd; 37 38 if (!OCTEON_IS_OCTEON2()) 39 return 0; 40 41 clk_rst_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_CLK_RST_CTL(0)); 42 if (clk_rst_ctl.s.hrst) { 43 ucmd = cvmx_read64_uint32(CVMX_UAHCX_EHCI_USBCMD); 44 ucmd &= ~CMD_RUN; 45 cvmx_write64_uint32(CVMX_UAHCX_EHCI_USBCMD, ucmd); 46 mdelay(2); 47 ucmd |= CMD_RESET; 48 cvmx_write64_uint32(CVMX_UAHCX_EHCI_USBCMD, ucmd); 49 ucmd = cvmx_read64_uint32(CVMX_UAHCX_OHCI_USBCMD); 50 ucmd |= CMD_RUN; 51 cvmx_write64_uint32(CVMX_UAHCX_OHCI_USBCMD, ucmd); 52 } 53 54 return 0; 55 } 56 arch_initcall(octeon2_usb_reset); 57 58 static void octeon2_usb_clocks_start(struct device *dev) 59 { 60 u64 div; 61 union cvmx_uctlx_if_ena if_ena; 62 union cvmx_uctlx_clk_rst_ctl clk_rst_ctl; 63 union cvmx_uctlx_uphy_portx_ctl_status port_ctl_status; 64 int i; 65 unsigned long io_clk_64_to_ns; 66 u32 clock_rate = 12000000; 67 bool is_crystal_clock = false; 68 69 70 mutex_lock(&octeon2_usb_clocks_mutex); 71 72 octeon2_usb_clock_start_cnt++; 73 if (octeon2_usb_clock_start_cnt != 1) 74 goto exit; 75 76 io_clk_64_to_ns = 64000000000ull / octeon_get_io_clock_rate(); 77 78 if (dev->of_node) { 79 struct device_node *uctl_node; 80 const char *clock_type; 81 82 uctl_node = of_get_parent(dev->of_node); 83 if (!uctl_node) { 84 dev_err(dev, "No UCTL device node\n"); 85 goto exit; 86 } 87 i = of_property_read_u32(uctl_node, 88 "refclk-frequency", &clock_rate); 89 if (i) { 90 dev_err(dev, "No UCTL \"refclk-frequency\"\n"); 91 of_node_put(uctl_node); 92 goto exit; 93 } 94 i = of_property_read_string(uctl_node, 95 "refclk-type", &clock_type); 96 of_node_put(uctl_node); 97 if (!i && strcmp("crystal", clock_type) == 0) 98 is_crystal_clock = true; 99 } 100 101 /* 102 * Step 1: Wait for voltages stable. That surely happened 103 * before starting the kernel. 104 * 105 * Step 2: Enable SCLK of UCTL by writing UCTL0_IF_ENA[EN] = 1 106 */ 107 if_ena.u64 = 0; 108 if_ena.s.en = 1; 109 cvmx_write_csr(CVMX_UCTLX_IF_ENA(0), if_ena.u64); 110 111 for (i = 0; i <= 1; i++) { 112 port_ctl_status.u64 = 113 cvmx_read_csr(CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(i, 0)); 114 /* Set txvreftune to 15 to obtain compliant 'eye' diagram. */ 115 port_ctl_status.s.txvreftune = 15; 116 port_ctl_status.s.txrisetune = 1; 117 port_ctl_status.s.txpreemphasistune = 1; 118 cvmx_write_csr(CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(i, 0), 119 port_ctl_status.u64); 120 } 121 122 /* Step 3: Configure the reference clock, PHY, and HCLK */ 123 clk_rst_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_CLK_RST_CTL(0)); 124 125 /* 126 * If the UCTL looks like it has already been started, skip 127 * the initialization, otherwise bus errors are obtained. 128 */ 129 if (clk_rst_ctl.s.hrst) 130 goto end_clock; 131 /* 3a */ 132 clk_rst_ctl.s.p_por = 1; 133 clk_rst_ctl.s.hrst = 0; 134 clk_rst_ctl.s.p_prst = 0; 135 clk_rst_ctl.s.h_clkdiv_rst = 0; 136 clk_rst_ctl.s.o_clkdiv_rst = 0; 137 clk_rst_ctl.s.h_clkdiv_en = 0; 138 clk_rst_ctl.s.o_clkdiv_en = 0; 139 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); 140 141 /* 3b */ 142 clk_rst_ctl.s.p_refclk_sel = is_crystal_clock ? 0 : 1; 143 switch (clock_rate) { 144 default: 145 pr_err("Invalid UCTL clock rate of %u, using 12000000 instead\n", 146 clock_rate); 147 fallthrough; 148 case 12000000: 149 clk_rst_ctl.s.p_refclk_div = 0; 150 break; 151 case 24000000: 152 clk_rst_ctl.s.p_refclk_div = 1; 153 break; 154 case 48000000: 155 clk_rst_ctl.s.p_refclk_div = 2; 156 break; 157 } 158 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); 159 160 /* 3c */ 161 div = octeon_get_io_clock_rate() / 130000000ull; 162 163 switch (div) { 164 case 0: 165 div = 1; 166 break; 167 case 1: 168 case 2: 169 case 3: 170 case 4: 171 break; 172 case 5: 173 div = 4; 174 break; 175 case 6: 176 case 7: 177 div = 6; 178 break; 179 case 8: 180 case 9: 181 case 10: 182 case 11: 183 div = 8; 184 break; 185 default: 186 div = 12; 187 break; 188 } 189 clk_rst_ctl.s.h_div = div; 190 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); 191 /* Read it back, */ 192 clk_rst_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_CLK_RST_CTL(0)); 193 clk_rst_ctl.s.h_clkdiv_en = 1; 194 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); 195 /* 3d */ 196 clk_rst_ctl.s.h_clkdiv_rst = 1; 197 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); 198 199 /* 3e: delay 64 io clocks */ 200 ndelay(io_clk_64_to_ns); 201 202 /* 203 * Step 4: Program the power-on reset field in the UCTL 204 * clock-reset-control register. 205 */ 206 clk_rst_ctl.s.p_por = 0; 207 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); 208 209 /* Step 5: Wait 3 ms for the PHY clock to start. */ 210 mdelay(3); 211 212 /* Steps 6..9 for ATE only, are skipped. */ 213 214 /* Step 10: Configure the OHCI_CLK48 and OHCI_CLK12 clocks. */ 215 /* 10a */ 216 clk_rst_ctl.s.o_clkdiv_rst = 1; 217 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); 218 219 /* 10b */ 220 clk_rst_ctl.s.o_clkdiv_en = 1; 221 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); 222 223 /* 10c */ 224 ndelay(io_clk_64_to_ns); 225 226 /* 227 * Step 11: Program the PHY reset field: 228 * UCTL0_CLK_RST_CTL[P_PRST] = 1 229 */ 230 clk_rst_ctl.s.p_prst = 1; 231 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); 232 233 /* Step 11b */ 234 udelay(1); 235 236 /* Step 11c */ 237 clk_rst_ctl.s.p_prst = 0; 238 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); 239 240 /* Step 11d */ 241 mdelay(1); 242 243 /* Step 11e */ 244 clk_rst_ctl.s.p_prst = 1; 245 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); 246 247 /* Step 12: Wait 1 uS. */ 248 udelay(1); 249 250 /* Step 13: Program the HRESET_N field: UCTL0_CLK_RST_CTL[HRST] = 1 */ 251 clk_rst_ctl.s.hrst = 1; 252 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); 253 254 end_clock: 255 /* Set uSOF cycle period to 60,000 bits. */ 256 cvmx_write_csr(CVMX_UCTLX_EHCI_FLA(0), 0x20ull); 257 258 exit: 259 mutex_unlock(&octeon2_usb_clocks_mutex); 260 } 261 262 static void octeon2_usb_clocks_stop(void) 263 { 264 mutex_lock(&octeon2_usb_clocks_mutex); 265 octeon2_usb_clock_start_cnt--; 266 mutex_unlock(&octeon2_usb_clocks_mutex); 267 } 268 269 static int octeon_ehci_power_on(struct platform_device *pdev) 270 { 271 octeon2_usb_clocks_start(&pdev->dev); 272 return 0; 273 } 274 275 static void octeon_ehci_power_off(struct platform_device *pdev) 276 { 277 octeon2_usb_clocks_stop(); 278 } 279 280 static struct usb_ehci_pdata octeon_ehci_pdata = { 281 /* Octeon EHCI matches CPU endianness. */ 282 #ifdef __BIG_ENDIAN 283 .big_endian_mmio = 1, 284 #endif 285 /* 286 * We can DMA from anywhere. But the descriptors must be in 287 * the lower 4GB. 288 */ 289 .dma_mask_64 = 0, 290 .power_on = octeon_ehci_power_on, 291 .power_off = octeon_ehci_power_off, 292 }; 293 294 static void __init octeon_ehci_hw_start(struct device *dev) 295 { 296 union cvmx_uctlx_ehci_ctl ehci_ctl; 297 298 octeon2_usb_clocks_start(dev); 299 300 ehci_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_EHCI_CTL(0)); 301 /* Use 64-bit addressing. */ 302 ehci_ctl.s.ehci_64b_addr_en = 1; 303 ehci_ctl.s.l2c_addr_msb = 0; 304 #ifdef __BIG_ENDIAN 305 ehci_ctl.s.l2c_buff_emod = 1; /* Byte swapped. */ 306 ehci_ctl.s.l2c_desc_emod = 1; /* Byte swapped. */ 307 #else 308 ehci_ctl.s.l2c_buff_emod = 0; /* not swapped. */ 309 ehci_ctl.s.l2c_desc_emod = 0; /* not swapped. */ 310 ehci_ctl.s.inv_reg_a2 = 1; 311 #endif 312 cvmx_write_csr(CVMX_UCTLX_EHCI_CTL(0), ehci_ctl.u64); 313 314 octeon2_usb_clocks_stop(); 315 } 316 317 static int __init octeon_ehci_device_init(void) 318 { 319 struct platform_device *pd; 320 struct device_node *ehci_node; 321 int ret = 0; 322 323 ehci_node = of_find_node_by_name(NULL, "ehci"); 324 if (!ehci_node) 325 return 0; 326 327 pd = of_find_device_by_node(ehci_node); 328 of_node_put(ehci_node); 329 if (!pd) 330 return 0; 331 332 pd->dev.platform_data = &octeon_ehci_pdata; 333 octeon_ehci_hw_start(&pd->dev); 334 put_device(&pd->dev); 335 336 return ret; 337 } 338 device_initcall(octeon_ehci_device_init); 339 340 static int octeon_ohci_power_on(struct platform_device *pdev) 341 { 342 octeon2_usb_clocks_start(&pdev->dev); 343 return 0; 344 } 345 346 static void octeon_ohci_power_off(struct platform_device *pdev) 347 { 348 octeon2_usb_clocks_stop(); 349 } 350 351 static struct usb_ohci_pdata octeon_ohci_pdata = { 352 /* Octeon OHCI matches CPU endianness. */ 353 #ifdef __BIG_ENDIAN 354 .big_endian_mmio = 1, 355 #endif 356 .power_on = octeon_ohci_power_on, 357 .power_off = octeon_ohci_power_off, 358 }; 359 360 static void __init octeon_ohci_hw_start(struct device *dev) 361 { 362 union cvmx_uctlx_ohci_ctl ohci_ctl; 363 364 octeon2_usb_clocks_start(dev); 365 366 ohci_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_OHCI_CTL(0)); 367 ohci_ctl.s.l2c_addr_msb = 0; 368 #ifdef __BIG_ENDIAN 369 ohci_ctl.s.l2c_buff_emod = 1; /* Byte swapped. */ 370 ohci_ctl.s.l2c_desc_emod = 1; /* Byte swapped. */ 371 #else 372 ohci_ctl.s.l2c_buff_emod = 0; /* not swapped. */ 373 ohci_ctl.s.l2c_desc_emod = 0; /* not swapped. */ 374 ohci_ctl.s.inv_reg_a2 = 1; 375 #endif 376 cvmx_write_csr(CVMX_UCTLX_OHCI_CTL(0), ohci_ctl.u64); 377 378 octeon2_usb_clocks_stop(); 379 } 380 381 static int __init octeon_ohci_device_init(void) 382 { 383 struct platform_device *pd; 384 struct device_node *ohci_node; 385 int ret = 0; 386 387 ohci_node = of_find_node_by_name(NULL, "ohci"); 388 if (!ohci_node) 389 return 0; 390 391 pd = of_find_device_by_node(ohci_node); 392 of_node_put(ohci_node); 393 if (!pd) 394 return 0; 395 396 pd->dev.platform_data = &octeon_ohci_pdata; 397 octeon_ohci_hw_start(&pd->dev); 398 put_device(&pd->dev); 399 400 return ret; 401 } 402 device_initcall(octeon_ohci_device_init); 403 404 #endif /* CONFIG_USB */ 405 406 /* Octeon Random Number Generator. */ 407 static int __init octeon_rng_device_init(void) 408 { 409 struct platform_device *pd; 410 int ret = 0; 411 412 struct resource rng_resources[] = { 413 { 414 .flags = IORESOURCE_MEM, 415 .start = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS), 416 .end = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS) + 0xf 417 }, { 418 .flags = IORESOURCE_MEM, 419 .start = cvmx_build_io_address(8, 0), 420 .end = cvmx_build_io_address(8, 0) + 0x7 421 } 422 }; 423 424 pd = platform_device_alloc("octeon_rng", -1); 425 if (!pd) { 426 ret = -ENOMEM; 427 goto out; 428 } 429 430 ret = platform_device_add_resources(pd, rng_resources, 431 ARRAY_SIZE(rng_resources)); 432 if (ret) 433 goto fail; 434 435 ret = platform_device_add(pd); 436 if (ret) 437 goto fail; 438 439 return ret; 440 fail: 441 platform_device_put(pd); 442 443 out: 444 return ret; 445 } 446 device_initcall(octeon_rng_device_init); 447 448 static const struct of_device_id octeon_ids[] __initconst = { 449 { .compatible = "simple-bus", }, 450 { .compatible = "cavium,octeon-6335-uctl", }, 451 { .compatible = "cavium,octeon-5750-usbn", }, 452 { .compatible = "cavium,octeon-3860-bootbus", }, 453 { .compatible = "cavium,mdio-mux", }, 454 { .compatible = "gpio-leds", }, 455 { .compatible = "cavium,octeon-7130-usb-uctl", }, 456 {}, 457 }; 458 459 static bool __init octeon_has_88e1145(void) 460 { 461 return !OCTEON_IS_MODEL(OCTEON_CN52XX) && 462 !OCTEON_IS_MODEL(OCTEON_CN6XXX) && 463 !OCTEON_IS_MODEL(OCTEON_CN56XX); 464 } 465 466 static bool __init octeon_has_fixed_link(int ipd_port) 467 { 468 switch (cvmx_sysinfo_get()->board_type) { 469 case CVMX_BOARD_TYPE_CN3005_EVB_HS5: 470 case CVMX_BOARD_TYPE_CN3010_EVB_HS5: 471 case CVMX_BOARD_TYPE_CN3020_EVB_HS5: 472 case CVMX_BOARD_TYPE_CUST_NB5: 473 case CVMX_BOARD_TYPE_EBH3100: 474 /* Port 1 on these boards is always gigabit. */ 475 return ipd_port == 1; 476 case CVMX_BOARD_TYPE_BBGW_REF: 477 /* Ports 0 and 1 connect to the switch. */ 478 return ipd_port == 0 || ipd_port == 1; 479 } 480 return false; 481 } 482 483 static void __init octeon_fdt_set_phy(int eth, int phy_addr) 484 { 485 const __be32 *phy_handle; 486 const __be32 *alt_phy_handle; 487 const __be32 *reg; 488 u32 phandle; 489 int phy; 490 int alt_phy; 491 const char *p; 492 int current_len; 493 char new_name[20]; 494 495 phy_handle = fdt_getprop(initial_boot_params, eth, "phy-handle", NULL); 496 if (!phy_handle) 497 return; 498 499 phandle = be32_to_cpup(phy_handle); 500 phy = fdt_node_offset_by_phandle(initial_boot_params, phandle); 501 502 alt_phy_handle = fdt_getprop(initial_boot_params, eth, "cavium,alt-phy-handle", NULL); 503 if (alt_phy_handle) { 504 u32 alt_phandle = be32_to_cpup(alt_phy_handle); 505 506 alt_phy = fdt_node_offset_by_phandle(initial_boot_params, alt_phandle); 507 } else { 508 alt_phy = -1; 509 } 510 511 if (phy_addr < 0 || phy < 0) { 512 /* Delete the PHY things */ 513 fdt_nop_property(initial_boot_params, eth, "phy-handle"); 514 /* This one may fail */ 515 fdt_nop_property(initial_boot_params, eth, "cavium,alt-phy-handle"); 516 if (phy >= 0) 517 fdt_nop_node(initial_boot_params, phy); 518 if (alt_phy >= 0) 519 fdt_nop_node(initial_boot_params, alt_phy); 520 return; 521 } 522 523 if (phy_addr >= 256 && alt_phy > 0) { 524 const struct fdt_property *phy_prop; 525 struct fdt_property *alt_prop; 526 fdt32_t phy_handle_name; 527 528 /* Use the alt phy node instead.*/ 529 phy_prop = fdt_get_property(initial_boot_params, eth, "phy-handle", NULL); 530 phy_handle_name = phy_prop->nameoff; 531 fdt_nop_node(initial_boot_params, phy); 532 fdt_nop_property(initial_boot_params, eth, "phy-handle"); 533 alt_prop = fdt_get_property_w(initial_boot_params, eth, "cavium,alt-phy-handle", NULL); 534 alt_prop->nameoff = phy_handle_name; 535 phy = alt_phy; 536 } 537 538 phy_addr &= 0xff; 539 540 if (octeon_has_88e1145()) { 541 fdt_nop_property(initial_boot_params, phy, "marvell,reg-init"); 542 memset(new_name, 0, sizeof(new_name)); 543 strcpy(new_name, "marvell,88e1145"); 544 p = fdt_getprop(initial_boot_params, phy, "compatible", 545 ¤t_len); 546 if (p && current_len >= strlen(new_name)) 547 fdt_setprop_inplace(initial_boot_params, phy, 548 "compatible", new_name, current_len); 549 } 550 551 reg = fdt_getprop(initial_boot_params, phy, "reg", NULL); 552 if (phy_addr == be32_to_cpup(reg)) 553 return; 554 555 fdt_setprop_inplace_cell(initial_boot_params, phy, "reg", phy_addr); 556 557 snprintf(new_name, sizeof(new_name), "ethernet-phy@%x", phy_addr); 558 559 p = fdt_get_name(initial_boot_params, phy, ¤t_len); 560 if (p && current_len == strlen(new_name)) 561 fdt_set_name(initial_boot_params, phy, new_name); 562 else 563 pr_err("Error: could not rename ethernet phy: <%s>", p); 564 } 565 566 static void __init octeon_fdt_set_mac_addr(int n, u64 *pmac) 567 { 568 const u8 *old_mac; 569 int old_len; 570 u8 new_mac[6]; 571 u64 mac = *pmac; 572 int r; 573 574 old_mac = fdt_getprop(initial_boot_params, n, "local-mac-address", 575 &old_len); 576 if (!old_mac || old_len != 6 || is_valid_ether_addr(old_mac)) 577 return; 578 579 new_mac[0] = (mac >> 40) & 0xff; 580 new_mac[1] = (mac >> 32) & 0xff; 581 new_mac[2] = (mac >> 24) & 0xff; 582 new_mac[3] = (mac >> 16) & 0xff; 583 new_mac[4] = (mac >> 8) & 0xff; 584 new_mac[5] = mac & 0xff; 585 586 r = fdt_setprop_inplace(initial_boot_params, n, "local-mac-address", 587 new_mac, sizeof(new_mac)); 588 589 if (r) { 590 pr_err("Setting \"local-mac-address\" failed %d", r); 591 return; 592 } 593 *pmac = mac + 1; 594 } 595 596 static void __init octeon_fdt_rm_ethernet(int node) 597 { 598 const __be32 *phy_handle; 599 600 phy_handle = fdt_getprop(initial_boot_params, node, "phy-handle", NULL); 601 if (phy_handle) { 602 u32 ph = be32_to_cpup(phy_handle); 603 int p = fdt_node_offset_by_phandle(initial_boot_params, ph); 604 605 if (p >= 0) 606 fdt_nop_node(initial_boot_params, p); 607 } 608 fdt_nop_node(initial_boot_params, node); 609 } 610 611 static void __init _octeon_rx_tx_delay(int eth, int rx_delay, int tx_delay) 612 { 613 fdt_setprop_inplace_cell(initial_boot_params, eth, "rx-delay", 614 rx_delay); 615 fdt_setprop_inplace_cell(initial_boot_params, eth, "tx-delay", 616 tx_delay); 617 } 618 619 static void __init octeon_rx_tx_delay(int eth, int iface, int port) 620 { 621 switch (cvmx_sysinfo_get()->board_type) { 622 case CVMX_BOARD_TYPE_CN3005_EVB_HS5: 623 if (iface == 0) { 624 if (port == 0) { 625 /* 626 * Boards with gigabit WAN ports need a 627 * different setting that is compatible with 628 * 100 Mbit settings 629 */ 630 _octeon_rx_tx_delay(eth, 0xc, 0x0c); 631 return; 632 } else if (port == 1) { 633 /* Different config for switch port. */ 634 _octeon_rx_tx_delay(eth, 0x0, 0x0); 635 return; 636 } 637 } 638 break; 639 case CVMX_BOARD_TYPE_UBNT_E100: 640 if (iface == 0 && port <= 2) { 641 _octeon_rx_tx_delay(eth, 0x0, 0x10); 642 return; 643 } 644 break; 645 } 646 fdt_nop_property(initial_boot_params, eth, "rx-delay"); 647 fdt_nop_property(initial_boot_params, eth, "tx-delay"); 648 } 649 650 static void __init octeon_fdt_pip_port(int iface, int i, int p, int max) 651 { 652 char name_buffer[20]; 653 int eth; 654 int phy_addr; 655 int ipd_port; 656 int fixed_link; 657 658 snprintf(name_buffer, sizeof(name_buffer), "ethernet@%x", p); 659 eth = fdt_subnode_offset(initial_boot_params, iface, name_buffer); 660 if (eth < 0) 661 return; 662 if (p > max) { 663 pr_debug("Deleting port %x:%x\n", i, p); 664 octeon_fdt_rm_ethernet(eth); 665 return; 666 } 667 if (OCTEON_IS_MODEL(OCTEON_CN68XX)) 668 ipd_port = (0x100 * i) + (0x10 * p) + 0x800; 669 else 670 ipd_port = 16 * i + p; 671 672 phy_addr = cvmx_helper_board_get_mii_address(ipd_port); 673 octeon_fdt_set_phy(eth, phy_addr); 674 675 fixed_link = fdt_subnode_offset(initial_boot_params, eth, "fixed-link"); 676 if (fixed_link < 0) 677 WARN_ON(octeon_has_fixed_link(ipd_port)); 678 else if (!octeon_has_fixed_link(ipd_port)) 679 fdt_nop_node(initial_boot_params, fixed_link); 680 octeon_rx_tx_delay(eth, i, p); 681 } 682 683 static void __init octeon_fdt_pip_iface(int pip, int idx) 684 { 685 char name_buffer[20]; 686 int iface; 687 int p; 688 int count = 0; 689 690 snprintf(name_buffer, sizeof(name_buffer), "interface@%d", idx); 691 iface = fdt_subnode_offset(initial_boot_params, pip, name_buffer); 692 if (iface < 0) 693 return; 694 695 if (cvmx_helper_interface_enumerate(idx) == 0) 696 count = cvmx_helper_ports_on_interface(idx); 697 698 for (p = 0; p < 16; p++) 699 octeon_fdt_pip_port(iface, idx, p, count - 1); 700 } 701 702 void __init octeon_fill_mac_addresses(void) 703 { 704 const char *alias_prop; 705 char name_buffer[20]; 706 u64 mac_addr_base; 707 int aliases; 708 int pip; 709 int i; 710 711 aliases = fdt_path_offset(initial_boot_params, "/aliases"); 712 if (aliases < 0) 713 return; 714 715 mac_addr_base = 716 ((octeon_bootinfo->mac_addr_base[0] & 0xffull)) << 40 | 717 ((octeon_bootinfo->mac_addr_base[1] & 0xffull)) << 32 | 718 ((octeon_bootinfo->mac_addr_base[2] & 0xffull)) << 24 | 719 ((octeon_bootinfo->mac_addr_base[3] & 0xffull)) << 16 | 720 ((octeon_bootinfo->mac_addr_base[4] & 0xffull)) << 8 | 721 (octeon_bootinfo->mac_addr_base[5] & 0xffull); 722 723 for (i = 0; i < 2; i++) { 724 int mgmt; 725 726 snprintf(name_buffer, sizeof(name_buffer), "mix%d", i); 727 alias_prop = fdt_getprop(initial_boot_params, aliases, 728 name_buffer, NULL); 729 if (!alias_prop) 730 continue; 731 mgmt = fdt_path_offset(initial_boot_params, alias_prop); 732 if (mgmt < 0) 733 continue; 734 octeon_fdt_set_mac_addr(mgmt, &mac_addr_base); 735 } 736 737 alias_prop = fdt_getprop(initial_boot_params, aliases, "pip", NULL); 738 if (!alias_prop) 739 return; 740 741 pip = fdt_path_offset(initial_boot_params, alias_prop); 742 if (pip < 0) 743 return; 744 745 for (i = 0; i <= 4; i++) { 746 int iface; 747 int p; 748 749 snprintf(name_buffer, sizeof(name_buffer), "interface@%d", i); 750 iface = fdt_subnode_offset(initial_boot_params, pip, 751 name_buffer); 752 if (iface < 0) 753 continue; 754 for (p = 0; p < 16; p++) { 755 int eth; 756 757 snprintf(name_buffer, sizeof(name_buffer), 758 "ethernet@%x", p); 759 eth = fdt_subnode_offset(initial_boot_params, iface, 760 name_buffer); 761 if (eth < 0) 762 continue; 763 octeon_fdt_set_mac_addr(eth, &mac_addr_base); 764 } 765 } 766 } 767 768 int __init octeon_prune_device_tree(void) 769 { 770 int i, max_port, uart_mask; 771 const char *pip_path; 772 const char *alias_prop; 773 char name_buffer[20]; 774 int aliases; 775 776 if (fdt_check_header(initial_boot_params)) 777 panic("Corrupt Device Tree."); 778 779 WARN(octeon_bootinfo->board_type == CVMX_BOARD_TYPE_CUST_DSR1000N, 780 "Built-in DTB booting is deprecated on %s. Please switch to use appended DTB.", 781 cvmx_board_type_to_string(octeon_bootinfo->board_type)); 782 783 aliases = fdt_path_offset(initial_boot_params, "/aliases"); 784 if (aliases < 0) { 785 pr_err("Error: No /aliases node in device tree."); 786 return -EINVAL; 787 } 788 789 if (OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)) 790 max_port = 2; 791 else if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)) 792 max_port = 1; 793 else 794 max_port = 0; 795 796 if (octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC10E) 797 max_port = 0; 798 799 for (i = 0; i < 2; i++) { 800 int mgmt; 801 802 snprintf(name_buffer, sizeof(name_buffer), 803 "mix%d", i); 804 alias_prop = fdt_getprop(initial_boot_params, aliases, 805 name_buffer, NULL); 806 if (alias_prop) { 807 mgmt = fdt_path_offset(initial_boot_params, alias_prop); 808 if (mgmt < 0) 809 continue; 810 if (i >= max_port) { 811 pr_debug("Deleting mix%d\n", i); 812 octeon_fdt_rm_ethernet(mgmt); 813 fdt_nop_property(initial_boot_params, aliases, 814 name_buffer); 815 } else { 816 int phy_addr = cvmx_helper_board_get_mii_address(CVMX_HELPER_BOARD_MGMT_IPD_PORT + i); 817 818 octeon_fdt_set_phy(mgmt, phy_addr); 819 } 820 } 821 } 822 823 pip_path = fdt_getprop(initial_boot_params, aliases, "pip", NULL); 824 if (pip_path) { 825 int pip = fdt_path_offset(initial_boot_params, pip_path); 826 827 if (pip >= 0) 828 for (i = 0; i <= 4; i++) 829 octeon_fdt_pip_iface(pip, i); 830 } 831 832 /* I2C */ 833 if (OCTEON_IS_MODEL(OCTEON_CN52XX) || 834 OCTEON_IS_MODEL(OCTEON_CN63XX) || 835 OCTEON_IS_MODEL(OCTEON_CN68XX) || 836 OCTEON_IS_MODEL(OCTEON_CN56XX)) 837 max_port = 2; 838 else 839 max_port = 1; 840 841 for (i = 0; i < 2; i++) { 842 int i2c; 843 844 snprintf(name_buffer, sizeof(name_buffer), 845 "twsi%d", i); 846 alias_prop = fdt_getprop(initial_boot_params, aliases, 847 name_buffer, NULL); 848 849 if (alias_prop) { 850 i2c = fdt_path_offset(initial_boot_params, alias_prop); 851 if (i2c < 0) 852 continue; 853 if (i >= max_port) { 854 pr_debug("Deleting twsi%d\n", i); 855 fdt_nop_node(initial_boot_params, i2c); 856 fdt_nop_property(initial_boot_params, aliases, 857 name_buffer); 858 } 859 } 860 } 861 862 /* SMI/MDIO */ 863 if (OCTEON_IS_MODEL(OCTEON_CN68XX)) 864 max_port = 4; 865 else if (OCTEON_IS_MODEL(OCTEON_CN52XX) || 866 OCTEON_IS_MODEL(OCTEON_CN63XX) || 867 OCTEON_IS_MODEL(OCTEON_CN56XX)) 868 max_port = 2; 869 else 870 max_port = 1; 871 872 for (i = 0; i < 2; i++) { 873 int i2c; 874 875 snprintf(name_buffer, sizeof(name_buffer), 876 "smi%d", i); 877 alias_prop = fdt_getprop(initial_boot_params, aliases, 878 name_buffer, NULL); 879 if (alias_prop) { 880 i2c = fdt_path_offset(initial_boot_params, alias_prop); 881 if (i2c < 0) 882 continue; 883 if (i >= max_port) { 884 pr_debug("Deleting smi%d\n", i); 885 fdt_nop_node(initial_boot_params, i2c); 886 fdt_nop_property(initial_boot_params, aliases, 887 name_buffer); 888 } 889 } 890 } 891 892 /* Serial */ 893 uart_mask = 3; 894 895 /* Right now CN52XX is the only chip with a third uart */ 896 if (OCTEON_IS_MODEL(OCTEON_CN52XX)) 897 uart_mask |= 4; /* uart2 */ 898 899 for (i = 0; i < 3; i++) { 900 int uart; 901 902 snprintf(name_buffer, sizeof(name_buffer), 903 "uart%d", i); 904 alias_prop = fdt_getprop(initial_boot_params, aliases, 905 name_buffer, NULL); 906 907 if (alias_prop) { 908 uart = fdt_path_offset(initial_boot_params, alias_prop); 909 if (uart_mask & (1 << i)) { 910 __be32 f; 911 912 f = cpu_to_be32(octeon_get_io_clock_rate()); 913 fdt_setprop_inplace(initial_boot_params, 914 uart, "clock-frequency", 915 &f, sizeof(f)); 916 continue; 917 } 918 pr_debug("Deleting uart%d\n", i); 919 fdt_nop_node(initial_boot_params, uart); 920 fdt_nop_property(initial_boot_params, aliases, 921 name_buffer); 922 } 923 } 924 925 /* Compact Flash */ 926 alias_prop = fdt_getprop(initial_boot_params, aliases, 927 "cf0", NULL); 928 if (alias_prop) { 929 union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg; 930 unsigned long base_ptr, region_base, region_size; 931 unsigned long region1_base = 0; 932 unsigned long region1_size = 0; 933 int cs, bootbus; 934 bool is_16bit = false; 935 bool is_true_ide = false; 936 __be32 new_reg[6]; 937 __be32 *ranges; 938 int len; 939 940 int cf = fdt_path_offset(initial_boot_params, alias_prop); 941 942 base_ptr = 0; 943 if (octeon_bootinfo->major_version == 1 944 && octeon_bootinfo->minor_version >= 1) { 945 if (octeon_bootinfo->compact_flash_common_base_addr) 946 base_ptr = octeon_bootinfo->compact_flash_common_base_addr; 947 } else { 948 base_ptr = 0x1d000800; 949 } 950 951 if (!base_ptr) 952 goto no_cf; 953 954 /* Find CS0 region. */ 955 for (cs = 0; cs < 8; cs++) { 956 mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs)); 957 region_base = mio_boot_reg_cfg.s.base << 16; 958 region_size = (mio_boot_reg_cfg.s.size + 1) << 16; 959 if (mio_boot_reg_cfg.s.en && base_ptr >= region_base 960 && base_ptr < region_base + region_size) { 961 is_16bit = mio_boot_reg_cfg.s.width; 962 break; 963 } 964 } 965 if (cs >= 7) { 966 /* cs and cs + 1 are CS0 and CS1, both must be less than 8. */ 967 goto no_cf; 968 } 969 970 if (!(base_ptr & 0xfffful)) { 971 /* 972 * Boot loader signals availability of DMA (true_ide 973 * mode) by setting low order bits of base_ptr to 974 * zero. 975 */ 976 977 /* Asume that CS1 immediately follows. */ 978 mio_boot_reg_cfg.u64 = 979 cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs + 1)); 980 region1_base = mio_boot_reg_cfg.s.base << 16; 981 region1_size = (mio_boot_reg_cfg.s.size + 1) << 16; 982 if (!mio_boot_reg_cfg.s.en) 983 goto no_cf; 984 is_true_ide = true; 985 986 } else { 987 fdt_nop_property(initial_boot_params, cf, "cavium,true-ide"); 988 fdt_nop_property(initial_boot_params, cf, "cavium,dma-engine-handle"); 989 if (!is_16bit) { 990 __be32 width = cpu_to_be32(8); 991 992 fdt_setprop_inplace(initial_boot_params, cf, 993 "cavium,bus-width", &width, sizeof(width)); 994 } 995 } 996 new_reg[0] = cpu_to_be32(cs); 997 new_reg[1] = cpu_to_be32(0); 998 new_reg[2] = cpu_to_be32(0x10000); 999 new_reg[3] = cpu_to_be32(cs + 1); 1000 new_reg[4] = cpu_to_be32(0); 1001 new_reg[5] = cpu_to_be32(0x10000); 1002 fdt_setprop_inplace(initial_boot_params, cf, 1003 "reg", new_reg, sizeof(new_reg)); 1004 1005 bootbus = fdt_parent_offset(initial_boot_params, cf); 1006 if (bootbus < 0) 1007 goto no_cf; 1008 ranges = fdt_getprop_w(initial_boot_params, bootbus, "ranges", &len); 1009 if (!ranges || len < (5 * 8 * sizeof(__be32))) 1010 goto no_cf; 1011 1012 ranges[(cs * 5) + 2] = cpu_to_be32(region_base >> 32); 1013 ranges[(cs * 5) + 3] = cpu_to_be32(region_base & 0xffffffff); 1014 ranges[(cs * 5) + 4] = cpu_to_be32(region_size); 1015 if (is_true_ide) { 1016 cs++; 1017 ranges[(cs * 5) + 2] = cpu_to_be32(region1_base >> 32); 1018 ranges[(cs * 5) + 3] = cpu_to_be32(region1_base & 0xffffffff); 1019 ranges[(cs * 5) + 4] = cpu_to_be32(region1_size); 1020 } 1021 goto end_cf; 1022 no_cf: 1023 fdt_nop_node(initial_boot_params, cf); 1024 1025 end_cf: 1026 ; 1027 } 1028 1029 /* 8 char LED */ 1030 alias_prop = fdt_getprop(initial_boot_params, aliases, 1031 "led0", NULL); 1032 if (alias_prop) { 1033 union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg; 1034 unsigned long base_ptr, region_base, region_size; 1035 int cs, bootbus; 1036 __be32 new_reg[6]; 1037 __be32 *ranges; 1038 int len; 1039 int led = fdt_path_offset(initial_boot_params, alias_prop); 1040 1041 base_ptr = octeon_bootinfo->led_display_base_addr; 1042 if (base_ptr == 0) 1043 goto no_led; 1044 /* Find CS0 region. */ 1045 for (cs = 0; cs < 8; cs++) { 1046 mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs)); 1047 region_base = mio_boot_reg_cfg.s.base << 16; 1048 region_size = (mio_boot_reg_cfg.s.size + 1) << 16; 1049 if (mio_boot_reg_cfg.s.en && base_ptr >= region_base 1050 && base_ptr < region_base + region_size) 1051 break; 1052 } 1053 1054 if (cs > 7) 1055 goto no_led; 1056 1057 new_reg[0] = cpu_to_be32(cs); 1058 new_reg[1] = cpu_to_be32(0x20); 1059 new_reg[2] = cpu_to_be32(0x20); 1060 new_reg[3] = cpu_to_be32(cs); 1061 new_reg[4] = cpu_to_be32(0); 1062 new_reg[5] = cpu_to_be32(0x20); 1063 fdt_setprop_inplace(initial_boot_params, led, 1064 "reg", new_reg, sizeof(new_reg)); 1065 1066 bootbus = fdt_parent_offset(initial_boot_params, led); 1067 if (bootbus < 0) 1068 goto no_led; 1069 ranges = fdt_getprop_w(initial_boot_params, bootbus, "ranges", &len); 1070 if (!ranges || len < (5 * 8 * sizeof(__be32))) 1071 goto no_led; 1072 1073 ranges[(cs * 5) + 2] = cpu_to_be32(region_base >> 32); 1074 ranges[(cs * 5) + 3] = cpu_to_be32(region_base & 0xffffffff); 1075 ranges[(cs * 5) + 4] = cpu_to_be32(region_size); 1076 goto end_led; 1077 1078 no_led: 1079 fdt_nop_node(initial_boot_params, led); 1080 end_led: 1081 ; 1082 } 1083 1084 #ifdef CONFIG_USB 1085 /* OHCI/UHCI USB */ 1086 alias_prop = fdt_getprop(initial_boot_params, aliases, 1087 "uctl", NULL); 1088 if (alias_prop) { 1089 int uctl = fdt_path_offset(initial_boot_params, alias_prop); 1090 1091 if (uctl >= 0 && (!OCTEON_IS_MODEL(OCTEON_CN6XXX) || 1092 octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC2E)) { 1093 pr_debug("Deleting uctl\n"); 1094 fdt_nop_node(initial_boot_params, uctl); 1095 fdt_nop_property(initial_boot_params, aliases, "uctl"); 1096 } else if (octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC10E || 1097 octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC4E) { 1098 /* Missing "refclk-type" defaults to crystal. */ 1099 fdt_nop_property(initial_boot_params, uctl, "refclk-type"); 1100 } 1101 } 1102 1103 /* DWC2 USB */ 1104 alias_prop = fdt_getprop(initial_boot_params, aliases, 1105 "usbn", NULL); 1106 if (alias_prop) { 1107 int usbn = fdt_path_offset(initial_boot_params, alias_prop); 1108 1109 if (usbn >= 0 && (current_cpu_type() == CPU_CAVIUM_OCTEON2 || 1110 !octeon_has_feature(OCTEON_FEATURE_USB))) { 1111 pr_debug("Deleting usbn\n"); 1112 fdt_nop_node(initial_boot_params, usbn); 1113 fdt_nop_property(initial_boot_params, aliases, "usbn"); 1114 } else { 1115 __be32 new_f[1]; 1116 enum cvmx_helper_board_usb_clock_types c; 1117 1118 c = __cvmx_helper_board_usb_get_clock_type(); 1119 switch (c) { 1120 case USB_CLOCK_TYPE_REF_48: 1121 new_f[0] = cpu_to_be32(48000000); 1122 fdt_setprop_inplace(initial_boot_params, usbn, 1123 "refclk-frequency", new_f, sizeof(new_f)); 1124 fallthrough; 1125 case USB_CLOCK_TYPE_REF_12: 1126 /* Missing "refclk-type" defaults to external. */ 1127 fdt_nop_property(initial_boot_params, usbn, "refclk-type"); 1128 break; 1129 default: 1130 break; 1131 } 1132 } 1133 } 1134 #endif 1135 1136 return 0; 1137 } 1138 1139 static int __init octeon_publish_devices(void) 1140 { 1141 return of_platform_populate(NULL, octeon_ids, NULL, NULL); 1142 } 1143 arch_initcall(octeon_publish_devices); 1144