1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2004-2016 Cavium Networks 7 * Copyright (C) 2008 Wind River Systems 8 */ 9 10 #include <linux/init.h> 11 #include <linux/delay.h> 12 #include <linux/etherdevice.h> 13 #include <linux/of_platform.h> 14 #include <linux/of_fdt.h> 15 #include <linux/libfdt.h> 16 #include <linux/usb/ehci_def.h> 17 #include <linux/usb/ehci_pdriver.h> 18 #include <linux/usb/ohci_pdriver.h> 19 20 #include <asm/octeon/octeon.h> 21 #include <asm/octeon/cvmx-helper-board.h> 22 #include <asm/octeon/cvmx-uctlx-defs.h> 23 24 #define CVMX_UAHCX_EHCI_USBCMD (CVMX_ADD_IO_SEG(0x00016F0000000010ull)) 25 #define CVMX_UAHCX_OHCI_USBCMD (CVMX_ADD_IO_SEG(0x00016F0000000408ull)) 26 27 /* Octeon Random Number Generator. */ 28 static int __init octeon_rng_device_init(void) 29 { 30 struct platform_device *pd; 31 int ret = 0; 32 33 struct resource rng_resources[] = { 34 { 35 .flags = IORESOURCE_MEM, 36 .start = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS), 37 .end = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS) + 0xf 38 }, { 39 .flags = IORESOURCE_MEM, 40 .start = cvmx_build_io_address(8, 0), 41 .end = cvmx_build_io_address(8, 0) + 0x7 42 } 43 }; 44 45 pd = platform_device_alloc("octeon_rng", -1); 46 if (!pd) { 47 ret = -ENOMEM; 48 goto out; 49 } 50 51 ret = platform_device_add_resources(pd, rng_resources, 52 ARRAY_SIZE(rng_resources)); 53 if (ret) 54 goto fail; 55 56 ret = platform_device_add(pd); 57 if (ret) 58 goto fail; 59 60 return ret; 61 fail: 62 platform_device_put(pd); 63 64 out: 65 return ret; 66 } 67 device_initcall(octeon_rng_device_init); 68 69 #ifdef CONFIG_USB 70 71 static DEFINE_MUTEX(octeon2_usb_clocks_mutex); 72 73 static int octeon2_usb_clock_start_cnt; 74 75 static int __init octeon2_usb_reset(void) 76 { 77 union cvmx_uctlx_clk_rst_ctl clk_rst_ctl; 78 u32 ucmd; 79 80 if (!OCTEON_IS_OCTEON2()) 81 return 0; 82 83 clk_rst_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_CLK_RST_CTL(0)); 84 if (clk_rst_ctl.s.hrst) { 85 ucmd = cvmx_read64_uint32(CVMX_UAHCX_EHCI_USBCMD); 86 ucmd &= ~CMD_RUN; 87 cvmx_write64_uint32(CVMX_UAHCX_EHCI_USBCMD, ucmd); 88 mdelay(2); 89 ucmd |= CMD_RESET; 90 cvmx_write64_uint32(CVMX_UAHCX_EHCI_USBCMD, ucmd); 91 ucmd = cvmx_read64_uint32(CVMX_UAHCX_OHCI_USBCMD); 92 ucmd |= CMD_RUN; 93 cvmx_write64_uint32(CVMX_UAHCX_OHCI_USBCMD, ucmd); 94 } 95 96 return 0; 97 } 98 arch_initcall(octeon2_usb_reset); 99 100 static void octeon2_usb_clocks_start(struct device *dev) 101 { 102 u64 div; 103 union cvmx_uctlx_if_ena if_ena; 104 union cvmx_uctlx_clk_rst_ctl clk_rst_ctl; 105 union cvmx_uctlx_uphy_portx_ctl_status port_ctl_status; 106 int i; 107 unsigned long io_clk_64_to_ns; 108 u32 clock_rate = 12000000; 109 bool is_crystal_clock = false; 110 111 112 mutex_lock(&octeon2_usb_clocks_mutex); 113 114 octeon2_usb_clock_start_cnt++; 115 if (octeon2_usb_clock_start_cnt != 1) 116 goto exit; 117 118 io_clk_64_to_ns = 64000000000ull / octeon_get_io_clock_rate(); 119 120 if (dev->of_node) { 121 struct device_node *uctl_node; 122 const char *clock_type; 123 124 uctl_node = of_get_parent(dev->of_node); 125 if (!uctl_node) { 126 dev_err(dev, "No UCTL device node\n"); 127 goto exit; 128 } 129 i = of_property_read_u32(uctl_node, 130 "refclk-frequency", &clock_rate); 131 if (i) { 132 dev_err(dev, "No UCTL \"refclk-frequency\"\n"); 133 goto exit; 134 } 135 i = of_property_read_string(uctl_node, 136 "refclk-type", &clock_type); 137 138 if (!i && strcmp("crystal", clock_type) == 0) 139 is_crystal_clock = true; 140 } 141 142 /* 143 * Step 1: Wait for voltages stable. That surely happened 144 * before starting the kernel. 145 * 146 * Step 2: Enable SCLK of UCTL by writing UCTL0_IF_ENA[EN] = 1 147 */ 148 if_ena.u64 = 0; 149 if_ena.s.en = 1; 150 cvmx_write_csr(CVMX_UCTLX_IF_ENA(0), if_ena.u64); 151 152 for (i = 0; i <= 1; i++) { 153 port_ctl_status.u64 = 154 cvmx_read_csr(CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(i, 0)); 155 /* Set txvreftune to 15 to obtain compliant 'eye' diagram. */ 156 port_ctl_status.s.txvreftune = 15; 157 port_ctl_status.s.txrisetune = 1; 158 port_ctl_status.s.txpreemphasistune = 1; 159 cvmx_write_csr(CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(i, 0), 160 port_ctl_status.u64); 161 } 162 163 /* Step 3: Configure the reference clock, PHY, and HCLK */ 164 clk_rst_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_CLK_RST_CTL(0)); 165 166 /* 167 * If the UCTL looks like it has already been started, skip 168 * the initialization, otherwise bus errors are obtained. 169 */ 170 if (clk_rst_ctl.s.hrst) 171 goto end_clock; 172 /* 3a */ 173 clk_rst_ctl.s.p_por = 1; 174 clk_rst_ctl.s.hrst = 0; 175 clk_rst_ctl.s.p_prst = 0; 176 clk_rst_ctl.s.h_clkdiv_rst = 0; 177 clk_rst_ctl.s.o_clkdiv_rst = 0; 178 clk_rst_ctl.s.h_clkdiv_en = 0; 179 clk_rst_ctl.s.o_clkdiv_en = 0; 180 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); 181 182 /* 3b */ 183 clk_rst_ctl.s.p_refclk_sel = is_crystal_clock ? 0 : 1; 184 switch (clock_rate) { 185 default: 186 pr_err("Invalid UCTL clock rate of %u, using 12000000 instead\n", 187 clock_rate); 188 /* Fall through */ 189 case 12000000: 190 clk_rst_ctl.s.p_refclk_div = 0; 191 break; 192 case 24000000: 193 clk_rst_ctl.s.p_refclk_div = 1; 194 break; 195 case 48000000: 196 clk_rst_ctl.s.p_refclk_div = 2; 197 break; 198 } 199 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); 200 201 /* 3c */ 202 div = octeon_get_io_clock_rate() / 130000000ull; 203 204 switch (div) { 205 case 0: 206 div = 1; 207 break; 208 case 1: 209 case 2: 210 case 3: 211 case 4: 212 break; 213 case 5: 214 div = 4; 215 break; 216 case 6: 217 case 7: 218 div = 6; 219 break; 220 case 8: 221 case 9: 222 case 10: 223 case 11: 224 div = 8; 225 break; 226 default: 227 div = 12; 228 break; 229 } 230 clk_rst_ctl.s.h_div = div; 231 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); 232 /* Read it back, */ 233 clk_rst_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_CLK_RST_CTL(0)); 234 clk_rst_ctl.s.h_clkdiv_en = 1; 235 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); 236 /* 3d */ 237 clk_rst_ctl.s.h_clkdiv_rst = 1; 238 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); 239 240 /* 3e: delay 64 io clocks */ 241 ndelay(io_clk_64_to_ns); 242 243 /* 244 * Step 4: Program the power-on reset field in the UCTL 245 * clock-reset-control register. 246 */ 247 clk_rst_ctl.s.p_por = 0; 248 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); 249 250 /* Step 5: Wait 3 ms for the PHY clock to start. */ 251 mdelay(3); 252 253 /* Steps 6..9 for ATE only, are skipped. */ 254 255 /* Step 10: Configure the OHCI_CLK48 and OHCI_CLK12 clocks. */ 256 /* 10a */ 257 clk_rst_ctl.s.o_clkdiv_rst = 1; 258 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); 259 260 /* 10b */ 261 clk_rst_ctl.s.o_clkdiv_en = 1; 262 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); 263 264 /* 10c */ 265 ndelay(io_clk_64_to_ns); 266 267 /* 268 * Step 11: Program the PHY reset field: 269 * UCTL0_CLK_RST_CTL[P_PRST] = 1 270 */ 271 clk_rst_ctl.s.p_prst = 1; 272 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); 273 274 /* Step 11b */ 275 udelay(1); 276 277 /* Step 11c */ 278 clk_rst_ctl.s.p_prst = 0; 279 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); 280 281 /* Step 11d */ 282 mdelay(1); 283 284 /* Step 11e */ 285 clk_rst_ctl.s.p_prst = 1; 286 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); 287 288 /* Step 12: Wait 1 uS. */ 289 udelay(1); 290 291 /* Step 13: Program the HRESET_N field: UCTL0_CLK_RST_CTL[HRST] = 1 */ 292 clk_rst_ctl.s.hrst = 1; 293 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); 294 295 end_clock: 296 /* Set uSOF cycle period to 60,000 bits. */ 297 cvmx_write_csr(CVMX_UCTLX_EHCI_FLA(0), 0x20ull); 298 299 exit: 300 mutex_unlock(&octeon2_usb_clocks_mutex); 301 } 302 303 static void octeon2_usb_clocks_stop(void) 304 { 305 mutex_lock(&octeon2_usb_clocks_mutex); 306 octeon2_usb_clock_start_cnt--; 307 mutex_unlock(&octeon2_usb_clocks_mutex); 308 } 309 310 static int octeon_ehci_power_on(struct platform_device *pdev) 311 { 312 octeon2_usb_clocks_start(&pdev->dev); 313 return 0; 314 } 315 316 static void octeon_ehci_power_off(struct platform_device *pdev) 317 { 318 octeon2_usb_clocks_stop(); 319 } 320 321 static struct usb_ehci_pdata octeon_ehci_pdata = { 322 /* Octeon EHCI matches CPU endianness. */ 323 #ifdef __BIG_ENDIAN 324 .big_endian_mmio = 1, 325 #endif 326 /* 327 * We can DMA from anywhere. But the descriptors must be in 328 * the lower 4GB. 329 */ 330 .dma_mask_64 = 0, 331 .power_on = octeon_ehci_power_on, 332 .power_off = octeon_ehci_power_off, 333 }; 334 335 static void __init octeon_ehci_hw_start(struct device *dev) 336 { 337 union cvmx_uctlx_ehci_ctl ehci_ctl; 338 339 octeon2_usb_clocks_start(dev); 340 341 ehci_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_EHCI_CTL(0)); 342 /* Use 64-bit addressing. */ 343 ehci_ctl.s.ehci_64b_addr_en = 1; 344 ehci_ctl.s.l2c_addr_msb = 0; 345 #ifdef __BIG_ENDIAN 346 ehci_ctl.s.l2c_buff_emod = 1; /* Byte swapped. */ 347 ehci_ctl.s.l2c_desc_emod = 1; /* Byte swapped. */ 348 #else 349 ehci_ctl.s.l2c_buff_emod = 0; /* not swapped. */ 350 ehci_ctl.s.l2c_desc_emod = 0; /* not swapped. */ 351 ehci_ctl.s.inv_reg_a2 = 1; 352 #endif 353 cvmx_write_csr(CVMX_UCTLX_EHCI_CTL(0), ehci_ctl.u64); 354 355 octeon2_usb_clocks_stop(); 356 } 357 358 static int __init octeon_ehci_device_init(void) 359 { 360 struct platform_device *pd; 361 struct device_node *ehci_node; 362 int ret = 0; 363 364 ehci_node = of_find_node_by_name(NULL, "ehci"); 365 if (!ehci_node) 366 return 0; 367 368 pd = of_find_device_by_node(ehci_node); 369 if (!pd) 370 return 0; 371 372 pd->dev.platform_data = &octeon_ehci_pdata; 373 octeon_ehci_hw_start(&pd->dev); 374 375 return ret; 376 } 377 device_initcall(octeon_ehci_device_init); 378 379 static int octeon_ohci_power_on(struct platform_device *pdev) 380 { 381 octeon2_usb_clocks_start(&pdev->dev); 382 return 0; 383 } 384 385 static void octeon_ohci_power_off(struct platform_device *pdev) 386 { 387 octeon2_usb_clocks_stop(); 388 } 389 390 static struct usb_ohci_pdata octeon_ohci_pdata = { 391 /* Octeon OHCI matches CPU endianness. */ 392 #ifdef __BIG_ENDIAN 393 .big_endian_mmio = 1, 394 #endif 395 .power_on = octeon_ohci_power_on, 396 .power_off = octeon_ohci_power_off, 397 }; 398 399 static void __init octeon_ohci_hw_start(struct device *dev) 400 { 401 union cvmx_uctlx_ohci_ctl ohci_ctl; 402 403 octeon2_usb_clocks_start(dev); 404 405 ohci_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_OHCI_CTL(0)); 406 ohci_ctl.s.l2c_addr_msb = 0; 407 #ifdef __BIG_ENDIAN 408 ohci_ctl.s.l2c_buff_emod = 1; /* Byte swapped. */ 409 ohci_ctl.s.l2c_desc_emod = 1; /* Byte swapped. */ 410 #else 411 ohci_ctl.s.l2c_buff_emod = 0; /* not swapped. */ 412 ohci_ctl.s.l2c_desc_emod = 0; /* not swapped. */ 413 ohci_ctl.s.inv_reg_a2 = 1; 414 #endif 415 cvmx_write_csr(CVMX_UCTLX_OHCI_CTL(0), ohci_ctl.u64); 416 417 octeon2_usb_clocks_stop(); 418 } 419 420 static int __init octeon_ohci_device_init(void) 421 { 422 struct platform_device *pd; 423 struct device_node *ohci_node; 424 int ret = 0; 425 426 ohci_node = of_find_node_by_name(NULL, "ohci"); 427 if (!ohci_node) 428 return 0; 429 430 pd = of_find_device_by_node(ohci_node); 431 if (!pd) 432 return 0; 433 434 pd->dev.platform_data = &octeon_ohci_pdata; 435 octeon_ohci_hw_start(&pd->dev); 436 437 return ret; 438 } 439 device_initcall(octeon_ohci_device_init); 440 441 #endif /* CONFIG_USB */ 442 443 444 static struct of_device_id __initdata octeon_ids[] = { 445 { .compatible = "simple-bus", }, 446 { .compatible = "cavium,octeon-6335-uctl", }, 447 { .compatible = "cavium,octeon-5750-usbn", }, 448 { .compatible = "cavium,octeon-3860-bootbus", }, 449 { .compatible = "cavium,mdio-mux", }, 450 { .compatible = "gpio-leds", }, 451 { .compatible = "cavium,octeon-7130-usb-uctl", }, 452 {}, 453 }; 454 455 static bool __init octeon_has_88e1145(void) 456 { 457 return !OCTEON_IS_MODEL(OCTEON_CN52XX) && 458 !OCTEON_IS_MODEL(OCTEON_CN6XXX) && 459 !OCTEON_IS_MODEL(OCTEON_CN56XX); 460 } 461 462 static void __init octeon_fdt_set_phy(int eth, int phy_addr) 463 { 464 const __be32 *phy_handle; 465 const __be32 *alt_phy_handle; 466 const __be32 *reg; 467 u32 phandle; 468 int phy; 469 int alt_phy; 470 const char *p; 471 int current_len; 472 char new_name[20]; 473 474 phy_handle = fdt_getprop(initial_boot_params, eth, "phy-handle", NULL); 475 if (!phy_handle) 476 return; 477 478 phandle = be32_to_cpup(phy_handle); 479 phy = fdt_node_offset_by_phandle(initial_boot_params, phandle); 480 481 alt_phy_handle = fdt_getprop(initial_boot_params, eth, "cavium,alt-phy-handle", NULL); 482 if (alt_phy_handle) { 483 u32 alt_phandle = be32_to_cpup(alt_phy_handle); 484 alt_phy = fdt_node_offset_by_phandle(initial_boot_params, alt_phandle); 485 } else { 486 alt_phy = -1; 487 } 488 489 if (phy_addr < 0 || phy < 0) { 490 /* Delete the PHY things */ 491 fdt_nop_property(initial_boot_params, eth, "phy-handle"); 492 /* This one may fail */ 493 fdt_nop_property(initial_boot_params, eth, "cavium,alt-phy-handle"); 494 if (phy >= 0) 495 fdt_nop_node(initial_boot_params, phy); 496 if (alt_phy >= 0) 497 fdt_nop_node(initial_boot_params, alt_phy); 498 return; 499 } 500 501 if (phy_addr >= 256 && alt_phy > 0) { 502 const struct fdt_property *phy_prop; 503 struct fdt_property *alt_prop; 504 u32 phy_handle_name; 505 506 /* Use the alt phy node instead.*/ 507 phy_prop = fdt_get_property(initial_boot_params, eth, "phy-handle", NULL); 508 phy_handle_name = phy_prop->nameoff; 509 fdt_nop_node(initial_boot_params, phy); 510 fdt_nop_property(initial_boot_params, eth, "phy-handle"); 511 alt_prop = fdt_get_property_w(initial_boot_params, eth, "cavium,alt-phy-handle", NULL); 512 alt_prop->nameoff = phy_handle_name; 513 phy = alt_phy; 514 } 515 516 phy_addr &= 0xff; 517 518 if (octeon_has_88e1145()) { 519 fdt_nop_property(initial_boot_params, phy, "marvell,reg-init"); 520 memset(new_name, 0, sizeof(new_name)); 521 strcpy(new_name, "marvell,88e1145"); 522 p = fdt_getprop(initial_boot_params, phy, "compatible", 523 ¤t_len); 524 if (p && current_len >= strlen(new_name)) 525 fdt_setprop_inplace(initial_boot_params, phy, 526 "compatible", new_name, current_len); 527 } 528 529 reg = fdt_getprop(initial_boot_params, phy, "reg", NULL); 530 if (phy_addr == be32_to_cpup(reg)) 531 return; 532 533 fdt_setprop_inplace_cell(initial_boot_params, phy, "reg", phy_addr); 534 535 snprintf(new_name, sizeof(new_name), "ethernet-phy@%x", phy_addr); 536 537 p = fdt_get_name(initial_boot_params, phy, ¤t_len); 538 if (p && current_len == strlen(new_name)) 539 fdt_set_name(initial_boot_params, phy, new_name); 540 else 541 pr_err("Error: could not rename ethernet phy: <%s>", p); 542 } 543 544 static void __init octeon_fdt_set_mac_addr(int n, u64 *pmac) 545 { 546 const u8 *old_mac; 547 int old_len; 548 u8 new_mac[6]; 549 u64 mac = *pmac; 550 int r; 551 552 old_mac = fdt_getprop(initial_boot_params, n, "local-mac-address", 553 &old_len); 554 if (!old_mac || old_len != 6 || is_valid_ether_addr(old_mac)) 555 return; 556 557 new_mac[0] = (mac >> 40) & 0xff; 558 new_mac[1] = (mac >> 32) & 0xff; 559 new_mac[2] = (mac >> 24) & 0xff; 560 new_mac[3] = (mac >> 16) & 0xff; 561 new_mac[4] = (mac >> 8) & 0xff; 562 new_mac[5] = mac & 0xff; 563 564 r = fdt_setprop_inplace(initial_boot_params, n, "local-mac-address", 565 new_mac, sizeof(new_mac)); 566 567 if (r) { 568 pr_err("Setting \"local-mac-address\" failed %d", r); 569 return; 570 } 571 *pmac = mac + 1; 572 } 573 574 static void __init octeon_fdt_rm_ethernet(int node) 575 { 576 const __be32 *phy_handle; 577 578 phy_handle = fdt_getprop(initial_boot_params, node, "phy-handle", NULL); 579 if (phy_handle) { 580 u32 ph = be32_to_cpup(phy_handle); 581 int p = fdt_node_offset_by_phandle(initial_boot_params, ph); 582 if (p >= 0) 583 fdt_nop_node(initial_boot_params, p); 584 } 585 fdt_nop_node(initial_boot_params, node); 586 } 587 588 static void __init octeon_fdt_pip_port(int iface, int i, int p, int max) 589 { 590 char name_buffer[20]; 591 int eth; 592 int phy_addr; 593 int ipd_port; 594 595 snprintf(name_buffer, sizeof(name_buffer), "ethernet@%x", p); 596 eth = fdt_subnode_offset(initial_boot_params, iface, name_buffer); 597 if (eth < 0) 598 return; 599 if (p > max) { 600 pr_debug("Deleting port %x:%x\n", i, p); 601 octeon_fdt_rm_ethernet(eth); 602 return; 603 } 604 if (OCTEON_IS_MODEL(OCTEON_CN68XX)) 605 ipd_port = (0x100 * i) + (0x10 * p) + 0x800; 606 else 607 ipd_port = 16 * i + p; 608 609 phy_addr = cvmx_helper_board_get_mii_address(ipd_port); 610 octeon_fdt_set_phy(eth, phy_addr); 611 } 612 613 static void __init octeon_fdt_pip_iface(int pip, int idx) 614 { 615 char name_buffer[20]; 616 int iface; 617 int p; 618 int count = 0; 619 620 snprintf(name_buffer, sizeof(name_buffer), "interface@%d", idx); 621 iface = fdt_subnode_offset(initial_boot_params, pip, name_buffer); 622 if (iface < 0) 623 return; 624 625 if (cvmx_helper_interface_enumerate(idx) == 0) 626 count = cvmx_helper_ports_on_interface(idx); 627 628 for (p = 0; p < 16; p++) 629 octeon_fdt_pip_port(iface, idx, p, count - 1); 630 } 631 632 void __init octeon_fill_mac_addresses(void) 633 { 634 const char *alias_prop; 635 char name_buffer[20]; 636 u64 mac_addr_base; 637 int aliases; 638 int pip; 639 int i; 640 641 aliases = fdt_path_offset(initial_boot_params, "/aliases"); 642 if (aliases < 0) 643 return; 644 645 mac_addr_base = 646 ((octeon_bootinfo->mac_addr_base[0] & 0xffull)) << 40 | 647 ((octeon_bootinfo->mac_addr_base[1] & 0xffull)) << 32 | 648 ((octeon_bootinfo->mac_addr_base[2] & 0xffull)) << 24 | 649 ((octeon_bootinfo->mac_addr_base[3] & 0xffull)) << 16 | 650 ((octeon_bootinfo->mac_addr_base[4] & 0xffull)) << 8 | 651 (octeon_bootinfo->mac_addr_base[5] & 0xffull); 652 653 for (i = 0; i < 2; i++) { 654 int mgmt; 655 656 snprintf(name_buffer, sizeof(name_buffer), "mix%d", i); 657 alias_prop = fdt_getprop(initial_boot_params, aliases, 658 name_buffer, NULL); 659 if (!alias_prop) 660 continue; 661 mgmt = fdt_path_offset(initial_boot_params, alias_prop); 662 if (mgmt < 0) 663 continue; 664 octeon_fdt_set_mac_addr(mgmt, &mac_addr_base); 665 } 666 667 alias_prop = fdt_getprop(initial_boot_params, aliases, "pip", NULL); 668 if (!alias_prop) 669 return; 670 671 pip = fdt_path_offset(initial_boot_params, alias_prop); 672 if (pip < 0) 673 return; 674 675 for (i = 0; i <= 4; i++) { 676 int iface; 677 int p; 678 679 snprintf(name_buffer, sizeof(name_buffer), "interface@%d", i); 680 iface = fdt_subnode_offset(initial_boot_params, pip, 681 name_buffer); 682 if (iface < 0) 683 continue; 684 for (p = 0; p < 16; p++) { 685 int eth; 686 687 snprintf(name_buffer, sizeof(name_buffer), 688 "ethernet@%x", p); 689 eth = fdt_subnode_offset(initial_boot_params, iface, 690 name_buffer); 691 if (eth < 0) 692 continue; 693 octeon_fdt_set_mac_addr(eth, &mac_addr_base); 694 } 695 } 696 } 697 698 int __init octeon_prune_device_tree(void) 699 { 700 int i, max_port, uart_mask; 701 const char *pip_path; 702 const char *alias_prop; 703 char name_buffer[20]; 704 int aliases; 705 706 if (fdt_check_header(initial_boot_params)) 707 panic("Corrupt Device Tree."); 708 709 WARN(octeon_bootinfo->board_type == CVMX_BOARD_TYPE_CUST_DSR1000N, 710 "Built-in DTB booting is deprecated on %s. Please switch to use appended DTB.", 711 cvmx_board_type_to_string(octeon_bootinfo->board_type)); 712 713 aliases = fdt_path_offset(initial_boot_params, "/aliases"); 714 if (aliases < 0) { 715 pr_err("Error: No /aliases node in device tree."); 716 return -EINVAL; 717 } 718 719 if (OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)) 720 max_port = 2; 721 else if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)) 722 max_port = 1; 723 else 724 max_port = 0; 725 726 if (octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC10E) 727 max_port = 0; 728 729 for (i = 0; i < 2; i++) { 730 int mgmt; 731 snprintf(name_buffer, sizeof(name_buffer), 732 "mix%d", i); 733 alias_prop = fdt_getprop(initial_boot_params, aliases, 734 name_buffer, NULL); 735 if (alias_prop) { 736 mgmt = fdt_path_offset(initial_boot_params, alias_prop); 737 if (mgmt < 0) 738 continue; 739 if (i >= max_port) { 740 pr_debug("Deleting mix%d\n", i); 741 octeon_fdt_rm_ethernet(mgmt); 742 fdt_nop_property(initial_boot_params, aliases, 743 name_buffer); 744 } else { 745 int phy_addr = cvmx_helper_board_get_mii_address(CVMX_HELPER_BOARD_MGMT_IPD_PORT + i); 746 octeon_fdt_set_phy(mgmt, phy_addr); 747 } 748 } 749 } 750 751 pip_path = fdt_getprop(initial_boot_params, aliases, "pip", NULL); 752 if (pip_path) { 753 int pip = fdt_path_offset(initial_boot_params, pip_path); 754 if (pip >= 0) 755 for (i = 0; i <= 4; i++) 756 octeon_fdt_pip_iface(pip, i); 757 } 758 759 /* I2C */ 760 if (OCTEON_IS_MODEL(OCTEON_CN52XX) || 761 OCTEON_IS_MODEL(OCTEON_CN63XX) || 762 OCTEON_IS_MODEL(OCTEON_CN68XX) || 763 OCTEON_IS_MODEL(OCTEON_CN56XX)) 764 max_port = 2; 765 else 766 max_port = 1; 767 768 for (i = 0; i < 2; i++) { 769 int i2c; 770 snprintf(name_buffer, sizeof(name_buffer), 771 "twsi%d", i); 772 alias_prop = fdt_getprop(initial_boot_params, aliases, 773 name_buffer, NULL); 774 775 if (alias_prop) { 776 i2c = fdt_path_offset(initial_boot_params, alias_prop); 777 if (i2c < 0) 778 continue; 779 if (i >= max_port) { 780 pr_debug("Deleting twsi%d\n", i); 781 fdt_nop_node(initial_boot_params, i2c); 782 fdt_nop_property(initial_boot_params, aliases, 783 name_buffer); 784 } 785 } 786 } 787 788 /* SMI/MDIO */ 789 if (OCTEON_IS_MODEL(OCTEON_CN68XX)) 790 max_port = 4; 791 else if (OCTEON_IS_MODEL(OCTEON_CN52XX) || 792 OCTEON_IS_MODEL(OCTEON_CN63XX) || 793 OCTEON_IS_MODEL(OCTEON_CN56XX)) 794 max_port = 2; 795 else 796 max_port = 1; 797 798 for (i = 0; i < 2; i++) { 799 int i2c; 800 snprintf(name_buffer, sizeof(name_buffer), 801 "smi%d", i); 802 alias_prop = fdt_getprop(initial_boot_params, aliases, 803 name_buffer, NULL); 804 805 if (alias_prop) { 806 i2c = fdt_path_offset(initial_boot_params, alias_prop); 807 if (i2c < 0) 808 continue; 809 if (i >= max_port) { 810 pr_debug("Deleting smi%d\n", i); 811 fdt_nop_node(initial_boot_params, i2c); 812 fdt_nop_property(initial_boot_params, aliases, 813 name_buffer); 814 } 815 } 816 } 817 818 /* Serial */ 819 uart_mask = 3; 820 821 /* Right now CN52XX is the only chip with a third uart */ 822 if (OCTEON_IS_MODEL(OCTEON_CN52XX)) 823 uart_mask |= 4; /* uart2 */ 824 825 for (i = 0; i < 3; i++) { 826 int uart; 827 snprintf(name_buffer, sizeof(name_buffer), 828 "uart%d", i); 829 alias_prop = fdt_getprop(initial_boot_params, aliases, 830 name_buffer, NULL); 831 832 if (alias_prop) { 833 uart = fdt_path_offset(initial_boot_params, alias_prop); 834 if (uart_mask & (1 << i)) { 835 __be32 f; 836 837 f = cpu_to_be32(octeon_get_io_clock_rate()); 838 fdt_setprop_inplace(initial_boot_params, 839 uart, "clock-frequency", 840 &f, sizeof(f)); 841 continue; 842 } 843 pr_debug("Deleting uart%d\n", i); 844 fdt_nop_node(initial_boot_params, uart); 845 fdt_nop_property(initial_boot_params, aliases, 846 name_buffer); 847 } 848 } 849 850 /* Compact Flash */ 851 alias_prop = fdt_getprop(initial_boot_params, aliases, 852 "cf0", NULL); 853 if (alias_prop) { 854 union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg; 855 unsigned long base_ptr, region_base, region_size; 856 unsigned long region1_base = 0; 857 unsigned long region1_size = 0; 858 int cs, bootbus; 859 bool is_16bit = false; 860 bool is_true_ide = false; 861 __be32 new_reg[6]; 862 __be32 *ranges; 863 int len; 864 865 int cf = fdt_path_offset(initial_boot_params, alias_prop); 866 base_ptr = 0; 867 if (octeon_bootinfo->major_version == 1 868 && octeon_bootinfo->minor_version >= 1) { 869 if (octeon_bootinfo->compact_flash_common_base_addr) 870 base_ptr = octeon_bootinfo->compact_flash_common_base_addr; 871 } else { 872 base_ptr = 0x1d000800; 873 } 874 875 if (!base_ptr) 876 goto no_cf; 877 878 /* Find CS0 region. */ 879 for (cs = 0; cs < 8; cs++) { 880 mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs)); 881 region_base = mio_boot_reg_cfg.s.base << 16; 882 region_size = (mio_boot_reg_cfg.s.size + 1) << 16; 883 if (mio_boot_reg_cfg.s.en && base_ptr >= region_base 884 && base_ptr < region_base + region_size) { 885 is_16bit = mio_boot_reg_cfg.s.width; 886 break; 887 } 888 } 889 if (cs >= 7) { 890 /* cs and cs + 1 are CS0 and CS1, both must be less than 8. */ 891 goto no_cf; 892 } 893 894 if (!(base_ptr & 0xfffful)) { 895 /* 896 * Boot loader signals availability of DMA (true_ide 897 * mode) by setting low order bits of base_ptr to 898 * zero. 899 */ 900 901 /* Asume that CS1 immediately follows. */ 902 mio_boot_reg_cfg.u64 = 903 cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs + 1)); 904 region1_base = mio_boot_reg_cfg.s.base << 16; 905 region1_size = (mio_boot_reg_cfg.s.size + 1) << 16; 906 if (!mio_boot_reg_cfg.s.en) 907 goto no_cf; 908 is_true_ide = true; 909 910 } else { 911 fdt_nop_property(initial_boot_params, cf, "cavium,true-ide"); 912 fdt_nop_property(initial_boot_params, cf, "cavium,dma-engine-handle"); 913 if (!is_16bit) { 914 __be32 width = cpu_to_be32(8); 915 fdt_setprop_inplace(initial_boot_params, cf, 916 "cavium,bus-width", &width, sizeof(width)); 917 } 918 } 919 new_reg[0] = cpu_to_be32(cs); 920 new_reg[1] = cpu_to_be32(0); 921 new_reg[2] = cpu_to_be32(0x10000); 922 new_reg[3] = cpu_to_be32(cs + 1); 923 new_reg[4] = cpu_to_be32(0); 924 new_reg[5] = cpu_to_be32(0x10000); 925 fdt_setprop_inplace(initial_boot_params, cf, 926 "reg", new_reg, sizeof(new_reg)); 927 928 bootbus = fdt_parent_offset(initial_boot_params, cf); 929 if (bootbus < 0) 930 goto no_cf; 931 ranges = fdt_getprop_w(initial_boot_params, bootbus, "ranges", &len); 932 if (!ranges || len < (5 * 8 * sizeof(__be32))) 933 goto no_cf; 934 935 ranges[(cs * 5) + 2] = cpu_to_be32(region_base >> 32); 936 ranges[(cs * 5) + 3] = cpu_to_be32(region_base & 0xffffffff); 937 ranges[(cs * 5) + 4] = cpu_to_be32(region_size); 938 if (is_true_ide) { 939 cs++; 940 ranges[(cs * 5) + 2] = cpu_to_be32(region1_base >> 32); 941 ranges[(cs * 5) + 3] = cpu_to_be32(region1_base & 0xffffffff); 942 ranges[(cs * 5) + 4] = cpu_to_be32(region1_size); 943 } 944 goto end_cf; 945 no_cf: 946 fdt_nop_node(initial_boot_params, cf); 947 948 end_cf: 949 ; 950 } 951 952 /* 8 char LED */ 953 alias_prop = fdt_getprop(initial_boot_params, aliases, 954 "led0", NULL); 955 if (alias_prop) { 956 union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg; 957 unsigned long base_ptr, region_base, region_size; 958 int cs, bootbus; 959 __be32 new_reg[6]; 960 __be32 *ranges; 961 int len; 962 int led = fdt_path_offset(initial_boot_params, alias_prop); 963 964 base_ptr = octeon_bootinfo->led_display_base_addr; 965 if (base_ptr == 0) 966 goto no_led; 967 /* Find CS0 region. */ 968 for (cs = 0; cs < 8; cs++) { 969 mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs)); 970 region_base = mio_boot_reg_cfg.s.base << 16; 971 region_size = (mio_boot_reg_cfg.s.size + 1) << 16; 972 if (mio_boot_reg_cfg.s.en && base_ptr >= region_base 973 && base_ptr < region_base + region_size) 974 break; 975 } 976 977 if (cs > 7) 978 goto no_led; 979 980 new_reg[0] = cpu_to_be32(cs); 981 new_reg[1] = cpu_to_be32(0x20); 982 new_reg[2] = cpu_to_be32(0x20); 983 new_reg[3] = cpu_to_be32(cs); 984 new_reg[4] = cpu_to_be32(0); 985 new_reg[5] = cpu_to_be32(0x20); 986 fdt_setprop_inplace(initial_boot_params, led, 987 "reg", new_reg, sizeof(new_reg)); 988 989 bootbus = fdt_parent_offset(initial_boot_params, led); 990 if (bootbus < 0) 991 goto no_led; 992 ranges = fdt_getprop_w(initial_boot_params, bootbus, "ranges", &len); 993 if (!ranges || len < (5 * 8 * sizeof(__be32))) 994 goto no_led; 995 996 ranges[(cs * 5) + 2] = cpu_to_be32(region_base >> 32); 997 ranges[(cs * 5) + 3] = cpu_to_be32(region_base & 0xffffffff); 998 ranges[(cs * 5) + 4] = cpu_to_be32(region_size); 999 goto end_led; 1000 1001 no_led: 1002 fdt_nop_node(initial_boot_params, led); 1003 end_led: 1004 ; 1005 } 1006 1007 /* OHCI/UHCI USB */ 1008 alias_prop = fdt_getprop(initial_boot_params, aliases, 1009 "uctl", NULL); 1010 if (alias_prop) { 1011 int uctl = fdt_path_offset(initial_boot_params, alias_prop); 1012 1013 if (uctl >= 0 && (!OCTEON_IS_MODEL(OCTEON_CN6XXX) || 1014 octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC2E)) { 1015 pr_debug("Deleting uctl\n"); 1016 fdt_nop_node(initial_boot_params, uctl); 1017 fdt_nop_property(initial_boot_params, aliases, "uctl"); 1018 } else if (octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC10E || 1019 octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC4E) { 1020 /* Missing "refclk-type" defaults to crystal. */ 1021 fdt_nop_property(initial_boot_params, uctl, "refclk-type"); 1022 } 1023 } 1024 1025 /* DWC2 USB */ 1026 alias_prop = fdt_getprop(initial_boot_params, aliases, 1027 "usbn", NULL); 1028 if (alias_prop) { 1029 int usbn = fdt_path_offset(initial_boot_params, alias_prop); 1030 1031 if (usbn >= 0 && (current_cpu_type() == CPU_CAVIUM_OCTEON2 || 1032 !octeon_has_feature(OCTEON_FEATURE_USB))) { 1033 pr_debug("Deleting usbn\n"); 1034 fdt_nop_node(initial_boot_params, usbn); 1035 fdt_nop_property(initial_boot_params, aliases, "usbn"); 1036 } else { 1037 __be32 new_f[1]; 1038 enum cvmx_helper_board_usb_clock_types c; 1039 c = __cvmx_helper_board_usb_get_clock_type(); 1040 switch (c) { 1041 case USB_CLOCK_TYPE_REF_48: 1042 new_f[0] = cpu_to_be32(48000000); 1043 fdt_setprop_inplace(initial_boot_params, usbn, 1044 "refclk-frequency", new_f, sizeof(new_f)); 1045 /* Fall through ...*/ 1046 case USB_CLOCK_TYPE_REF_12: 1047 /* Missing "refclk-type" defaults to external. */ 1048 fdt_nop_property(initial_boot_params, usbn, "refclk-type"); 1049 break; 1050 default: 1051 break; 1052 } 1053 } 1054 } 1055 1056 return 0; 1057 } 1058 1059 static int __init octeon_publish_devices(void) 1060 { 1061 return of_platform_bus_probe(NULL, octeon_ids, NULL); 1062 } 1063 arch_initcall(octeon_publish_devices); 1064