1 /*
2  * This file is subject to the terms and conditions of the GNU General Public
3  * License.  See the file "COPYING" in the main directory of this archive
4  * for more details.
5  *
6  * Copyright (C) 2004-2017 Cavium, Inc.
7  * Copyright (C) 2008 Wind River Systems
8  */
9 
10 #include <linux/etherdevice.h>
11 #include <linux/of_platform.h>
12 #include <linux/of_fdt.h>
13 #include <linux/libfdt.h>
14 
15 #include <asm/octeon/octeon.h>
16 #include <asm/octeon/cvmx-helper-board.h>
17 
18 #ifdef CONFIG_USB
19 #include <linux/usb/ehci_def.h>
20 #include <linux/usb/ehci_pdriver.h>
21 #include <linux/usb/ohci_pdriver.h>
22 #include <asm/octeon/cvmx-uctlx-defs.h>
23 
24 #define CVMX_UAHCX_EHCI_USBCMD	(CVMX_ADD_IO_SEG(0x00016F0000000010ull))
25 #define CVMX_UAHCX_OHCI_USBCMD	(CVMX_ADD_IO_SEG(0x00016F0000000408ull))
26 
27 static DEFINE_MUTEX(octeon2_usb_clocks_mutex);
28 
29 static int octeon2_usb_clock_start_cnt;
30 
31 static int __init octeon2_usb_reset(void)
32 {
33 	union cvmx_uctlx_clk_rst_ctl clk_rst_ctl;
34 	u32 ucmd;
35 
36 	if (!OCTEON_IS_OCTEON2())
37 		return 0;
38 
39 	clk_rst_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_CLK_RST_CTL(0));
40 	if (clk_rst_ctl.s.hrst) {
41 		ucmd = cvmx_read64_uint32(CVMX_UAHCX_EHCI_USBCMD);
42 		ucmd &= ~CMD_RUN;
43 		cvmx_write64_uint32(CVMX_UAHCX_EHCI_USBCMD, ucmd);
44 		mdelay(2);
45 		ucmd |= CMD_RESET;
46 		cvmx_write64_uint32(CVMX_UAHCX_EHCI_USBCMD, ucmd);
47 		ucmd = cvmx_read64_uint32(CVMX_UAHCX_OHCI_USBCMD);
48 		ucmd |= CMD_RUN;
49 		cvmx_write64_uint32(CVMX_UAHCX_OHCI_USBCMD, ucmd);
50 	}
51 
52 	return 0;
53 }
54 arch_initcall(octeon2_usb_reset);
55 
56 static void octeon2_usb_clocks_start(struct device *dev)
57 {
58 	u64 div;
59 	union cvmx_uctlx_if_ena if_ena;
60 	union cvmx_uctlx_clk_rst_ctl clk_rst_ctl;
61 	union cvmx_uctlx_uphy_portx_ctl_status port_ctl_status;
62 	int i;
63 	unsigned long io_clk_64_to_ns;
64 	u32 clock_rate = 12000000;
65 	bool is_crystal_clock = false;
66 
67 
68 	mutex_lock(&octeon2_usb_clocks_mutex);
69 
70 	octeon2_usb_clock_start_cnt++;
71 	if (octeon2_usb_clock_start_cnt != 1)
72 		goto exit;
73 
74 	io_clk_64_to_ns = 64000000000ull / octeon_get_io_clock_rate();
75 
76 	if (dev->of_node) {
77 		struct device_node *uctl_node;
78 		const char *clock_type;
79 
80 		uctl_node = of_get_parent(dev->of_node);
81 		if (!uctl_node) {
82 			dev_err(dev, "No UCTL device node\n");
83 			goto exit;
84 		}
85 		i = of_property_read_u32(uctl_node,
86 					 "refclk-frequency", &clock_rate);
87 		if (i) {
88 			dev_err(dev, "No UCTL \"refclk-frequency\"\n");
89 			goto exit;
90 		}
91 		i = of_property_read_string(uctl_node,
92 					    "refclk-type", &clock_type);
93 
94 		if (!i && strcmp("crystal", clock_type) == 0)
95 			is_crystal_clock = true;
96 	}
97 
98 	/*
99 	 * Step 1: Wait for voltages stable.  That surely happened
100 	 * before starting the kernel.
101 	 *
102 	 * Step 2: Enable  SCLK of UCTL by writing UCTL0_IF_ENA[EN] = 1
103 	 */
104 	if_ena.u64 = 0;
105 	if_ena.s.en = 1;
106 	cvmx_write_csr(CVMX_UCTLX_IF_ENA(0), if_ena.u64);
107 
108 	for (i = 0; i <= 1; i++) {
109 		port_ctl_status.u64 =
110 			cvmx_read_csr(CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(i, 0));
111 		/* Set txvreftune to 15 to obtain compliant 'eye' diagram. */
112 		port_ctl_status.s.txvreftune = 15;
113 		port_ctl_status.s.txrisetune = 1;
114 		port_ctl_status.s.txpreemphasistune = 1;
115 		cvmx_write_csr(CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(i, 0),
116 			       port_ctl_status.u64);
117 	}
118 
119 	/* Step 3: Configure the reference clock, PHY, and HCLK */
120 	clk_rst_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_CLK_RST_CTL(0));
121 
122 	/*
123 	 * If the UCTL looks like it has already been started, skip
124 	 * the initialization, otherwise bus errors are obtained.
125 	 */
126 	if (clk_rst_ctl.s.hrst)
127 		goto end_clock;
128 	/* 3a */
129 	clk_rst_ctl.s.p_por = 1;
130 	clk_rst_ctl.s.hrst = 0;
131 	clk_rst_ctl.s.p_prst = 0;
132 	clk_rst_ctl.s.h_clkdiv_rst = 0;
133 	clk_rst_ctl.s.o_clkdiv_rst = 0;
134 	clk_rst_ctl.s.h_clkdiv_en = 0;
135 	clk_rst_ctl.s.o_clkdiv_en = 0;
136 	cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
137 
138 	/* 3b */
139 	clk_rst_ctl.s.p_refclk_sel = is_crystal_clock ? 0 : 1;
140 	switch (clock_rate) {
141 	default:
142 		pr_err("Invalid UCTL clock rate of %u, using 12000000 instead\n",
143 			clock_rate);
144 		fallthrough;
145 	case 12000000:
146 		clk_rst_ctl.s.p_refclk_div = 0;
147 		break;
148 	case 24000000:
149 		clk_rst_ctl.s.p_refclk_div = 1;
150 		break;
151 	case 48000000:
152 		clk_rst_ctl.s.p_refclk_div = 2;
153 		break;
154 	}
155 	cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
156 
157 	/* 3c */
158 	div = octeon_get_io_clock_rate() / 130000000ull;
159 
160 	switch (div) {
161 	case 0:
162 		div = 1;
163 		break;
164 	case 1:
165 	case 2:
166 	case 3:
167 	case 4:
168 		break;
169 	case 5:
170 		div = 4;
171 		break;
172 	case 6:
173 	case 7:
174 		div = 6;
175 		break;
176 	case 8:
177 	case 9:
178 	case 10:
179 	case 11:
180 		div = 8;
181 		break;
182 	default:
183 		div = 12;
184 		break;
185 	}
186 	clk_rst_ctl.s.h_div = div;
187 	cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
188 	/* Read it back, */
189 	clk_rst_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_CLK_RST_CTL(0));
190 	clk_rst_ctl.s.h_clkdiv_en = 1;
191 	cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
192 	/* 3d */
193 	clk_rst_ctl.s.h_clkdiv_rst = 1;
194 	cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
195 
196 	/* 3e: delay 64 io clocks */
197 	ndelay(io_clk_64_to_ns);
198 
199 	/*
200 	 * Step 4: Program the power-on reset field in the UCTL
201 	 * clock-reset-control register.
202 	 */
203 	clk_rst_ctl.s.p_por = 0;
204 	cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
205 
206 	/* Step 5:    Wait 3 ms for the PHY clock to start. */
207 	mdelay(3);
208 
209 	/* Steps 6..9 for ATE only, are skipped. */
210 
211 	/* Step 10: Configure the OHCI_CLK48 and OHCI_CLK12 clocks. */
212 	/* 10a */
213 	clk_rst_ctl.s.o_clkdiv_rst = 1;
214 	cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
215 
216 	/* 10b */
217 	clk_rst_ctl.s.o_clkdiv_en = 1;
218 	cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
219 
220 	/* 10c */
221 	ndelay(io_clk_64_to_ns);
222 
223 	/*
224 	 * Step 11: Program the PHY reset field:
225 	 * UCTL0_CLK_RST_CTL[P_PRST] = 1
226 	 */
227 	clk_rst_ctl.s.p_prst = 1;
228 	cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
229 
230 	/* Step 11b */
231 	udelay(1);
232 
233 	/* Step 11c */
234 	clk_rst_ctl.s.p_prst = 0;
235 	cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
236 
237 	/* Step 11d */
238 	mdelay(1);
239 
240 	/* Step 11e */
241 	clk_rst_ctl.s.p_prst = 1;
242 	cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
243 
244 	/* Step 12: Wait 1 uS. */
245 	udelay(1);
246 
247 	/* Step 13: Program the HRESET_N field: UCTL0_CLK_RST_CTL[HRST] = 1 */
248 	clk_rst_ctl.s.hrst = 1;
249 	cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
250 
251 end_clock:
252 	/* Set uSOF cycle period to 60,000 bits. */
253 	cvmx_write_csr(CVMX_UCTLX_EHCI_FLA(0), 0x20ull);
254 
255 exit:
256 	mutex_unlock(&octeon2_usb_clocks_mutex);
257 }
258 
259 static void octeon2_usb_clocks_stop(void)
260 {
261 	mutex_lock(&octeon2_usb_clocks_mutex);
262 	octeon2_usb_clock_start_cnt--;
263 	mutex_unlock(&octeon2_usb_clocks_mutex);
264 }
265 
266 static int octeon_ehci_power_on(struct platform_device *pdev)
267 {
268 	octeon2_usb_clocks_start(&pdev->dev);
269 	return 0;
270 }
271 
272 static void octeon_ehci_power_off(struct platform_device *pdev)
273 {
274 	octeon2_usb_clocks_stop();
275 }
276 
277 static struct usb_ehci_pdata octeon_ehci_pdata = {
278 	/* Octeon EHCI matches CPU endianness. */
279 #ifdef __BIG_ENDIAN
280 	.big_endian_mmio	= 1,
281 #endif
282 	/*
283 	 * We can DMA from anywhere. But the descriptors must be in
284 	 * the lower 4GB.
285 	 */
286 	.dma_mask_64	= 0,
287 	.power_on	= octeon_ehci_power_on,
288 	.power_off	= octeon_ehci_power_off,
289 };
290 
291 static void __init octeon_ehci_hw_start(struct device *dev)
292 {
293 	union cvmx_uctlx_ehci_ctl ehci_ctl;
294 
295 	octeon2_usb_clocks_start(dev);
296 
297 	ehci_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_EHCI_CTL(0));
298 	/* Use 64-bit addressing. */
299 	ehci_ctl.s.ehci_64b_addr_en = 1;
300 	ehci_ctl.s.l2c_addr_msb = 0;
301 #ifdef __BIG_ENDIAN
302 	ehci_ctl.s.l2c_buff_emod = 1; /* Byte swapped. */
303 	ehci_ctl.s.l2c_desc_emod = 1; /* Byte swapped. */
304 #else
305 	ehci_ctl.s.l2c_buff_emod = 0; /* not swapped. */
306 	ehci_ctl.s.l2c_desc_emod = 0; /* not swapped. */
307 	ehci_ctl.s.inv_reg_a2 = 1;
308 #endif
309 	cvmx_write_csr(CVMX_UCTLX_EHCI_CTL(0), ehci_ctl.u64);
310 
311 	octeon2_usb_clocks_stop();
312 }
313 
314 static int __init octeon_ehci_device_init(void)
315 {
316 	struct platform_device *pd;
317 	struct device_node *ehci_node;
318 	int ret = 0;
319 
320 	ehci_node = of_find_node_by_name(NULL, "ehci");
321 	if (!ehci_node)
322 		return 0;
323 
324 	pd = of_find_device_by_node(ehci_node);
325 	of_node_put(ehci_node);
326 	if (!pd)
327 		return 0;
328 
329 	pd->dev.platform_data = &octeon_ehci_pdata;
330 	octeon_ehci_hw_start(&pd->dev);
331 
332 	return ret;
333 }
334 device_initcall(octeon_ehci_device_init);
335 
336 static int octeon_ohci_power_on(struct platform_device *pdev)
337 {
338 	octeon2_usb_clocks_start(&pdev->dev);
339 	return 0;
340 }
341 
342 static void octeon_ohci_power_off(struct platform_device *pdev)
343 {
344 	octeon2_usb_clocks_stop();
345 }
346 
347 static struct usb_ohci_pdata octeon_ohci_pdata = {
348 	/* Octeon OHCI matches CPU endianness. */
349 #ifdef __BIG_ENDIAN
350 	.big_endian_mmio	= 1,
351 #endif
352 	.power_on	= octeon_ohci_power_on,
353 	.power_off	= octeon_ohci_power_off,
354 };
355 
356 static void __init octeon_ohci_hw_start(struct device *dev)
357 {
358 	union cvmx_uctlx_ohci_ctl ohci_ctl;
359 
360 	octeon2_usb_clocks_start(dev);
361 
362 	ohci_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_OHCI_CTL(0));
363 	ohci_ctl.s.l2c_addr_msb = 0;
364 #ifdef __BIG_ENDIAN
365 	ohci_ctl.s.l2c_buff_emod = 1; /* Byte swapped. */
366 	ohci_ctl.s.l2c_desc_emod = 1; /* Byte swapped. */
367 #else
368 	ohci_ctl.s.l2c_buff_emod = 0; /* not swapped. */
369 	ohci_ctl.s.l2c_desc_emod = 0; /* not swapped. */
370 	ohci_ctl.s.inv_reg_a2 = 1;
371 #endif
372 	cvmx_write_csr(CVMX_UCTLX_OHCI_CTL(0), ohci_ctl.u64);
373 
374 	octeon2_usb_clocks_stop();
375 }
376 
377 static int __init octeon_ohci_device_init(void)
378 {
379 	struct platform_device *pd;
380 	struct device_node *ohci_node;
381 	int ret = 0;
382 
383 	ohci_node = of_find_node_by_name(NULL, "ohci");
384 	if (!ohci_node)
385 		return 0;
386 
387 	pd = of_find_device_by_node(ohci_node);
388 	of_node_put(ohci_node);
389 	if (!pd)
390 		return 0;
391 
392 	pd->dev.platform_data = &octeon_ohci_pdata;
393 	octeon_ohci_hw_start(&pd->dev);
394 
395 	return ret;
396 }
397 device_initcall(octeon_ohci_device_init);
398 
399 #endif /* CONFIG_USB */
400 
401 /* Octeon Random Number Generator.  */
402 static int __init octeon_rng_device_init(void)
403 {
404 	struct platform_device *pd;
405 	int ret = 0;
406 
407 	struct resource rng_resources[] = {
408 		{
409 			.flags	= IORESOURCE_MEM,
410 			.start	= XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS),
411 			.end	= XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS) + 0xf
412 		}, {
413 			.flags	= IORESOURCE_MEM,
414 			.start	= cvmx_build_io_address(8, 0),
415 			.end	= cvmx_build_io_address(8, 0) + 0x7
416 		}
417 	};
418 
419 	pd = platform_device_alloc("octeon_rng", -1);
420 	if (!pd) {
421 		ret = -ENOMEM;
422 		goto out;
423 	}
424 
425 	ret = platform_device_add_resources(pd, rng_resources,
426 					    ARRAY_SIZE(rng_resources));
427 	if (ret)
428 		goto fail;
429 
430 	ret = platform_device_add(pd);
431 	if (ret)
432 		goto fail;
433 
434 	return ret;
435 fail:
436 	platform_device_put(pd);
437 
438 out:
439 	return ret;
440 }
441 device_initcall(octeon_rng_device_init);
442 
443 static const struct of_device_id octeon_ids[] __initconst = {
444 	{ .compatible = "simple-bus", },
445 	{ .compatible = "cavium,octeon-6335-uctl", },
446 	{ .compatible = "cavium,octeon-5750-usbn", },
447 	{ .compatible = "cavium,octeon-3860-bootbus", },
448 	{ .compatible = "cavium,mdio-mux", },
449 	{ .compatible = "gpio-leds", },
450 	{ .compatible = "cavium,octeon-7130-usb-uctl", },
451 	{},
452 };
453 
454 static bool __init octeon_has_88e1145(void)
455 {
456 	return !OCTEON_IS_MODEL(OCTEON_CN52XX) &&
457 	       !OCTEON_IS_MODEL(OCTEON_CN6XXX) &&
458 	       !OCTEON_IS_MODEL(OCTEON_CN56XX);
459 }
460 
461 static bool __init octeon_has_fixed_link(int ipd_port)
462 {
463 	switch (cvmx_sysinfo_get()->board_type) {
464 	case CVMX_BOARD_TYPE_CN3005_EVB_HS5:
465 	case CVMX_BOARD_TYPE_CN3010_EVB_HS5:
466 	case CVMX_BOARD_TYPE_CN3020_EVB_HS5:
467 	case CVMX_BOARD_TYPE_CUST_NB5:
468 	case CVMX_BOARD_TYPE_EBH3100:
469 		/* Port 1 on these boards is always gigabit. */
470 		return ipd_port == 1;
471 	case CVMX_BOARD_TYPE_BBGW_REF:
472 		/* Ports 0 and 1 connect to the switch. */
473 		return ipd_port == 0 || ipd_port == 1;
474 	}
475 	return false;
476 }
477 
478 static void __init octeon_fdt_set_phy(int eth, int phy_addr)
479 {
480 	const __be32 *phy_handle;
481 	const __be32 *alt_phy_handle;
482 	const __be32 *reg;
483 	u32 phandle;
484 	int phy;
485 	int alt_phy;
486 	const char *p;
487 	int current_len;
488 	char new_name[20];
489 
490 	phy_handle = fdt_getprop(initial_boot_params, eth, "phy-handle", NULL);
491 	if (!phy_handle)
492 		return;
493 
494 	phandle = be32_to_cpup(phy_handle);
495 	phy = fdt_node_offset_by_phandle(initial_boot_params, phandle);
496 
497 	alt_phy_handle = fdt_getprop(initial_boot_params, eth, "cavium,alt-phy-handle", NULL);
498 	if (alt_phy_handle) {
499 		u32 alt_phandle = be32_to_cpup(alt_phy_handle);
500 
501 		alt_phy = fdt_node_offset_by_phandle(initial_boot_params, alt_phandle);
502 	} else {
503 		alt_phy = -1;
504 	}
505 
506 	if (phy_addr < 0 || phy < 0) {
507 		/* Delete the PHY things */
508 		fdt_nop_property(initial_boot_params, eth, "phy-handle");
509 		/* This one may fail */
510 		fdt_nop_property(initial_boot_params, eth, "cavium,alt-phy-handle");
511 		if (phy >= 0)
512 			fdt_nop_node(initial_boot_params, phy);
513 		if (alt_phy >= 0)
514 			fdt_nop_node(initial_boot_params, alt_phy);
515 		return;
516 	}
517 
518 	if (phy_addr >= 256 && alt_phy > 0) {
519 		const struct fdt_property *phy_prop;
520 		struct fdt_property *alt_prop;
521 		fdt32_t phy_handle_name;
522 
523 		/* Use the alt phy node instead.*/
524 		phy_prop = fdt_get_property(initial_boot_params, eth, "phy-handle", NULL);
525 		phy_handle_name = phy_prop->nameoff;
526 		fdt_nop_node(initial_boot_params, phy);
527 		fdt_nop_property(initial_boot_params, eth, "phy-handle");
528 		alt_prop = fdt_get_property_w(initial_boot_params, eth, "cavium,alt-phy-handle", NULL);
529 		alt_prop->nameoff = phy_handle_name;
530 		phy = alt_phy;
531 	}
532 
533 	phy_addr &= 0xff;
534 
535 	if (octeon_has_88e1145()) {
536 		fdt_nop_property(initial_boot_params, phy, "marvell,reg-init");
537 		memset(new_name, 0, sizeof(new_name));
538 		strcpy(new_name, "marvell,88e1145");
539 		p = fdt_getprop(initial_boot_params, phy, "compatible",
540 				&current_len);
541 		if (p && current_len >= strlen(new_name))
542 			fdt_setprop_inplace(initial_boot_params, phy,
543 					"compatible", new_name, current_len);
544 	}
545 
546 	reg = fdt_getprop(initial_boot_params, phy, "reg", NULL);
547 	if (phy_addr == be32_to_cpup(reg))
548 		return;
549 
550 	fdt_setprop_inplace_cell(initial_boot_params, phy, "reg", phy_addr);
551 
552 	snprintf(new_name, sizeof(new_name), "ethernet-phy@%x", phy_addr);
553 
554 	p = fdt_get_name(initial_boot_params, phy, &current_len);
555 	if (p && current_len == strlen(new_name))
556 		fdt_set_name(initial_boot_params, phy, new_name);
557 	else
558 		pr_err("Error: could not rename ethernet phy: <%s>", p);
559 }
560 
561 static void __init octeon_fdt_set_mac_addr(int n, u64 *pmac)
562 {
563 	const u8 *old_mac;
564 	int old_len;
565 	u8 new_mac[6];
566 	u64 mac = *pmac;
567 	int r;
568 
569 	old_mac = fdt_getprop(initial_boot_params, n, "local-mac-address",
570 			      &old_len);
571 	if (!old_mac || old_len != 6 || is_valid_ether_addr(old_mac))
572 		return;
573 
574 	new_mac[0] = (mac >> 40) & 0xff;
575 	new_mac[1] = (mac >> 32) & 0xff;
576 	new_mac[2] = (mac >> 24) & 0xff;
577 	new_mac[3] = (mac >> 16) & 0xff;
578 	new_mac[4] = (mac >> 8) & 0xff;
579 	new_mac[5] = mac & 0xff;
580 
581 	r = fdt_setprop_inplace(initial_boot_params, n, "local-mac-address",
582 				new_mac, sizeof(new_mac));
583 
584 	if (r) {
585 		pr_err("Setting \"local-mac-address\" failed %d", r);
586 		return;
587 	}
588 	*pmac = mac + 1;
589 }
590 
591 static void __init octeon_fdt_rm_ethernet(int node)
592 {
593 	const __be32 *phy_handle;
594 
595 	phy_handle = fdt_getprop(initial_boot_params, node, "phy-handle", NULL);
596 	if (phy_handle) {
597 		u32 ph = be32_to_cpup(phy_handle);
598 		int p = fdt_node_offset_by_phandle(initial_boot_params, ph);
599 
600 		if (p >= 0)
601 			fdt_nop_node(initial_boot_params, p);
602 	}
603 	fdt_nop_node(initial_boot_params, node);
604 }
605 
606 static void __init _octeon_rx_tx_delay(int eth, int rx_delay, int tx_delay)
607 {
608 	fdt_setprop_inplace_cell(initial_boot_params, eth, "rx-delay",
609 				 rx_delay);
610 	fdt_setprop_inplace_cell(initial_boot_params, eth, "tx-delay",
611 				 tx_delay);
612 }
613 
614 static void __init octeon_rx_tx_delay(int eth, int iface, int port)
615 {
616 	switch (cvmx_sysinfo_get()->board_type) {
617 	case CVMX_BOARD_TYPE_CN3005_EVB_HS5:
618 		if (iface == 0) {
619 			if (port == 0) {
620 				/*
621 				 * Boards with gigabit WAN ports need a
622 				 * different setting that is compatible with
623 				 * 100 Mbit settings
624 				 */
625 				_octeon_rx_tx_delay(eth, 0xc, 0x0c);
626 				return;
627 			} else if (port == 1) {
628 				/* Different config for switch port. */
629 				_octeon_rx_tx_delay(eth, 0x0, 0x0);
630 				return;
631 			}
632 		}
633 		break;
634 	case CVMX_BOARD_TYPE_UBNT_E100:
635 		if (iface == 0 && port <= 2) {
636 			_octeon_rx_tx_delay(eth, 0x0, 0x10);
637 			return;
638 		}
639 		break;
640 	}
641 	fdt_nop_property(initial_boot_params, eth, "rx-delay");
642 	fdt_nop_property(initial_boot_params, eth, "tx-delay");
643 }
644 
645 static void __init octeon_fdt_pip_port(int iface, int i, int p, int max)
646 {
647 	char name_buffer[20];
648 	int eth;
649 	int phy_addr;
650 	int ipd_port;
651 	int fixed_link;
652 
653 	snprintf(name_buffer, sizeof(name_buffer), "ethernet@%x", p);
654 	eth = fdt_subnode_offset(initial_boot_params, iface, name_buffer);
655 	if (eth < 0)
656 		return;
657 	if (p > max) {
658 		pr_debug("Deleting port %x:%x\n", i, p);
659 		octeon_fdt_rm_ethernet(eth);
660 		return;
661 	}
662 	if (OCTEON_IS_MODEL(OCTEON_CN68XX))
663 		ipd_port = (0x100 * i) + (0x10 * p) + 0x800;
664 	else
665 		ipd_port = 16 * i + p;
666 
667 	phy_addr = cvmx_helper_board_get_mii_address(ipd_port);
668 	octeon_fdt_set_phy(eth, phy_addr);
669 
670 	fixed_link = fdt_subnode_offset(initial_boot_params, eth, "fixed-link");
671 	if (fixed_link < 0)
672 		WARN_ON(octeon_has_fixed_link(ipd_port));
673 	else if (!octeon_has_fixed_link(ipd_port))
674 		fdt_nop_node(initial_boot_params, fixed_link);
675 	octeon_rx_tx_delay(eth, i, p);
676 }
677 
678 static void __init octeon_fdt_pip_iface(int pip, int idx)
679 {
680 	char name_buffer[20];
681 	int iface;
682 	int p;
683 	int count = 0;
684 
685 	snprintf(name_buffer, sizeof(name_buffer), "interface@%d", idx);
686 	iface = fdt_subnode_offset(initial_boot_params, pip, name_buffer);
687 	if (iface < 0)
688 		return;
689 
690 	if (cvmx_helper_interface_enumerate(idx) == 0)
691 		count = cvmx_helper_ports_on_interface(idx);
692 
693 	for (p = 0; p < 16; p++)
694 		octeon_fdt_pip_port(iface, idx, p, count - 1);
695 }
696 
697 void __init octeon_fill_mac_addresses(void)
698 {
699 	const char *alias_prop;
700 	char name_buffer[20];
701 	u64 mac_addr_base;
702 	int aliases;
703 	int pip;
704 	int i;
705 
706 	aliases = fdt_path_offset(initial_boot_params, "/aliases");
707 	if (aliases < 0)
708 		return;
709 
710 	mac_addr_base =
711 		((octeon_bootinfo->mac_addr_base[0] & 0xffull)) << 40 |
712 		((octeon_bootinfo->mac_addr_base[1] & 0xffull)) << 32 |
713 		((octeon_bootinfo->mac_addr_base[2] & 0xffull)) << 24 |
714 		((octeon_bootinfo->mac_addr_base[3] & 0xffull)) << 16 |
715 		((octeon_bootinfo->mac_addr_base[4] & 0xffull)) << 8 |
716 		 (octeon_bootinfo->mac_addr_base[5] & 0xffull);
717 
718 	for (i = 0; i < 2; i++) {
719 		int mgmt;
720 
721 		snprintf(name_buffer, sizeof(name_buffer), "mix%d", i);
722 		alias_prop = fdt_getprop(initial_boot_params, aliases,
723 					 name_buffer, NULL);
724 		if (!alias_prop)
725 			continue;
726 		mgmt = fdt_path_offset(initial_boot_params, alias_prop);
727 		if (mgmt < 0)
728 			continue;
729 		octeon_fdt_set_mac_addr(mgmt, &mac_addr_base);
730 	}
731 
732 	alias_prop = fdt_getprop(initial_boot_params, aliases, "pip", NULL);
733 	if (!alias_prop)
734 		return;
735 
736 	pip = fdt_path_offset(initial_boot_params, alias_prop);
737 	if (pip < 0)
738 		return;
739 
740 	for (i = 0; i <= 4; i++) {
741 		int iface;
742 		int p;
743 
744 		snprintf(name_buffer, sizeof(name_buffer), "interface@%d", i);
745 		iface = fdt_subnode_offset(initial_boot_params, pip,
746 					   name_buffer);
747 		if (iface < 0)
748 			continue;
749 		for (p = 0; p < 16; p++) {
750 			int eth;
751 
752 			snprintf(name_buffer, sizeof(name_buffer),
753 				 "ethernet@%x", p);
754 			eth = fdt_subnode_offset(initial_boot_params, iface,
755 						 name_buffer);
756 			if (eth < 0)
757 				continue;
758 			octeon_fdt_set_mac_addr(eth, &mac_addr_base);
759 		}
760 	}
761 }
762 
763 int __init octeon_prune_device_tree(void)
764 {
765 	int i, max_port, uart_mask;
766 	const char *pip_path;
767 	const char *alias_prop;
768 	char name_buffer[20];
769 	int aliases;
770 
771 	if (fdt_check_header(initial_boot_params))
772 		panic("Corrupt Device Tree.");
773 
774 	WARN(octeon_bootinfo->board_type == CVMX_BOARD_TYPE_CUST_DSR1000N,
775 	     "Built-in DTB booting is deprecated on %s. Please switch to use appended DTB.",
776 	     cvmx_board_type_to_string(octeon_bootinfo->board_type));
777 
778 	aliases = fdt_path_offset(initial_boot_params, "/aliases");
779 	if (aliases < 0) {
780 		pr_err("Error: No /aliases node in device tree.");
781 		return -EINVAL;
782 	}
783 
784 	if (OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))
785 		max_port = 2;
786 	else if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))
787 		max_port = 1;
788 	else
789 		max_port = 0;
790 
791 	if (octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC10E)
792 		max_port = 0;
793 
794 	for (i = 0; i < 2; i++) {
795 		int mgmt;
796 
797 		snprintf(name_buffer, sizeof(name_buffer),
798 			 "mix%d", i);
799 		alias_prop = fdt_getprop(initial_boot_params, aliases,
800 					name_buffer, NULL);
801 		if (alias_prop) {
802 			mgmt = fdt_path_offset(initial_boot_params, alias_prop);
803 			if (mgmt < 0)
804 				continue;
805 			if (i >= max_port) {
806 				pr_debug("Deleting mix%d\n", i);
807 				octeon_fdt_rm_ethernet(mgmt);
808 				fdt_nop_property(initial_boot_params, aliases,
809 						 name_buffer);
810 			} else {
811 				int phy_addr = cvmx_helper_board_get_mii_address(CVMX_HELPER_BOARD_MGMT_IPD_PORT + i);
812 
813 				octeon_fdt_set_phy(mgmt, phy_addr);
814 			}
815 		}
816 	}
817 
818 	pip_path = fdt_getprop(initial_boot_params, aliases, "pip", NULL);
819 	if (pip_path) {
820 		int pip = fdt_path_offset(initial_boot_params, pip_path);
821 
822 		if (pip	 >= 0)
823 			for (i = 0; i <= 4; i++)
824 				octeon_fdt_pip_iface(pip, i);
825 	}
826 
827 	/* I2C */
828 	if (OCTEON_IS_MODEL(OCTEON_CN52XX) ||
829 	    OCTEON_IS_MODEL(OCTEON_CN63XX) ||
830 	    OCTEON_IS_MODEL(OCTEON_CN68XX) ||
831 	    OCTEON_IS_MODEL(OCTEON_CN56XX))
832 		max_port = 2;
833 	else
834 		max_port = 1;
835 
836 	for (i = 0; i < 2; i++) {
837 		int i2c;
838 
839 		snprintf(name_buffer, sizeof(name_buffer),
840 			 "twsi%d", i);
841 		alias_prop = fdt_getprop(initial_boot_params, aliases,
842 					name_buffer, NULL);
843 
844 		if (alias_prop) {
845 			i2c = fdt_path_offset(initial_boot_params, alias_prop);
846 			if (i2c < 0)
847 				continue;
848 			if (i >= max_port) {
849 				pr_debug("Deleting twsi%d\n", i);
850 				fdt_nop_node(initial_boot_params, i2c);
851 				fdt_nop_property(initial_boot_params, aliases,
852 						 name_buffer);
853 			}
854 		}
855 	}
856 
857 	/* SMI/MDIO */
858 	if (OCTEON_IS_MODEL(OCTEON_CN68XX))
859 		max_port = 4;
860 	else if (OCTEON_IS_MODEL(OCTEON_CN52XX) ||
861 		 OCTEON_IS_MODEL(OCTEON_CN63XX) ||
862 		 OCTEON_IS_MODEL(OCTEON_CN56XX))
863 		max_port = 2;
864 	else
865 		max_port = 1;
866 
867 	for (i = 0; i < 2; i++) {
868 		int i2c;
869 
870 		snprintf(name_buffer, sizeof(name_buffer),
871 			 "smi%d", i);
872 		alias_prop = fdt_getprop(initial_boot_params, aliases,
873 					name_buffer, NULL);
874 		if (alias_prop) {
875 			i2c = fdt_path_offset(initial_boot_params, alias_prop);
876 			if (i2c < 0)
877 				continue;
878 			if (i >= max_port) {
879 				pr_debug("Deleting smi%d\n", i);
880 				fdt_nop_node(initial_boot_params, i2c);
881 				fdt_nop_property(initial_boot_params, aliases,
882 						 name_buffer);
883 			}
884 		}
885 	}
886 
887 	/* Serial */
888 	uart_mask = 3;
889 
890 	/* Right now CN52XX is the only chip with a third uart */
891 	if (OCTEON_IS_MODEL(OCTEON_CN52XX))
892 		uart_mask |= 4; /* uart2 */
893 
894 	for (i = 0; i < 3; i++) {
895 		int uart;
896 
897 		snprintf(name_buffer, sizeof(name_buffer),
898 			 "uart%d", i);
899 		alias_prop = fdt_getprop(initial_boot_params, aliases,
900 					name_buffer, NULL);
901 
902 		if (alias_prop) {
903 			uart = fdt_path_offset(initial_boot_params, alias_prop);
904 			if (uart_mask & (1 << i)) {
905 				__be32 f;
906 
907 				f = cpu_to_be32(octeon_get_io_clock_rate());
908 				fdt_setprop_inplace(initial_boot_params,
909 						    uart, "clock-frequency",
910 						    &f, sizeof(f));
911 				continue;
912 			}
913 			pr_debug("Deleting uart%d\n", i);
914 			fdt_nop_node(initial_boot_params, uart);
915 			fdt_nop_property(initial_boot_params, aliases,
916 					 name_buffer);
917 		}
918 	}
919 
920 	/* Compact Flash */
921 	alias_prop = fdt_getprop(initial_boot_params, aliases,
922 				 "cf0", NULL);
923 	if (alias_prop) {
924 		union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg;
925 		unsigned long base_ptr, region_base, region_size;
926 		unsigned long region1_base = 0;
927 		unsigned long region1_size = 0;
928 		int cs, bootbus;
929 		bool is_16bit = false;
930 		bool is_true_ide = false;
931 		__be32 new_reg[6];
932 		__be32 *ranges;
933 		int len;
934 
935 		int cf = fdt_path_offset(initial_boot_params, alias_prop);
936 
937 		base_ptr = 0;
938 		if (octeon_bootinfo->major_version == 1
939 			&& octeon_bootinfo->minor_version >= 1) {
940 			if (octeon_bootinfo->compact_flash_common_base_addr)
941 				base_ptr = octeon_bootinfo->compact_flash_common_base_addr;
942 		} else {
943 			base_ptr = 0x1d000800;
944 		}
945 
946 		if (!base_ptr)
947 			goto no_cf;
948 
949 		/* Find CS0 region. */
950 		for (cs = 0; cs < 8; cs++) {
951 			mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs));
952 			region_base = mio_boot_reg_cfg.s.base << 16;
953 			region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
954 			if (mio_boot_reg_cfg.s.en && base_ptr >= region_base
955 				&& base_ptr < region_base + region_size) {
956 				is_16bit = mio_boot_reg_cfg.s.width;
957 				break;
958 			}
959 		}
960 		if (cs >= 7) {
961 			/* cs and cs + 1 are CS0 and CS1, both must be less than 8. */
962 			goto no_cf;
963 		}
964 
965 		if (!(base_ptr & 0xfffful)) {
966 			/*
967 			 * Boot loader signals availability of DMA (true_ide
968 			 * mode) by setting low order bits of base_ptr to
969 			 * zero.
970 			 */
971 
972 			/* Asume that CS1 immediately follows. */
973 			mio_boot_reg_cfg.u64 =
974 				cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs + 1));
975 			region1_base = mio_boot_reg_cfg.s.base << 16;
976 			region1_size = (mio_boot_reg_cfg.s.size + 1) << 16;
977 			if (!mio_boot_reg_cfg.s.en)
978 				goto no_cf;
979 			is_true_ide = true;
980 
981 		} else {
982 			fdt_nop_property(initial_boot_params, cf, "cavium,true-ide");
983 			fdt_nop_property(initial_boot_params, cf, "cavium,dma-engine-handle");
984 			if (!is_16bit) {
985 				__be32 width = cpu_to_be32(8);
986 
987 				fdt_setprop_inplace(initial_boot_params, cf,
988 						"cavium,bus-width", &width, sizeof(width));
989 			}
990 		}
991 		new_reg[0] = cpu_to_be32(cs);
992 		new_reg[1] = cpu_to_be32(0);
993 		new_reg[2] = cpu_to_be32(0x10000);
994 		new_reg[3] = cpu_to_be32(cs + 1);
995 		new_reg[4] = cpu_to_be32(0);
996 		new_reg[5] = cpu_to_be32(0x10000);
997 		fdt_setprop_inplace(initial_boot_params, cf,
998 				    "reg",  new_reg, sizeof(new_reg));
999 
1000 		bootbus = fdt_parent_offset(initial_boot_params, cf);
1001 		if (bootbus < 0)
1002 			goto no_cf;
1003 		ranges = fdt_getprop_w(initial_boot_params, bootbus, "ranges", &len);
1004 		if (!ranges || len < (5 * 8 * sizeof(__be32)))
1005 			goto no_cf;
1006 
1007 		ranges[(cs * 5) + 2] = cpu_to_be32(region_base >> 32);
1008 		ranges[(cs * 5) + 3] = cpu_to_be32(region_base & 0xffffffff);
1009 		ranges[(cs * 5) + 4] = cpu_to_be32(region_size);
1010 		if (is_true_ide) {
1011 			cs++;
1012 			ranges[(cs * 5) + 2] = cpu_to_be32(region1_base >> 32);
1013 			ranges[(cs * 5) + 3] = cpu_to_be32(region1_base & 0xffffffff);
1014 			ranges[(cs * 5) + 4] = cpu_to_be32(region1_size);
1015 		}
1016 		goto end_cf;
1017 no_cf:
1018 		fdt_nop_node(initial_boot_params, cf);
1019 
1020 end_cf:
1021 		;
1022 	}
1023 
1024 	/* 8 char LED */
1025 	alias_prop = fdt_getprop(initial_boot_params, aliases,
1026 				 "led0", NULL);
1027 	if (alias_prop) {
1028 		union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg;
1029 		unsigned long base_ptr, region_base, region_size;
1030 		int cs, bootbus;
1031 		__be32 new_reg[6];
1032 		__be32 *ranges;
1033 		int len;
1034 		int led = fdt_path_offset(initial_boot_params, alias_prop);
1035 
1036 		base_ptr = octeon_bootinfo->led_display_base_addr;
1037 		if (base_ptr == 0)
1038 			goto no_led;
1039 		/* Find CS0 region. */
1040 		for (cs = 0; cs < 8; cs++) {
1041 			mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs));
1042 			region_base = mio_boot_reg_cfg.s.base << 16;
1043 			region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
1044 			if (mio_boot_reg_cfg.s.en && base_ptr >= region_base
1045 				&& base_ptr < region_base + region_size)
1046 				break;
1047 		}
1048 
1049 		if (cs > 7)
1050 			goto no_led;
1051 
1052 		new_reg[0] = cpu_to_be32(cs);
1053 		new_reg[1] = cpu_to_be32(0x20);
1054 		new_reg[2] = cpu_to_be32(0x20);
1055 		new_reg[3] = cpu_to_be32(cs);
1056 		new_reg[4] = cpu_to_be32(0);
1057 		new_reg[5] = cpu_to_be32(0x20);
1058 		fdt_setprop_inplace(initial_boot_params, led,
1059 				    "reg",  new_reg, sizeof(new_reg));
1060 
1061 		bootbus = fdt_parent_offset(initial_boot_params, led);
1062 		if (bootbus < 0)
1063 			goto no_led;
1064 		ranges = fdt_getprop_w(initial_boot_params, bootbus, "ranges", &len);
1065 		if (!ranges || len < (5 * 8 * sizeof(__be32)))
1066 			goto no_led;
1067 
1068 		ranges[(cs * 5) + 2] = cpu_to_be32(region_base >> 32);
1069 		ranges[(cs * 5) + 3] = cpu_to_be32(region_base & 0xffffffff);
1070 		ranges[(cs * 5) + 4] = cpu_to_be32(region_size);
1071 		goto end_led;
1072 
1073 no_led:
1074 		fdt_nop_node(initial_boot_params, led);
1075 end_led:
1076 		;
1077 	}
1078 
1079 #ifdef CONFIG_USB
1080 	/* OHCI/UHCI USB */
1081 	alias_prop = fdt_getprop(initial_boot_params, aliases,
1082 				 "uctl", NULL);
1083 	if (alias_prop) {
1084 		int uctl = fdt_path_offset(initial_boot_params, alias_prop);
1085 
1086 		if (uctl >= 0 && (!OCTEON_IS_MODEL(OCTEON_CN6XXX) ||
1087 				  octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC2E)) {
1088 			pr_debug("Deleting uctl\n");
1089 			fdt_nop_node(initial_boot_params, uctl);
1090 			fdt_nop_property(initial_boot_params, aliases, "uctl");
1091 		} else if (octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC10E ||
1092 			   octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC4E) {
1093 			/* Missing "refclk-type" defaults to crystal. */
1094 			fdt_nop_property(initial_boot_params, uctl, "refclk-type");
1095 		}
1096 	}
1097 
1098 	/* DWC2 USB */
1099 	alias_prop = fdt_getprop(initial_boot_params, aliases,
1100 				 "usbn", NULL);
1101 	if (alias_prop) {
1102 		int usbn = fdt_path_offset(initial_boot_params, alias_prop);
1103 
1104 		if (usbn >= 0 && (current_cpu_type() == CPU_CAVIUM_OCTEON2 ||
1105 				  !octeon_has_feature(OCTEON_FEATURE_USB))) {
1106 			pr_debug("Deleting usbn\n");
1107 			fdt_nop_node(initial_boot_params, usbn);
1108 			fdt_nop_property(initial_boot_params, aliases, "usbn");
1109 		} else  {
1110 			__be32 new_f[1];
1111 			enum cvmx_helper_board_usb_clock_types c;
1112 
1113 			c = __cvmx_helper_board_usb_get_clock_type();
1114 			switch (c) {
1115 			case USB_CLOCK_TYPE_REF_48:
1116 				new_f[0] = cpu_to_be32(48000000);
1117 				fdt_setprop_inplace(initial_boot_params, usbn,
1118 						    "refclk-frequency",  new_f, sizeof(new_f));
1119 				fallthrough;
1120 			case USB_CLOCK_TYPE_REF_12:
1121 				/* Missing "refclk-type" defaults to external. */
1122 				fdt_nop_property(initial_boot_params, usbn, "refclk-type");
1123 				break;
1124 			default:
1125 				break;
1126 			}
1127 		}
1128 	}
1129 #endif
1130 
1131 	return 0;
1132 }
1133 
1134 static int __init octeon_publish_devices(void)
1135 {
1136 	return of_platform_populate(NULL, octeon_ids, NULL, NULL);
1137 }
1138 arch_initcall(octeon_publish_devices);
1139