1 #include <linux/fs.h> 2 #include <linux/interrupt.h> 3 #include <asm/octeon/octeon.h> 4 #include <asm/octeon/cvmx-ciu-defs.h> 5 #include <asm/octeon/cvmx.h> 6 #include <linux/debugfs.h> 7 #include <linux/kernel.h> 8 #include <linux/module.h> 9 #include <linux/seq_file.h> 10 11 #define TIMER_NUM 3 12 13 static bool reset_stats; 14 15 struct latency_info { 16 u64 io_interval; 17 u64 cpu_interval; 18 u64 timer_start1; 19 u64 timer_start2; 20 u64 max_latency; 21 u64 min_latency; 22 u64 latency_sum; 23 u64 average_latency; 24 u64 interrupt_cnt; 25 }; 26 27 static struct latency_info li; 28 static struct dentry *dir; 29 30 static int show_latency(struct seq_file *m, void *v) 31 { 32 u64 cpuclk, avg, max, min; 33 struct latency_info curr_li = li; 34 35 cpuclk = octeon_get_clock_rate(); 36 37 max = (curr_li.max_latency * 1000000000) / cpuclk; 38 min = (curr_li.min_latency * 1000000000) / cpuclk; 39 avg = (curr_li.latency_sum * 1000000000) / (cpuclk * curr_li.interrupt_cnt); 40 41 seq_printf(m, "cnt: %10lld, avg: %7lld ns, max: %7lld ns, min: %7lld ns\n", 42 curr_li.interrupt_cnt, avg, max, min); 43 return 0; 44 } 45 46 static int oct_ilm_open(struct inode *inode, struct file *file) 47 { 48 return single_open(file, show_latency, NULL); 49 } 50 51 static const struct file_operations oct_ilm_ops = { 52 .open = oct_ilm_open, 53 .read = seq_read, 54 .llseek = seq_lseek, 55 .release = single_release, 56 }; 57 58 static int reset_statistics(void *data, u64 value) 59 { 60 reset_stats = true; 61 return 0; 62 } 63 64 DEFINE_SIMPLE_ATTRIBUTE(reset_statistics_ops, NULL, reset_statistics, "%llu\n"); 65 66 static void init_debugfs(void) 67 { 68 dir = debugfs_create_dir("oct_ilm", 0); 69 debugfs_create_file("statistics", 0222, dir, NULL, &oct_ilm_ops); 70 debugfs_create_file("reset", 0222, dir, NULL, &reset_statistics_ops); 71 } 72 73 static void init_latency_info(struct latency_info *li, int startup) 74 { 75 /* interval in milli seconds after which the interrupt will 76 * be triggered 77 */ 78 int interval = 1; 79 80 if (startup) { 81 /* Calculating by the amounts io clock and cpu clock would 82 * increment in interval amount of ms 83 */ 84 li->io_interval = (octeon_get_io_clock_rate() * interval) / 1000; 85 li->cpu_interval = (octeon_get_clock_rate() * interval) / 1000; 86 } 87 li->timer_start1 = 0; 88 li->timer_start2 = 0; 89 li->max_latency = 0; 90 li->min_latency = (u64)-1; 91 li->latency_sum = 0; 92 li->interrupt_cnt = 0; 93 } 94 95 96 static void start_timer(int timer, u64 interval) 97 { 98 union cvmx_ciu_timx timx; 99 unsigned long flags; 100 101 timx.u64 = 0; 102 timx.s.one_shot = 1; 103 timx.s.len = interval; 104 raw_local_irq_save(flags); 105 li.timer_start1 = read_c0_cvmcount(); 106 cvmx_write_csr(CVMX_CIU_TIMX(timer), timx.u64); 107 /* Read it back to force wait until register is written. */ 108 timx.u64 = cvmx_read_csr(CVMX_CIU_TIMX(timer)); 109 li.timer_start2 = read_c0_cvmcount(); 110 raw_local_irq_restore(flags); 111 } 112 113 114 static irqreturn_t cvm_oct_ciu_timer_interrupt(int cpl, void *dev_id) 115 { 116 u64 last_latency; 117 u64 last_int_cnt; 118 119 if (reset_stats) { 120 init_latency_info(&li, 0); 121 reset_stats = false; 122 } else { 123 last_int_cnt = read_c0_cvmcount(); 124 last_latency = last_int_cnt - (li.timer_start1 + li.cpu_interval); 125 li.interrupt_cnt++; 126 li.latency_sum += last_latency; 127 if (last_latency > li.max_latency) 128 li.max_latency = last_latency; 129 if (last_latency < li.min_latency) 130 li.min_latency = last_latency; 131 } 132 start_timer(TIMER_NUM, li.io_interval); 133 return IRQ_HANDLED; 134 } 135 136 static void disable_timer(int timer) 137 { 138 union cvmx_ciu_timx timx; 139 140 timx.s.one_shot = 0; 141 timx.s.len = 0; 142 cvmx_write_csr(CVMX_CIU_TIMX(timer), timx.u64); 143 /* Read it back to force immediate write of timer register*/ 144 timx.u64 = cvmx_read_csr(CVMX_CIU_TIMX(timer)); 145 } 146 147 static __init int oct_ilm_module_init(void) 148 { 149 int rc; 150 int irq = OCTEON_IRQ_TIMER0 + TIMER_NUM; 151 152 init_debugfs(); 153 154 rc = request_irq(irq, cvm_oct_ciu_timer_interrupt, IRQF_NO_THREAD, 155 "oct_ilm", 0); 156 if (rc) { 157 WARN(1, "Could not acquire IRQ %d", irq); 158 goto err_irq; 159 } 160 161 init_latency_info(&li, 1); 162 start_timer(TIMER_NUM, li.io_interval); 163 164 return 0; 165 err_irq: 166 debugfs_remove_recursive(dir); 167 return rc; 168 } 169 170 static __exit void oct_ilm_module_exit(void) 171 { 172 disable_timer(TIMER_NUM); 173 debugfs_remove_recursive(dir); 174 free_irq(OCTEON_IRQ_TIMER0 + TIMER_NUM, 0); 175 } 176 177 module_exit(oct_ilm_module_exit); 178 module_init(oct_ilm_module_init); 179 MODULE_AUTHOR("Venkat Subbiah, Cavium"); 180 MODULE_DESCRIPTION("Measures interrupt latency on Octeon chips."); 181 MODULE_LICENSE("GPL"); 182