1af866496SDavid Daney /***********************license start***************
2af866496SDavid Daney * Author: Cavium Networks
3af866496SDavid Daney *
4af866496SDavid Daney * Contact: support@caviumnetworks.com
5af866496SDavid Daney * This file is part of the OCTEON SDK
6af866496SDavid Daney *
7af866496SDavid Daney * Copyright (c) 2003-2008 Cavium Networks
8af866496SDavid Daney *
9af866496SDavid Daney * This file is free software; you can redistribute it and/or modify
10af866496SDavid Daney * it under the terms of the GNU General Public License, Version 2, as
11af866496SDavid Daney * published by the Free Software Foundation.
12af866496SDavid Daney *
13af866496SDavid Daney * This file is distributed in the hope that it will be useful, but
14af866496SDavid Daney * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15af866496SDavid Daney * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16af866496SDavid Daney * NONINFRINGEMENT. See the GNU General Public License for more
17af866496SDavid Daney * details.
18af866496SDavid Daney *
19af866496SDavid Daney * You should have received a copy of the GNU General Public License
20af866496SDavid Daney * along with this file; if not, write to the Free Software
21af866496SDavid Daney * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22af866496SDavid Daney * or visit http://www.gnu.org/licenses/.
23af866496SDavid Daney *
24af866496SDavid Daney * This file may also be available under a different license from Cavium.
25af866496SDavid Daney * Contact Cavium Networks for more information
26af866496SDavid Daney ***********************license end**************************************/
27af866496SDavid Daney
28af866496SDavid Daney /*
29af866496SDavid Daney * Support library for the hardware Packet Output unit.
30af866496SDavid Daney */
31af866496SDavid Daney
32af866496SDavid Daney #include <asm/octeon/octeon.h>
33af866496SDavid Daney
34af866496SDavid Daney #include <asm/octeon/cvmx-config.h>
35af866496SDavid Daney #include <asm/octeon/cvmx-pko.h>
36af866496SDavid Daney #include <asm/octeon/cvmx-helper.h>
37af866496SDavid Daney
3816df55ceSRandy Dunlap /*
39af866496SDavid Daney * Internal state of packet output
40af866496SDavid Daney */
41af866496SDavid Daney
__cvmx_pko_int(int interface,int index)42153bfe38SJanne Huttunen static int __cvmx_pko_int(int interface, int index)
43153bfe38SJanne Huttunen {
44153bfe38SJanne Huttunen switch (interface) {
45153bfe38SJanne Huttunen case 0:
46153bfe38SJanne Huttunen return index;
47153bfe38SJanne Huttunen case 1:
48153bfe38SJanne Huttunen return 4;
49153bfe38SJanne Huttunen case 2:
50153bfe38SJanne Huttunen return index + 0x08;
51153bfe38SJanne Huttunen case 3:
52153bfe38SJanne Huttunen return index + 0x0c;
53153bfe38SJanne Huttunen case 4:
54153bfe38SJanne Huttunen return index + 0x10;
55153bfe38SJanne Huttunen case 5:
56153bfe38SJanne Huttunen return 0x1c;
57153bfe38SJanne Huttunen case 6:
58153bfe38SJanne Huttunen return 0x1d;
59153bfe38SJanne Huttunen case 7:
60153bfe38SJanne Huttunen return 0x1e;
61153bfe38SJanne Huttunen case 8:
62153bfe38SJanne Huttunen return 0x1f;
63153bfe38SJanne Huttunen default:
64153bfe38SJanne Huttunen return -1;
65153bfe38SJanne Huttunen }
66153bfe38SJanne Huttunen }
67153bfe38SJanne Huttunen
__cvmx_pko_iport_config(int pko_port)68153bfe38SJanne Huttunen static void __cvmx_pko_iport_config(int pko_port)
69153bfe38SJanne Huttunen {
70153bfe38SJanne Huttunen int queue;
71153bfe38SJanne Huttunen const int num_queues = 1;
72153bfe38SJanne Huttunen const int base_queue = pko_port;
73153bfe38SJanne Huttunen const int static_priority_end = 1;
74153bfe38SJanne Huttunen const int static_priority_base = 1;
75153bfe38SJanne Huttunen
76153bfe38SJanne Huttunen for (queue = 0; queue < num_queues; queue++) {
77153bfe38SJanne Huttunen union cvmx_pko_mem_iqueue_ptrs config;
78153bfe38SJanne Huttunen cvmx_cmd_queue_result_t cmd_res;
79153bfe38SJanne Huttunen uint64_t *buf_ptr;
80153bfe38SJanne Huttunen
81153bfe38SJanne Huttunen config.u64 = 0;
82153bfe38SJanne Huttunen config.s.index = queue;
83153bfe38SJanne Huttunen config.s.qid = base_queue + queue;
84153bfe38SJanne Huttunen config.s.ipid = pko_port;
85153bfe38SJanne Huttunen config.s.tail = (queue == (num_queues - 1));
86153bfe38SJanne Huttunen config.s.s_tail = (queue == static_priority_end);
87153bfe38SJanne Huttunen config.s.static_p = (static_priority_base >= 0);
88153bfe38SJanne Huttunen config.s.static_q = (queue <= static_priority_end);
89153bfe38SJanne Huttunen config.s.qos_mask = 0xff;
90153bfe38SJanne Huttunen
91153bfe38SJanne Huttunen cmd_res = cvmx_cmd_queue_initialize(
92153bfe38SJanne Huttunen CVMX_CMD_QUEUE_PKO(base_queue + queue),
93153bfe38SJanne Huttunen CVMX_PKO_MAX_QUEUE_DEPTH,
94153bfe38SJanne Huttunen CVMX_FPA_OUTPUT_BUFFER_POOL,
95153bfe38SJanne Huttunen (CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE -
96153bfe38SJanne Huttunen CVMX_PKO_COMMAND_BUFFER_SIZE_ADJUST * 8));
97153bfe38SJanne Huttunen
98153bfe38SJanne Huttunen WARN(cmd_res,
99153bfe38SJanne Huttunen "%s: cmd_res=%d pko_port=%d base_queue=%d num_queues=%d queue=%d\n",
100153bfe38SJanne Huttunen __func__, (int)cmd_res, pko_port, base_queue,
101153bfe38SJanne Huttunen num_queues, queue);
102153bfe38SJanne Huttunen
103153bfe38SJanne Huttunen buf_ptr = (uint64_t *)cvmx_cmd_queue_buffer(
104153bfe38SJanne Huttunen CVMX_CMD_QUEUE_PKO(base_queue + queue));
105153bfe38SJanne Huttunen config.s.buf_ptr = cvmx_ptr_to_phys(buf_ptr) >> 7;
106153bfe38SJanne Huttunen CVMX_SYNCWS;
107153bfe38SJanne Huttunen cvmx_write_csr(CVMX_PKO_MEM_IQUEUE_PTRS, config.u64);
108153bfe38SJanne Huttunen }
109153bfe38SJanne Huttunen }
110153bfe38SJanne Huttunen
__cvmx_pko_queue_alloc_o68(void)111153bfe38SJanne Huttunen static void __cvmx_pko_queue_alloc_o68(void)
112153bfe38SJanne Huttunen {
113153bfe38SJanne Huttunen int port;
114153bfe38SJanne Huttunen
115153bfe38SJanne Huttunen for (port = 0; port < 48; port++)
116153bfe38SJanne Huttunen __cvmx_pko_iport_config(port);
117153bfe38SJanne Huttunen }
118153bfe38SJanne Huttunen
__cvmx_pko_port_map_o68(void)119153bfe38SJanne Huttunen static void __cvmx_pko_port_map_o68(void)
120153bfe38SJanne Huttunen {
121153bfe38SJanne Huttunen int port;
122153bfe38SJanne Huttunen int interface, index;
123153bfe38SJanne Huttunen cvmx_helper_interface_mode_t mode;
124153bfe38SJanne Huttunen union cvmx_pko_mem_iport_ptrs config;
125153bfe38SJanne Huttunen
126153bfe38SJanne Huttunen /*
127153bfe38SJanne Huttunen * Initialize every iport with the invalid eid.
128153bfe38SJanne Huttunen */
129153bfe38SJanne Huttunen config.u64 = 0;
130153bfe38SJanne Huttunen config.s.eid = 31; /* Invalid */
131153bfe38SJanne Huttunen for (port = 0; port < 128; port++) {
132153bfe38SJanne Huttunen config.s.ipid = port;
133153bfe38SJanne Huttunen cvmx_write_csr(CVMX_PKO_MEM_IPORT_PTRS, config.u64);
134153bfe38SJanne Huttunen }
135153bfe38SJanne Huttunen
136153bfe38SJanne Huttunen /*
137153bfe38SJanne Huttunen * Set up PKO_MEM_IPORT_PTRS
138153bfe38SJanne Huttunen */
139153bfe38SJanne Huttunen for (port = 0; port < 48; port++) {
140153bfe38SJanne Huttunen interface = cvmx_helper_get_interface_num(port);
141153bfe38SJanne Huttunen index = cvmx_helper_get_interface_index_num(port);
142153bfe38SJanne Huttunen mode = cvmx_helper_interface_get_mode(interface);
143153bfe38SJanne Huttunen if (mode == CVMX_HELPER_INTERFACE_MODE_DISABLED)
144153bfe38SJanne Huttunen continue;
145153bfe38SJanne Huttunen
146153bfe38SJanne Huttunen config.s.ipid = port;
147153bfe38SJanne Huttunen config.s.qos_mask = 0xff;
148153bfe38SJanne Huttunen config.s.crc = 1;
149153bfe38SJanne Huttunen config.s.min_pkt = 1;
150153bfe38SJanne Huttunen config.s.intr = __cvmx_pko_int(interface, index);
151153bfe38SJanne Huttunen config.s.eid = config.s.intr;
152153bfe38SJanne Huttunen config.s.pipe = (mode == CVMX_HELPER_INTERFACE_MODE_LOOP) ?
153153bfe38SJanne Huttunen index : port;
154153bfe38SJanne Huttunen cvmx_write_csr(CVMX_PKO_MEM_IPORT_PTRS, config.u64);
155153bfe38SJanne Huttunen }
156153bfe38SJanne Huttunen }
157153bfe38SJanne Huttunen
__cvmx_pko_chip_init(void)158153bfe38SJanne Huttunen static void __cvmx_pko_chip_init(void)
159153bfe38SJanne Huttunen {
160153bfe38SJanne Huttunen int i;
161153bfe38SJanne Huttunen
162153bfe38SJanne Huttunen if (OCTEON_IS_MODEL(OCTEON_CN68XX)) {
163153bfe38SJanne Huttunen __cvmx_pko_port_map_o68();
164153bfe38SJanne Huttunen __cvmx_pko_queue_alloc_o68();
165153bfe38SJanne Huttunen return;
166153bfe38SJanne Huttunen }
167153bfe38SJanne Huttunen
168153bfe38SJanne Huttunen /*
169153bfe38SJanne Huttunen * Initialize queues
170153bfe38SJanne Huttunen */
171153bfe38SJanne Huttunen for (i = 0; i < CVMX_PKO_MAX_OUTPUT_QUEUES; i++) {
172153bfe38SJanne Huttunen const uint64_t priority = 8;
173153bfe38SJanne Huttunen
174153bfe38SJanne Huttunen cvmx_pko_config_port(CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID, i, 1,
175153bfe38SJanne Huttunen &priority);
176153bfe38SJanne Huttunen }
177153bfe38SJanne Huttunen }
178153bfe38SJanne Huttunen
17916df55ceSRandy Dunlap /*
180af866496SDavid Daney * Call before any other calls to initialize the packet
181af866496SDavid Daney * output system. This does chip global config, and should only be
182af866496SDavid Daney * done by one core.
183af866496SDavid Daney */
184af866496SDavid Daney
cvmx_pko_initialize_global(void)185af866496SDavid Daney void cvmx_pko_initialize_global(void)
186af866496SDavid Daney {
187af866496SDavid Daney union cvmx_pko_reg_cmd_buf config;
188af866496SDavid Daney
189af866496SDavid Daney /*
190af866496SDavid Daney * Set the size of the PKO command buffers to an odd number of
191af866496SDavid Daney * 64bit words. This allows the normal two word send to stay
19292a76f6dSAdam Buchbinder * aligned and never span a command word buffer.
193af866496SDavid Daney */
194af866496SDavid Daney config.u64 = 0;
195af866496SDavid Daney config.s.pool = CVMX_FPA_OUTPUT_BUFFER_POOL;
196af866496SDavid Daney config.s.size = CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE / 8 - 1;
197af866496SDavid Daney
198af866496SDavid Daney cvmx_write_csr(CVMX_PKO_REG_CMD_BUF, config.u64);
199af866496SDavid Daney
200153bfe38SJanne Huttunen /*
201153bfe38SJanne Huttunen * Chip-specific setup.
202153bfe38SJanne Huttunen */
203153bfe38SJanne Huttunen __cvmx_pko_chip_init();
204af866496SDavid Daney
205af866496SDavid Daney /*
206af866496SDavid Daney * If we aren't using all of the queues optimize PKO's
207af866496SDavid Daney * internal memory.
208af866496SDavid Daney */
209af866496SDavid Daney if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)
210af866496SDavid Daney || OCTEON_IS_MODEL(OCTEON_CN56XX)
211af866496SDavid Daney || OCTEON_IS_MODEL(OCTEON_CN52XX)) {
212af866496SDavid Daney int num_interfaces = cvmx_helper_get_number_of_interfaces();
213af866496SDavid Daney int last_port =
214af866496SDavid Daney cvmx_helper_get_last_ipd_port(num_interfaces - 1);
215af866496SDavid Daney int max_queues =
216af866496SDavid Daney cvmx_pko_get_base_queue(last_port) +
217af866496SDavid Daney cvmx_pko_get_num_queues(last_port);
218af866496SDavid Daney if (OCTEON_IS_MODEL(OCTEON_CN38XX)) {
219af866496SDavid Daney if (max_queues <= 32)
220af866496SDavid Daney cvmx_write_csr(CVMX_PKO_REG_QUEUE_MODE, 2);
221af866496SDavid Daney else if (max_queues <= 64)
222af866496SDavid Daney cvmx_write_csr(CVMX_PKO_REG_QUEUE_MODE, 1);
223af866496SDavid Daney } else {
224af866496SDavid Daney if (max_queues <= 64)
225af866496SDavid Daney cvmx_write_csr(CVMX_PKO_REG_QUEUE_MODE, 2);
226af866496SDavid Daney else if (max_queues <= 128)
227af866496SDavid Daney cvmx_write_csr(CVMX_PKO_REG_QUEUE_MODE, 1);
228af866496SDavid Daney }
229af866496SDavid Daney }
230af866496SDavid Daney }
231af866496SDavid Daney
23216df55ceSRandy Dunlap /*
233af866496SDavid Daney * Enables the packet output hardware. It must already be
234af866496SDavid Daney * configured.
235af866496SDavid Daney */
cvmx_pko_enable(void)236af866496SDavid Daney void cvmx_pko_enable(void)
237af866496SDavid Daney {
238af866496SDavid Daney union cvmx_pko_reg_flags flags;
239af866496SDavid Daney
240af866496SDavid Daney flags.u64 = cvmx_read_csr(CVMX_PKO_REG_FLAGS);
241af866496SDavid Daney if (flags.s.ena_pko)
242af866496SDavid Daney cvmx_dprintf
243af866496SDavid Daney ("Warning: Enabling PKO when PKO already enabled.\n");
244af866496SDavid Daney
245af866496SDavid Daney flags.s.ena_dwb = 1;
246af866496SDavid Daney flags.s.ena_pko = 1;
247af866496SDavid Daney /*
248af866496SDavid Daney * always enable big endian for 3-word command. Does nothing
249af866496SDavid Daney * for 2-word.
250af866496SDavid Daney */
251af866496SDavid Daney flags.s.store_be = 1;
252af866496SDavid Daney cvmx_write_csr(CVMX_PKO_REG_FLAGS, flags.u64);
253af866496SDavid Daney }
254af866496SDavid Daney
25516df55ceSRandy Dunlap /*
256af866496SDavid Daney * Disables the packet output. Does not affect any configuration.
257af866496SDavid Daney */
cvmx_pko_disable(void)258af866496SDavid Daney void cvmx_pko_disable(void)
259af866496SDavid Daney {
260af866496SDavid Daney union cvmx_pko_reg_flags pko_reg_flags;
261af866496SDavid Daney pko_reg_flags.u64 = cvmx_read_csr(CVMX_PKO_REG_FLAGS);
262af866496SDavid Daney pko_reg_flags.s.ena_pko = 0;
263af866496SDavid Daney cvmx_write_csr(CVMX_PKO_REG_FLAGS, pko_reg_flags.u64);
264af866496SDavid Daney }
265ce4126cbSAaro Koskinen EXPORT_SYMBOL_GPL(cvmx_pko_disable);
266af866496SDavid Daney
26716df55ceSRandy Dunlap /*
268af866496SDavid Daney * Reset the packet output.
269af866496SDavid Daney */
__cvmx_pko_reset(void)270af866496SDavid Daney static void __cvmx_pko_reset(void)
271af866496SDavid Daney {
272af866496SDavid Daney union cvmx_pko_reg_flags pko_reg_flags;
273af866496SDavid Daney pko_reg_flags.u64 = cvmx_read_csr(CVMX_PKO_REG_FLAGS);
274af866496SDavid Daney pko_reg_flags.s.reset = 1;
275af866496SDavid Daney cvmx_write_csr(CVMX_PKO_REG_FLAGS, pko_reg_flags.u64);
276af866496SDavid Daney }
277af866496SDavid Daney
27816df55ceSRandy Dunlap /*
279af866496SDavid Daney * Shutdown and free resources required by packet output.
280af866496SDavid Daney */
cvmx_pko_shutdown(void)281af866496SDavid Daney void cvmx_pko_shutdown(void)
282af866496SDavid Daney {
283af866496SDavid Daney union cvmx_pko_mem_queue_ptrs config;
284af866496SDavid Daney int queue;
285af866496SDavid Daney
286af866496SDavid Daney cvmx_pko_disable();
287af866496SDavid Daney
288af866496SDavid Daney for (queue = 0; queue < CVMX_PKO_MAX_OUTPUT_QUEUES; queue++) {
289af866496SDavid Daney config.u64 = 0;
290af866496SDavid Daney config.s.tail = 1;
291af866496SDavid Daney config.s.index = 0;
292af866496SDavid Daney config.s.port = CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID;
293af866496SDavid Daney config.s.queue = queue & 0x7f;
294af866496SDavid Daney config.s.qos_mask = 0;
295af866496SDavid Daney config.s.buf_ptr = 0;
296af866496SDavid Daney if (!OCTEON_IS_MODEL(OCTEON_CN3XXX)) {
297af866496SDavid Daney union cvmx_pko_reg_queue_ptrs1 config1;
298af866496SDavid Daney config1.u64 = 0;
299af866496SDavid Daney config1.s.qid7 = queue >> 7;
300af866496SDavid Daney cvmx_write_csr(CVMX_PKO_REG_QUEUE_PTRS1, config1.u64);
301af866496SDavid Daney }
302af866496SDavid Daney cvmx_write_csr(CVMX_PKO_MEM_QUEUE_PTRS, config.u64);
303af866496SDavid Daney cvmx_cmd_queue_shutdown(CVMX_CMD_QUEUE_PKO(queue));
304af866496SDavid Daney }
305af866496SDavid Daney __cvmx_pko_reset();
306af866496SDavid Daney }
307ce4126cbSAaro Koskinen EXPORT_SYMBOL_GPL(cvmx_pko_shutdown);
308af866496SDavid Daney
30916df55ceSRandy Dunlap /*
310af866496SDavid Daney * Configure a output port and the associated queues for use.
311af866496SDavid Daney *
312af866496SDavid Daney * @port: Port to configure.
313af866496SDavid Daney * @base_queue: First queue number to associate with this port.
314af866496SDavid Daney * @num_queues: Number of queues to associate with this port
315af866496SDavid Daney * @priority: Array of priority levels for each queue. Values are
316af866496SDavid Daney * allowed to be 0-8. A value of 8 get 8 times the traffic
317af866496SDavid Daney * of a value of 1. A value of 0 indicates that no rounds
318af866496SDavid Daney * will be participated in. These priorities can be changed
319af866496SDavid Daney * on the fly while the pko is enabled. A priority of 9
320af866496SDavid Daney * indicates that static priority should be used. If static
321af866496SDavid Daney * priority is used all queues with static priority must be
322af866496SDavid Daney * contiguous starting at the base_queue, and lower numbered
323af866496SDavid Daney * queues have higher priority than higher numbered queues.
324af866496SDavid Daney * There must be num_queues elements in the array.
325af866496SDavid Daney */
cvmx_pko_config_port(uint64_t port,uint64_t base_queue,uint64_t num_queues,const uint64_t priority[])326af866496SDavid Daney cvmx_pko_status_t cvmx_pko_config_port(uint64_t port, uint64_t base_queue,
327af866496SDavid Daney uint64_t num_queues,
328af866496SDavid Daney const uint64_t priority[])
329af866496SDavid Daney {
330af866496SDavid Daney cvmx_pko_status_t result_code;
331af866496SDavid Daney uint64_t queue;
332af866496SDavid Daney union cvmx_pko_mem_queue_ptrs config;
333af866496SDavid Daney union cvmx_pko_reg_queue_ptrs1 config1;
334af866496SDavid Daney int static_priority_base = -1;
335af866496SDavid Daney int static_priority_end = -1;
336af866496SDavid Daney
337153bfe38SJanne Huttunen if (OCTEON_IS_MODEL(OCTEON_CN68XX))
338153bfe38SJanne Huttunen return CVMX_PKO_SUCCESS;
339153bfe38SJanne Huttunen
340af866496SDavid Daney if ((port >= CVMX_PKO_NUM_OUTPUT_PORTS)
341af866496SDavid Daney && (port != CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID)) {
342af866496SDavid Daney cvmx_dprintf("ERROR: cvmx_pko_config_port: Invalid port %llu\n",
343af866496SDavid Daney (unsigned long long)port);
344af866496SDavid Daney return CVMX_PKO_INVALID_PORT;
345af866496SDavid Daney }
346af866496SDavid Daney
347af866496SDavid Daney if (base_queue + num_queues > CVMX_PKO_MAX_OUTPUT_QUEUES) {
348af866496SDavid Daney cvmx_dprintf
349af866496SDavid Daney ("ERROR: cvmx_pko_config_port: Invalid queue range %llu\n",
350af866496SDavid Daney (unsigned long long)(base_queue + num_queues));
351af866496SDavid Daney return CVMX_PKO_INVALID_QUEUE;
352af866496SDavid Daney }
353af866496SDavid Daney
354af866496SDavid Daney if (port != CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID) {
355af866496SDavid Daney /*
356af866496SDavid Daney * Validate the static queue priority setup and set
357af866496SDavid Daney * static_priority_base and static_priority_end
358af866496SDavid Daney * accordingly.
359af866496SDavid Daney */
360af866496SDavid Daney for (queue = 0; queue < num_queues; queue++) {
361af866496SDavid Daney /* Find first queue of static priority */
362af866496SDavid Daney if (static_priority_base == -1
363af866496SDavid Daney && priority[queue] ==
364af866496SDavid Daney CVMX_PKO_QUEUE_STATIC_PRIORITY)
365af866496SDavid Daney static_priority_base = queue;
366af866496SDavid Daney /* Find last queue of static priority */
367af866496SDavid Daney if (static_priority_base != -1
368af866496SDavid Daney && static_priority_end == -1
369af866496SDavid Daney && priority[queue] != CVMX_PKO_QUEUE_STATIC_PRIORITY
370af866496SDavid Daney && queue)
371af866496SDavid Daney static_priority_end = queue - 1;
372af866496SDavid Daney else if (static_priority_base != -1
373af866496SDavid Daney && static_priority_end == -1
374af866496SDavid Daney && queue == num_queues - 1)
375af866496SDavid Daney /* all queues are static priority */
376af866496SDavid Daney static_priority_end = queue;
377af866496SDavid Daney /*
378af866496SDavid Daney * Check to make sure all static priority
379af866496SDavid Daney * queues are contiguous. Also catches some
380*94bd83e4SJulia Lawall * cases of static priorities not starting at
381af866496SDavid Daney * queue 0.
382af866496SDavid Daney */
383af866496SDavid Daney if (static_priority_end != -1
384af866496SDavid Daney && (int)queue > static_priority_end
385af866496SDavid Daney && priority[queue] ==
386af866496SDavid Daney CVMX_PKO_QUEUE_STATIC_PRIORITY) {
387af866496SDavid Daney cvmx_dprintf("ERROR: cvmx_pko_config_port: "
388af866496SDavid Daney "Static priority queues aren't "
389af866496SDavid Daney "contiguous or don't start at "
390af866496SDavid Daney "base queue. q: %d, eq: %d\n",
391af866496SDavid Daney (int)queue, static_priority_end);
392af866496SDavid Daney return CVMX_PKO_INVALID_PRIORITY;
393af866496SDavid Daney }
394af866496SDavid Daney }
395af866496SDavid Daney if (static_priority_base > 0) {
396af866496SDavid Daney cvmx_dprintf("ERROR: cvmx_pko_config_port: Static "
397af866496SDavid Daney "priority queues don't start at base "
398af866496SDavid Daney "queue. sq: %d\n",
399af866496SDavid Daney static_priority_base);
400af866496SDavid Daney return CVMX_PKO_INVALID_PRIORITY;
401af866496SDavid Daney }
402af866496SDavid Daney #if 0
403af866496SDavid Daney cvmx_dprintf("Port %d: Static priority queue base: %d, "
404af866496SDavid Daney "end: %d\n", port,
405af866496SDavid Daney static_priority_base, static_priority_end);
406af866496SDavid Daney #endif
407af866496SDavid Daney }
408af866496SDavid Daney /*
409af866496SDavid Daney * At this point, static_priority_base and static_priority_end
410af866496SDavid Daney * are either both -1, or are valid start/end queue
411af866496SDavid Daney * numbers.
412af866496SDavid Daney */
413af866496SDavid Daney
414af866496SDavid Daney result_code = CVMX_PKO_SUCCESS;
415af866496SDavid Daney
416af866496SDavid Daney #ifdef PKO_DEBUG
417af866496SDavid Daney cvmx_dprintf("num queues: %d (%lld,%lld)\n", num_queues,
418af866496SDavid Daney CVMX_PKO_QUEUES_PER_PORT_INTERFACE0,
419af866496SDavid Daney CVMX_PKO_QUEUES_PER_PORT_INTERFACE1);
420af866496SDavid Daney #endif
421af866496SDavid Daney
422af866496SDavid Daney for (queue = 0; queue < num_queues; queue++) {
423af866496SDavid Daney uint64_t *buf_ptr = NULL;
424af866496SDavid Daney
425af866496SDavid Daney config1.u64 = 0;
426af866496SDavid Daney config1.s.idx3 = queue >> 3;
427af866496SDavid Daney config1.s.qid7 = (base_queue + queue) >> 7;
428af866496SDavid Daney
429af866496SDavid Daney config.u64 = 0;
430af866496SDavid Daney config.s.tail = queue == (num_queues - 1);
431af866496SDavid Daney config.s.index = queue;
432af866496SDavid Daney config.s.port = port;
433af866496SDavid Daney config.s.queue = base_queue + queue;
434af866496SDavid Daney
435af866496SDavid Daney if (!cvmx_octeon_is_pass1()) {
436af866496SDavid Daney config.s.static_p = static_priority_base >= 0;
437af866496SDavid Daney config.s.static_q = (int)queue <= static_priority_end;
438af866496SDavid Daney config.s.s_tail = (int)queue == static_priority_end;
439af866496SDavid Daney }
440af866496SDavid Daney /*
441af866496SDavid Daney * Convert the priority into an enable bit field. Try
442af866496SDavid Daney * to space the bits out evenly so the packet don't
443af866496SDavid Daney * get grouped up
444af866496SDavid Daney */
445af866496SDavid Daney switch ((int)priority[queue]) {
446af866496SDavid Daney case 0:
447af866496SDavid Daney config.s.qos_mask = 0x00;
448af866496SDavid Daney break;
449af866496SDavid Daney case 1:
450af866496SDavid Daney config.s.qos_mask = 0x01;
451af866496SDavid Daney break;
452af866496SDavid Daney case 2:
453af866496SDavid Daney config.s.qos_mask = 0x11;
454af866496SDavid Daney break;
455af866496SDavid Daney case 3:
456af866496SDavid Daney config.s.qos_mask = 0x49;
457af866496SDavid Daney break;
458af866496SDavid Daney case 4:
459af866496SDavid Daney config.s.qos_mask = 0x55;
460af866496SDavid Daney break;
461af866496SDavid Daney case 5:
462af866496SDavid Daney config.s.qos_mask = 0x57;
463af866496SDavid Daney break;
464af866496SDavid Daney case 6:
465af866496SDavid Daney config.s.qos_mask = 0x77;
466af866496SDavid Daney break;
467af866496SDavid Daney case 7:
468af866496SDavid Daney config.s.qos_mask = 0x7f;
469af866496SDavid Daney break;
470af866496SDavid Daney case 8:
471af866496SDavid Daney config.s.qos_mask = 0xff;
472af866496SDavid Daney break;
473af866496SDavid Daney case CVMX_PKO_QUEUE_STATIC_PRIORITY:
474af866496SDavid Daney if (!cvmx_octeon_is_pass1()) {
475af866496SDavid Daney config.s.qos_mask = 0xff;
476af866496SDavid Daney break;
477af866496SDavid Daney }
478c9b02990SLiangliang Huang fallthrough; /* to the error case, when Pass 1 */
479af866496SDavid Daney default:
480af866496SDavid Daney cvmx_dprintf("ERROR: cvmx_pko_config_port: Invalid "
481af866496SDavid Daney "priority %llu\n",
482af866496SDavid Daney (unsigned long long)priority[queue]);
483af866496SDavid Daney config.s.qos_mask = 0xff;
484af866496SDavid Daney result_code = CVMX_PKO_INVALID_PRIORITY;
485af866496SDavid Daney break;
486af866496SDavid Daney }
487af866496SDavid Daney
488af866496SDavid Daney if (port != CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID) {
489af866496SDavid Daney cvmx_cmd_queue_result_t cmd_res =
490af866496SDavid Daney cvmx_cmd_queue_initialize(CVMX_CMD_QUEUE_PKO
491af866496SDavid Daney (base_queue + queue),
492af866496SDavid Daney CVMX_PKO_MAX_QUEUE_DEPTH,
493af866496SDavid Daney CVMX_FPA_OUTPUT_BUFFER_POOL,
494af866496SDavid Daney CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE
495af866496SDavid Daney -
496af866496SDavid Daney CVMX_PKO_COMMAND_BUFFER_SIZE_ADJUST
497af866496SDavid Daney * 8);
498af866496SDavid Daney if (cmd_res != CVMX_CMD_QUEUE_SUCCESS) {
499af866496SDavid Daney switch (cmd_res) {
500af866496SDavid Daney case CVMX_CMD_QUEUE_NO_MEMORY:
501af866496SDavid Daney cvmx_dprintf("ERROR: "
502af866496SDavid Daney "cvmx_pko_config_port: "
503af866496SDavid Daney "Unable to allocate "
504af866496SDavid Daney "output buffer.\n");
505af866496SDavid Daney return CVMX_PKO_NO_MEMORY;
506af866496SDavid Daney case CVMX_CMD_QUEUE_ALREADY_SETUP:
507af866496SDavid Daney cvmx_dprintf
508af866496SDavid Daney ("ERROR: cvmx_pko_config_port: Port already setup.\n");
509af866496SDavid Daney return CVMX_PKO_PORT_ALREADY_SETUP;
510af866496SDavid Daney case CVMX_CMD_QUEUE_INVALID_PARAM:
511af866496SDavid Daney default:
512af866496SDavid Daney cvmx_dprintf
513af866496SDavid Daney ("ERROR: cvmx_pko_config_port: Command queue initialization failed.\n");
514af866496SDavid Daney return CVMX_PKO_CMD_QUEUE_INIT_ERROR;
515af866496SDavid Daney }
516af866496SDavid Daney }
517af866496SDavid Daney
518af866496SDavid Daney buf_ptr =
519af866496SDavid Daney (uint64_t *)
520af866496SDavid Daney cvmx_cmd_queue_buffer(CVMX_CMD_QUEUE_PKO
521af866496SDavid Daney (base_queue + queue));
522af866496SDavid Daney config.s.buf_ptr = cvmx_ptr_to_phys(buf_ptr);
523af866496SDavid Daney } else
524af866496SDavid Daney config.s.buf_ptr = 0;
525af866496SDavid Daney
526af866496SDavid Daney CVMX_SYNCWS;
527af866496SDavid Daney
528af866496SDavid Daney if (!OCTEON_IS_MODEL(OCTEON_CN3XXX))
529af866496SDavid Daney cvmx_write_csr(CVMX_PKO_REG_QUEUE_PTRS1, config1.u64);
530af866496SDavid Daney cvmx_write_csr(CVMX_PKO_MEM_QUEUE_PTRS, config.u64);
531af866496SDavid Daney }
532af866496SDavid Daney
533af866496SDavid Daney return result_code;
534af866496SDavid Daney }
535af866496SDavid Daney
536af866496SDavid Daney #ifdef PKO_DEBUG
53716df55ceSRandy Dunlap /*
538af866496SDavid Daney * Show map of ports -> queues for different cores.
539af866496SDavid Daney */
cvmx_pko_show_queue_map()540af866496SDavid Daney void cvmx_pko_show_queue_map()
541af866496SDavid Daney {
542af866496SDavid Daney int core, port;
543af866496SDavid Daney int pko_output_ports = 36;
544af866496SDavid Daney
545af866496SDavid Daney cvmx_dprintf("port");
546af866496SDavid Daney for (port = 0; port < pko_output_ports; port++)
547af866496SDavid Daney cvmx_dprintf("%3d ", port);
548af866496SDavid Daney cvmx_dprintf("\n");
549af866496SDavid Daney
550af866496SDavid Daney for (core = 0; core < CVMX_MAX_CORES; core++) {
551af866496SDavid Daney cvmx_dprintf("\n%2d: ", core);
552af866496SDavid Daney for (port = 0; port < pko_output_ports; port++) {
553af866496SDavid Daney cvmx_dprintf("%3d ",
554af866496SDavid Daney cvmx_pko_get_base_queue_per_core(port,
555af866496SDavid Daney core));
556af866496SDavid Daney }
557af866496SDavid Daney }
558af866496SDavid Daney cvmx_dprintf("\n");
559af866496SDavid Daney }
560af866496SDavid Daney #endif
561af866496SDavid Daney
56216df55ceSRandy Dunlap /*
563af866496SDavid Daney * Rate limit a PKO port to a max packets/sec. This function is only
564af866496SDavid Daney * supported on CN51XX and higher, excluding CN58XX.
565af866496SDavid Daney *
566af866496SDavid Daney * @port: Port to rate limit
567af866496SDavid Daney * @packets_s: Maximum packet/sec
568af866496SDavid Daney * @burst: Maximum number of packets to burst in a row before rate
569af866496SDavid Daney * limiting cuts in.
570af866496SDavid Daney *
571af866496SDavid Daney * Returns Zero on success, negative on failure
572af866496SDavid Daney */
cvmx_pko_rate_limit_packets(int port,int packets_s,int burst)573af866496SDavid Daney int cvmx_pko_rate_limit_packets(int port, int packets_s, int burst)
574af866496SDavid Daney {
575af866496SDavid Daney union cvmx_pko_mem_port_rate0 pko_mem_port_rate0;
576af866496SDavid Daney union cvmx_pko_mem_port_rate1 pko_mem_port_rate1;
577af866496SDavid Daney
578af866496SDavid Daney pko_mem_port_rate0.u64 = 0;
579af866496SDavid Daney pko_mem_port_rate0.s.pid = port;
580af866496SDavid Daney pko_mem_port_rate0.s.rate_pkt =
581af866496SDavid Daney cvmx_sysinfo_get()->cpu_clock_hz / packets_s / 16;
582af866496SDavid Daney /* No cost per word since we are limited by packets/sec, not bits/sec */
583af866496SDavid Daney pko_mem_port_rate0.s.rate_word = 0;
584af866496SDavid Daney
585af866496SDavid Daney pko_mem_port_rate1.u64 = 0;
586af866496SDavid Daney pko_mem_port_rate1.s.pid = port;
587af866496SDavid Daney pko_mem_port_rate1.s.rate_lim =
588af866496SDavid Daney ((uint64_t) pko_mem_port_rate0.s.rate_pkt * burst) >> 8;
589af866496SDavid Daney
590af866496SDavid Daney cvmx_write_csr(CVMX_PKO_MEM_PORT_RATE0, pko_mem_port_rate0.u64);
591af866496SDavid Daney cvmx_write_csr(CVMX_PKO_MEM_PORT_RATE1, pko_mem_port_rate1.u64);
592af866496SDavid Daney return 0;
593af866496SDavid Daney }
594af866496SDavid Daney
59516df55ceSRandy Dunlap /*
596af866496SDavid Daney * Rate limit a PKO port to a max bits/sec. This function is only
597af866496SDavid Daney * supported on CN51XX and higher, excluding CN58XX.
598af866496SDavid Daney *
599af866496SDavid Daney * @port: Port to rate limit
600af866496SDavid Daney * @bits_s: PKO rate limit in bits/sec
601af866496SDavid Daney * @burst: Maximum number of bits to burst before rate
602af866496SDavid Daney * limiting cuts in.
603af866496SDavid Daney *
604af866496SDavid Daney * Returns Zero on success, negative on failure
605af866496SDavid Daney */
cvmx_pko_rate_limit_bits(int port,uint64_t bits_s,int burst)606af866496SDavid Daney int cvmx_pko_rate_limit_bits(int port, uint64_t bits_s, int burst)
607af866496SDavid Daney {
608af866496SDavid Daney union cvmx_pko_mem_port_rate0 pko_mem_port_rate0;
609af866496SDavid Daney union cvmx_pko_mem_port_rate1 pko_mem_port_rate1;
610af866496SDavid Daney uint64_t clock_rate = cvmx_sysinfo_get()->cpu_clock_hz;
611af866496SDavid Daney uint64_t tokens_per_bit = clock_rate * 16 / bits_s;
612af866496SDavid Daney
613af866496SDavid Daney pko_mem_port_rate0.u64 = 0;
614af866496SDavid Daney pko_mem_port_rate0.s.pid = port;
615af866496SDavid Daney /*
616af866496SDavid Daney * Each packet has a 12 bytes of interframe gap, an 8 byte
617af866496SDavid Daney * preamble, and a 4 byte CRC. These are not included in the
618af866496SDavid Daney * per word count. Multiply by 8 to covert to bits and divide
619af866496SDavid Daney * by 256 for limit granularity.
620af866496SDavid Daney */
621af866496SDavid Daney pko_mem_port_rate0.s.rate_pkt = (12 + 8 + 4) * 8 * tokens_per_bit / 256;
622af866496SDavid Daney /* Each 8 byte word has 64bits */
623af866496SDavid Daney pko_mem_port_rate0.s.rate_word = 64 * tokens_per_bit;
624af866496SDavid Daney
625af866496SDavid Daney pko_mem_port_rate1.u64 = 0;
626af866496SDavid Daney pko_mem_port_rate1.s.pid = port;
627af866496SDavid Daney pko_mem_port_rate1.s.rate_lim = tokens_per_bit * burst / 256;
628af866496SDavid Daney
629af866496SDavid Daney cvmx_write_csr(CVMX_PKO_MEM_PORT_RATE0, pko_mem_port_rate0.u64);
630af866496SDavid Daney cvmx_write_csr(CVMX_PKO_MEM_PORT_RATE1, pko_mem_port_rate1.u64);
631af866496SDavid Daney return 0;
632af866496SDavid Daney }
633