1 /***********************license start***************
2  * Author: Cavium Networks
3  *
4  * Contact: support@caviumnetworks.com
5  * This file is part of the OCTEON SDK
6  *
7  * Copyright (c) 2003-2008 Cavium Networks
8  *
9  * This file is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License, Version 2, as
11  * published by the Free Software Foundation.
12  *
13  * This file is distributed in the hope that it will be useful, but
14  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16  * NONINFRINGEMENT.  See the GNU General Public License for more
17  * details.
18  *
19  * You should have received a copy of the GNU General Public License
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21  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22  * or visit http://www.gnu.org/licenses/.
23  *
24  * This file may also be available under a different license from Cavium.
25  * Contact Cavium Networks for more information
26  ***********************license end**************************************/
27 
28 /*
29  * Functions for XAUI initialization, configuration,
30  * and monitoring.
31  *
32  */
33 
34 #include <asm/octeon/octeon.h>
35 
36 #include <asm/octeon/cvmx-config.h>
37 
38 #include <asm/octeon/cvmx-helper.h>
39 
40 #include <asm/octeon/cvmx-pko-defs.h>
41 #include <asm/octeon/cvmx-gmxx-defs.h>
42 #include <asm/octeon/cvmx-pcsxx-defs.h>
43 
44 void __cvmx_interrupt_gmxx_enable(int interface);
45 void __cvmx_interrupt_pcsx_intx_en_reg_enable(int index, int block);
46 void __cvmx_interrupt_pcsxx_int_en_reg_enable(int index);
47 
48 int __cvmx_helper_xaui_enumerate(int interface)
49 {
50 	union cvmx_gmxx_hg2_control gmx_hg2_control;
51 
52 	/* If HiGig2 is enabled return 16 ports, otherwise return 1 port */
53 	gmx_hg2_control.u64 = cvmx_read_csr(CVMX_GMXX_HG2_CONTROL(interface));
54 	if (gmx_hg2_control.s.hg2tx_en)
55 		return 16;
56 	else
57 		return 1;
58 }
59 
60 /**
61  * Probe a XAUI interface and determine the number of ports
62  * connected to it. The XAUI interface should still be down
63  * after this call.
64  *
65  * @interface: Interface to probe
66  *
67  * Returns Number of ports on the interface. Zero to disable.
68  */
69 int __cvmx_helper_xaui_probe(int interface)
70 {
71 	int i;
72 	union cvmx_gmxx_inf_mode mode;
73 
74 	/*
75 	 * Due to errata GMX-700 on CN56XXp1.x and CN52XXp1.x, the
76 	 * interface needs to be enabled before IPD otherwise per port
77 	 * backpressure may not work properly.
78 	 */
79 	mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface));
80 	mode.s.en = 1;
81 	cvmx_write_csr(CVMX_GMXX_INF_MODE(interface), mode.u64);
82 
83 	__cvmx_helper_setup_gmx(interface, 1);
84 
85 	/*
86 	 * Setup PKO to support 16 ports for HiGig2 virtual
87 	 * ports. We're pointing all of the PKO packet ports for this
88 	 * interface to the XAUI. This allows us to use HiGig2
89 	 * backpressure per port.
90 	 */
91 	for (i = 0; i < 16; i++) {
92 		union cvmx_pko_mem_port_ptrs pko_mem_port_ptrs;
93 		pko_mem_port_ptrs.u64 = 0;
94 		/*
95 		 * We set each PKO port to have equal priority in a
96 		 * round robin fashion.
97 		 */
98 		pko_mem_port_ptrs.s.static_p = 0;
99 		pko_mem_port_ptrs.s.qos_mask = 0xff;
100 		/* All PKO ports map to the same XAUI hardware port */
101 		pko_mem_port_ptrs.s.eid = interface * 4;
102 		pko_mem_port_ptrs.s.pid = interface * 16 + i;
103 		cvmx_write_csr(CVMX_PKO_MEM_PORT_PTRS, pko_mem_port_ptrs.u64);
104 	}
105 	return __cvmx_helper_xaui_enumerate(interface);
106 }
107 
108 /**
109  * Bringup and enable a XAUI interface. After this call packet
110  * I/O should be fully functional. This is called with IPD
111  * enabled but PKO disabled.
112  *
113  * @interface: Interface to bring up
114  *
115  * Returns Zero on success, negative on failure
116  */
117 int __cvmx_helper_xaui_enable(int interface)
118 {
119 	union cvmx_gmxx_prtx_cfg gmx_cfg;
120 	union cvmx_pcsxx_control1_reg xauiCtl;
121 	union cvmx_pcsxx_misc_ctl_reg xauiMiscCtl;
122 	union cvmx_gmxx_tx_xaui_ctl gmxXauiTxCtl;
123 	union cvmx_gmxx_rxx_int_en gmx_rx_int_en;
124 	union cvmx_gmxx_tx_int_en gmx_tx_int_en;
125 	union cvmx_pcsxx_int_en_reg pcsx_int_en_reg;
126 
127 	/* Setup PKND */
128 	if (octeon_has_feature(OCTEON_FEATURE_PKND)) {
129 		gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface));
130 		gmx_cfg.s.pknd = cvmx_helper_get_ipd_port(interface, 0);
131 		cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64);
132 	}
133 
134 	/* (1) Interface has already been enabled. */
135 
136 	/* (2) Disable GMX. */
137 	xauiMiscCtl.u64 = cvmx_read_csr(CVMX_PCSXX_MISC_CTL_REG(interface));
138 	xauiMiscCtl.s.gmxeno = 1;
139 	cvmx_write_csr(CVMX_PCSXX_MISC_CTL_REG(interface), xauiMiscCtl.u64);
140 
141 	/* (3) Disable GMX and PCSX interrupts. */
142 	gmx_rx_int_en.u64 = cvmx_read_csr(CVMX_GMXX_RXX_INT_EN(0, interface));
143 	cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(0, interface), 0x0);
144 	gmx_tx_int_en.u64 = cvmx_read_csr(CVMX_GMXX_TX_INT_EN(interface));
145 	cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), 0x0);
146 	pcsx_int_en_reg.u64 = cvmx_read_csr(CVMX_PCSXX_INT_EN_REG(interface));
147 	cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(interface), 0x0);
148 
149 	/* (4) Bring up the PCSX and GMX reconciliation layer. */
150 	/* (4)a Set polarity and lane swapping. */
151 	/* (4)b */
152 	gmxXauiTxCtl.u64 = cvmx_read_csr(CVMX_GMXX_TX_XAUI_CTL(interface));
153 	/* Enable better IFG packing and improves performance */
154 	gmxXauiTxCtl.s.dic_en = 1;
155 	gmxXauiTxCtl.s.uni_en = 0;
156 	cvmx_write_csr(CVMX_GMXX_TX_XAUI_CTL(interface), gmxXauiTxCtl.u64);
157 
158 	/* (4)c Aply reset sequence */
159 	xauiCtl.u64 = cvmx_read_csr(CVMX_PCSXX_CONTROL1_REG(interface));
160 	xauiCtl.s.lo_pwr = 0;
161 
162 	/* Issuing a reset here seems to hang some CN68XX chips. */
163 	if (!OCTEON_IS_MODEL(OCTEON_CN68XX_PASS1_X) &&
164 	    !OCTEON_IS_MODEL(OCTEON_CN68XX_PASS2_X))
165 		xauiCtl.s.reset = 1;
166 
167 	cvmx_write_csr(CVMX_PCSXX_CONTROL1_REG(interface), xauiCtl.u64);
168 
169 	/* Wait for PCS to come out of reset */
170 	if (CVMX_WAIT_FOR_FIELD64
171 	    (CVMX_PCSXX_CONTROL1_REG(interface), union cvmx_pcsxx_control1_reg,
172 	     reset, ==, 0, 10000))
173 		return -1;
174 	/* Wait for PCS to be aligned */
175 	if (CVMX_WAIT_FOR_FIELD64
176 	    (CVMX_PCSXX_10GBX_STATUS_REG(interface),
177 	     union cvmx_pcsxx_10gbx_status_reg, alignd, ==, 1, 10000))
178 		return -1;
179 	/* Wait for RX to be ready */
180 	if (CVMX_WAIT_FOR_FIELD64
181 	    (CVMX_GMXX_RX_XAUI_CTL(interface), union cvmx_gmxx_rx_xaui_ctl,
182 		    status, ==, 0, 10000))
183 		return -1;
184 
185 	/* (6) Configure GMX */
186 	gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface));
187 	gmx_cfg.s.en = 0;
188 	cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64);
189 
190 	/* Wait for GMX RX to be idle */
191 	if (CVMX_WAIT_FOR_FIELD64
192 	    (CVMX_GMXX_PRTX_CFG(0, interface), union cvmx_gmxx_prtx_cfg,
193 		    rx_idle, ==, 1, 10000))
194 		return -1;
195 	/* Wait for GMX TX to be idle */
196 	if (CVMX_WAIT_FOR_FIELD64
197 	    (CVMX_GMXX_PRTX_CFG(0, interface), union cvmx_gmxx_prtx_cfg,
198 		    tx_idle, ==, 1, 10000))
199 		return -1;
200 
201 	/* GMX configure */
202 	gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface));
203 	gmx_cfg.s.speed = 1;
204 	gmx_cfg.s.speed_msb = 0;
205 	gmx_cfg.s.slottime = 1;
206 	cvmx_write_csr(CVMX_GMXX_TX_PRTS(interface), 1);
207 	cvmx_write_csr(CVMX_GMXX_TXX_SLOT(0, interface), 512);
208 	cvmx_write_csr(CVMX_GMXX_TXX_BURST(0, interface), 8192);
209 	cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64);
210 
211 	/* (7) Clear out any error state */
212 	cvmx_write_csr(CVMX_GMXX_RXX_INT_REG(0, interface),
213 		       cvmx_read_csr(CVMX_GMXX_RXX_INT_REG(0, interface)));
214 	cvmx_write_csr(CVMX_GMXX_TX_INT_REG(interface),
215 		       cvmx_read_csr(CVMX_GMXX_TX_INT_REG(interface)));
216 	cvmx_write_csr(CVMX_PCSXX_INT_REG(interface),
217 		       cvmx_read_csr(CVMX_PCSXX_INT_REG(interface)));
218 
219 	/* Wait for receive link */
220 	if (CVMX_WAIT_FOR_FIELD64
221 	    (CVMX_PCSXX_STATUS1_REG(interface), union cvmx_pcsxx_status1_reg,
222 	     rcv_lnk, ==, 1, 10000))
223 		return -1;
224 	if (CVMX_WAIT_FOR_FIELD64
225 	    (CVMX_PCSXX_STATUS2_REG(interface), union cvmx_pcsxx_status2_reg,
226 	     xmtflt, ==, 0, 10000))
227 		return -1;
228 	if (CVMX_WAIT_FOR_FIELD64
229 	    (CVMX_PCSXX_STATUS2_REG(interface), union cvmx_pcsxx_status2_reg,
230 	     rcvflt, ==, 0, 10000))
231 		return -1;
232 
233 	cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(0, interface), gmx_rx_int_en.u64);
234 	cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), gmx_tx_int_en.u64);
235 	cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(interface), pcsx_int_en_reg.u64);
236 
237 	/* (8) Enable packet reception */
238 	xauiMiscCtl.s.gmxeno = 0;
239 	cvmx_write_csr(CVMX_PCSXX_MISC_CTL_REG(interface), xauiMiscCtl.u64);
240 
241 	gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface));
242 	gmx_cfg.s.en = 1;
243 	cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64);
244 
245 	__cvmx_interrupt_pcsx_intx_en_reg_enable(0, interface);
246 	__cvmx_interrupt_pcsx_intx_en_reg_enable(1, interface);
247 	__cvmx_interrupt_pcsx_intx_en_reg_enable(2, interface);
248 	__cvmx_interrupt_pcsx_intx_en_reg_enable(3, interface);
249 	__cvmx_interrupt_pcsxx_int_en_reg_enable(interface);
250 	__cvmx_interrupt_gmxx_enable(interface);
251 
252 	return 0;
253 }
254 
255 /**
256  * Return the link state of an IPD/PKO port as returned by
257  * auto negotiation. The result of this function may not match
258  * Octeon's link config if auto negotiation has changed since
259  * the last call to cvmx_helper_link_set().
260  *
261  * @ipd_port: IPD/PKO port to query
262  *
263  * Returns Link state
264  */
265 cvmx_helper_link_info_t __cvmx_helper_xaui_link_get(int ipd_port)
266 {
267 	int interface = cvmx_helper_get_interface_num(ipd_port);
268 	union cvmx_gmxx_tx_xaui_ctl gmxx_tx_xaui_ctl;
269 	union cvmx_gmxx_rx_xaui_ctl gmxx_rx_xaui_ctl;
270 	union cvmx_pcsxx_status1_reg pcsxx_status1_reg;
271 	cvmx_helper_link_info_t result;
272 
273 	gmxx_tx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_TX_XAUI_CTL(interface));
274 	gmxx_rx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_RX_XAUI_CTL(interface));
275 	pcsxx_status1_reg.u64 =
276 	    cvmx_read_csr(CVMX_PCSXX_STATUS1_REG(interface));
277 	result.u64 = 0;
278 
279 	/* Only return a link if both RX and TX are happy */
280 	if ((gmxx_tx_xaui_ctl.s.ls == 0) && (gmxx_rx_xaui_ctl.s.status == 0) &&
281 	    (pcsxx_status1_reg.s.rcv_lnk == 1)) {
282 		result.s.link_up = 1;
283 		result.s.full_duplex = 1;
284 		result.s.speed = 10000;
285 	} else {
286 		/* Disable GMX and PCSX interrupts. */
287 		cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(0, interface), 0x0);
288 		cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), 0x0);
289 		cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(interface), 0x0);
290 	}
291 	return result;
292 }
293 
294 /**
295  * Configure an IPD/PKO port for the specified link state. This
296  * function does not influence auto negotiation at the PHY level.
297  * The passed link state must always match the link state returned
298  * by cvmx_helper_link_get().
299  *
300  * @ipd_port:  IPD/PKO port to configure
301  * @link_info: The new link state
302  *
303  * Returns Zero on success, negative on failure
304  */
305 int __cvmx_helper_xaui_link_set(int ipd_port, cvmx_helper_link_info_t link_info)
306 {
307 	int interface = cvmx_helper_get_interface_num(ipd_port);
308 	union cvmx_gmxx_tx_xaui_ctl gmxx_tx_xaui_ctl;
309 	union cvmx_gmxx_rx_xaui_ctl gmxx_rx_xaui_ctl;
310 
311 	gmxx_tx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_TX_XAUI_CTL(interface));
312 	gmxx_rx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_RX_XAUI_CTL(interface));
313 
314 	/* If the link shouldn't be up, then just return */
315 	if (!link_info.s.link_up)
316 		return 0;
317 
318 	/* Do nothing if both RX and TX are happy */
319 	if ((gmxx_tx_xaui_ctl.s.ls == 0) && (gmxx_rx_xaui_ctl.s.status == 0))
320 		return 0;
321 
322 	/* Bring the link up */
323 	return __cvmx_helper_xaui_enable(interface);
324 }
325 
326 /**
327  * Configure a port for internal and/or external loopback. Internal loopback
328  * causes packets sent by the port to be received by Octeon. External loopback
329  * causes packets received from the wire to sent out again.
330  *
331  * @ipd_port: IPD/PKO port to loopback.
332  * @enable_internal:
333  *		   Non zero if you want internal loopback
334  * @enable_external:
335  *		   Non zero if you want external loopback
336  *
337  * Returns Zero on success, negative on failure.
338  */
339 extern int __cvmx_helper_xaui_configure_loopback(int ipd_port,
340 						 int enable_internal,
341 						 int enable_external)
342 {
343 	int interface = cvmx_helper_get_interface_num(ipd_port);
344 	union cvmx_pcsxx_control1_reg pcsxx_control1_reg;
345 	union cvmx_gmxx_xaui_ext_loopback gmxx_xaui_ext_loopback;
346 
347 	/* Set the internal loop */
348 	pcsxx_control1_reg.u64 =
349 	    cvmx_read_csr(CVMX_PCSXX_CONTROL1_REG(interface));
350 	pcsxx_control1_reg.s.loopbck1 = enable_internal;
351 	cvmx_write_csr(CVMX_PCSXX_CONTROL1_REG(interface),
352 		       pcsxx_control1_reg.u64);
353 
354 	/* Set the external loop */
355 	gmxx_xaui_ext_loopback.u64 =
356 	    cvmx_read_csr(CVMX_GMXX_XAUI_EXT_LOOPBACK(interface));
357 	gmxx_xaui_ext_loopback.s.en = enable_external;
358 	cvmx_write_csr(CVMX_GMXX_XAUI_EXT_LOOPBACK(interface),
359 		       gmxx_xaui_ext_loopback.u64);
360 
361 	/* Take the link through a reset */
362 	return __cvmx_helper_xaui_enable(interface);
363 }
364