1 /***********************license start*************** 2 * Author: Cavium Networks 3 * 4 * Contact: support@caviumnetworks.com 5 * This file is part of the OCTEON SDK 6 * 7 * Copyright (c) 2003-2008 Cavium Networks 8 * 9 * This file is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License, Version 2, as 11 * published by the Free Software Foundation. 12 * 13 * This file is distributed in the hope that it will be useful, but 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16 * NONINFRINGEMENT. See the GNU General Public License for more 17 * details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this file; if not, write to the Free Software 21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 22 * or visit http://www.gnu.org/licenses/. 23 * 24 * This file may also be available under a different license from Cavium. 25 * Contact Cavium Networks for more information 26 ***********************license end**************************************/ 27 28 /* 29 * 30 * Helper functions to abstract board specific data about 31 * network ports from the rest of the cvmx-helper files. 32 */ 33 34 #include <asm/octeon/octeon.h> 35 #include <asm/octeon/cvmx-bootinfo.h> 36 37 #include <asm/octeon/cvmx-config.h> 38 39 #include <asm/octeon/cvmx-mdio.h> 40 41 #include <asm/octeon/cvmx-helper.h> 42 #include <asm/octeon/cvmx-helper-util.h> 43 #include <asm/octeon/cvmx-helper-board.h> 44 45 #include <asm/octeon/cvmx-gmxx-defs.h> 46 #include <asm/octeon/cvmx-asxx-defs.h> 47 48 /** 49 * cvmx_override_board_link_get(int ipd_port) is a function 50 * pointer. It is meant to allow customization of the process of 51 * talking to a PHY to determine link speed. It is called every 52 * time a PHY must be polled for link status. Users should set 53 * this pointer to a function before calling any cvmx-helper 54 * operations. 55 */ 56 cvmx_helper_link_info_t(*cvmx_override_board_link_get) (int ipd_port) = 57 NULL; 58 59 /** 60 * Return the MII PHY address associated with the given IPD 61 * port. A result of -1 means there isn't a MII capable PHY 62 * connected to this port. On chips supporting multiple MII 63 * busses the bus number is encoded in bits <15:8>. 64 * 65 * This function must be modified for every new Octeon board. 66 * Internally it uses switch statements based on the cvmx_sysinfo 67 * data to determine board types and revisions. It replies on the 68 * fact that every Octeon board receives a unique board type 69 * enumeration from the bootloader. 70 * 71 * @ipd_port: Octeon IPD port to get the MII address for. 72 * 73 * Returns MII PHY address and bus number or -1. 74 */ 75 int cvmx_helper_board_get_mii_address(int ipd_port) 76 { 77 switch (cvmx_sysinfo_get()->board_type) { 78 case CVMX_BOARD_TYPE_SIM: 79 /* Simulator doesn't have MII */ 80 return -1; 81 case CVMX_BOARD_TYPE_EBT3000: 82 case CVMX_BOARD_TYPE_EBT5800: 83 case CVMX_BOARD_TYPE_THUNDER: 84 case CVMX_BOARD_TYPE_NICPRO2: 85 /* Interface 0 is SPI4, interface 1 is RGMII */ 86 if ((ipd_port >= 16) && (ipd_port < 20)) 87 return ipd_port - 16; 88 else 89 return -1; 90 case CVMX_BOARD_TYPE_KODAMA: 91 case CVMX_BOARD_TYPE_EBH3100: 92 case CVMX_BOARD_TYPE_HIKARI: 93 case CVMX_BOARD_TYPE_CN3010_EVB_HS5: 94 case CVMX_BOARD_TYPE_CN3005_EVB_HS5: 95 case CVMX_BOARD_TYPE_CN3020_EVB_HS5: 96 /* 97 * Port 0 is WAN connected to a PHY, Port 1 is GMII 98 * connected to a switch 99 */ 100 if (ipd_port == 0) 101 return 4; 102 else if (ipd_port == 1) 103 return 9; 104 else 105 return -1; 106 case CVMX_BOARD_TYPE_NAC38: 107 /* Board has 8 RGMII ports PHYs are 0-7 */ 108 if ((ipd_port >= 0) && (ipd_port < 4)) 109 return ipd_port; 110 else if ((ipd_port >= 16) && (ipd_port < 20)) 111 return ipd_port - 16 + 4; 112 else 113 return -1; 114 case CVMX_BOARD_TYPE_EBH3000: 115 /* Board has dual SPI4 and no PHYs */ 116 return -1; 117 case CVMX_BOARD_TYPE_EBH5200: 118 case CVMX_BOARD_TYPE_EBH5201: 119 case CVMX_BOARD_TYPE_EBT5200: 120 /* Board has 2 management ports */ 121 if ((ipd_port >= CVMX_HELPER_BOARD_MGMT_IPD_PORT) && 122 (ipd_port < (CVMX_HELPER_BOARD_MGMT_IPD_PORT + 2))) 123 return ipd_port - CVMX_HELPER_BOARD_MGMT_IPD_PORT; 124 /* 125 * Board has 4 SGMII ports. The PHYs start right after the MII 126 * ports MII0 = 0, MII1 = 1, SGMII = 2-5. 127 */ 128 if ((ipd_port >= 0) && (ipd_port < 4)) 129 return ipd_port + 2; 130 else 131 return -1; 132 case CVMX_BOARD_TYPE_EBH5600: 133 case CVMX_BOARD_TYPE_EBH5601: 134 case CVMX_BOARD_TYPE_EBH5610: 135 /* Board has 1 management port */ 136 if (ipd_port == CVMX_HELPER_BOARD_MGMT_IPD_PORT) 137 return 0; 138 /* 139 * Board has 8 SGMII ports. 4 connect out, two connect 140 * to a switch, and 2 loop to each other 141 */ 142 if ((ipd_port >= 0) && (ipd_port < 4)) 143 return ipd_port + 1; 144 else 145 return -1; 146 case CVMX_BOARD_TYPE_CUST_NB5: 147 if (ipd_port == 2) 148 return 4; 149 else 150 return -1; 151 case CVMX_BOARD_TYPE_NIC_XLE_4G: 152 /* Board has 4 SGMII ports. connected QLM3(interface 1) */ 153 if ((ipd_port >= 16) && (ipd_port < 20)) 154 return ipd_port - 16 + 1; 155 else 156 return -1; 157 case CVMX_BOARD_TYPE_NIC_XLE_10G: 158 case CVMX_BOARD_TYPE_NIC10E: 159 return -1; 160 case CVMX_BOARD_TYPE_NIC4E: 161 if (ipd_port >= 0 && ipd_port <= 3) 162 return (ipd_port + 0x1f) & 0x1f; 163 else 164 return -1; 165 case CVMX_BOARD_TYPE_NIC2E: 166 if (ipd_port >= 0 && ipd_port <= 1) 167 return ipd_port + 1; 168 else 169 return -1; 170 case CVMX_BOARD_TYPE_BBGW_REF: 171 /* 172 * No PHYs are connected to Octeon, everything is 173 * through switch. 174 */ 175 return -1; 176 177 case CVMX_BOARD_TYPE_CUST_WSX16: 178 if (ipd_port >= 0 && ipd_port <= 3) 179 return ipd_port; 180 else if (ipd_port >= 16 && ipd_port <= 19) 181 return ipd_port - 16 + 4; 182 else 183 return -1; 184 case CVMX_BOARD_TYPE_UBNT_E100: 185 if (ipd_port >= 0 && ipd_port <= 2) 186 return 7 - ipd_port; 187 else 188 return -1; 189 } 190 191 /* Some unknown board. Somebody forgot to update this function... */ 192 cvmx_dprintf 193 ("cvmx_helper_board_get_mii_address: Unknown board type %d\n", 194 cvmx_sysinfo_get()->board_type); 195 return -1; 196 } 197 198 /** 199 * This function is the board specific method of determining an 200 * ethernet ports link speed. Most Octeon boards have Marvell PHYs 201 * and are handled by the fall through case. This function must be 202 * updated for boards that don't have the normal Marvell PHYs. 203 * 204 * This function must be modified for every new Octeon board. 205 * Internally it uses switch statements based on the cvmx_sysinfo 206 * data to determine board types and revisions. It relies on the 207 * fact that every Octeon board receives a unique board type 208 * enumeration from the bootloader. 209 * 210 * @ipd_port: IPD input port associated with the port we want to get link 211 * status for. 212 * 213 * Returns The ports link status. If the link isn't fully resolved, this must 214 * return zero. 215 */ 216 cvmx_helper_link_info_t __cvmx_helper_board_link_get(int ipd_port) 217 { 218 cvmx_helper_link_info_t result; 219 int phy_addr; 220 int is_broadcom_phy = 0; 221 222 /* Give the user a chance to override the processing of this function */ 223 if (cvmx_override_board_link_get) 224 return cvmx_override_board_link_get(ipd_port); 225 226 /* Unless we fix it later, all links are defaulted to down */ 227 result.u64 = 0; 228 229 /* 230 * This switch statement should handle all ports that either don't use 231 * Marvell PHYS, or don't support in-band status. 232 */ 233 switch (cvmx_sysinfo_get()->board_type) { 234 case CVMX_BOARD_TYPE_SIM: 235 /* The simulator gives you a simulated 1Gbps full duplex link */ 236 result.s.link_up = 1; 237 result.s.full_duplex = 1; 238 result.s.speed = 1000; 239 return result; 240 case CVMX_BOARD_TYPE_EBH3100: 241 case CVMX_BOARD_TYPE_CN3010_EVB_HS5: 242 case CVMX_BOARD_TYPE_CN3005_EVB_HS5: 243 case CVMX_BOARD_TYPE_CN3020_EVB_HS5: 244 /* Port 1 on these boards is always Gigabit */ 245 if (ipd_port == 1) { 246 result.s.link_up = 1; 247 result.s.full_duplex = 1; 248 result.s.speed = 1000; 249 return result; 250 } 251 /* Fall through to the generic code below */ 252 break; 253 case CVMX_BOARD_TYPE_CUST_NB5: 254 /* Port 1 on these boards is always Gigabit */ 255 if (ipd_port == 1) { 256 result.s.link_up = 1; 257 result.s.full_duplex = 1; 258 result.s.speed = 1000; 259 return result; 260 } else /* The other port uses a broadcom PHY */ 261 is_broadcom_phy = 1; 262 break; 263 case CVMX_BOARD_TYPE_BBGW_REF: 264 /* Port 1 on these boards is always Gigabit */ 265 if (ipd_port == 2) { 266 /* Port 2 is not hooked up */ 267 result.u64 = 0; 268 return result; 269 } else { 270 /* Ports 0 and 1 connect to the switch */ 271 result.s.link_up = 1; 272 result.s.full_duplex = 1; 273 result.s.speed = 1000; 274 return result; 275 } 276 break; 277 } 278 279 phy_addr = cvmx_helper_board_get_mii_address(ipd_port); 280 if (phy_addr != -1) { 281 if (is_broadcom_phy) { 282 /* 283 * Below we are going to read SMI/MDIO 284 * register 0x19 which works on Broadcom 285 * parts 286 */ 287 int phy_status = 288 cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, 289 0x19); 290 switch ((phy_status >> 8) & 0x7) { 291 case 0: 292 result.u64 = 0; 293 break; 294 case 1: 295 result.s.link_up = 1; 296 result.s.full_duplex = 0; 297 result.s.speed = 10; 298 break; 299 case 2: 300 result.s.link_up = 1; 301 result.s.full_duplex = 1; 302 result.s.speed = 10; 303 break; 304 case 3: 305 result.s.link_up = 1; 306 result.s.full_duplex = 0; 307 result.s.speed = 100; 308 break; 309 case 4: 310 result.s.link_up = 1; 311 result.s.full_duplex = 1; 312 result.s.speed = 100; 313 break; 314 case 5: 315 result.s.link_up = 1; 316 result.s.full_duplex = 1; 317 result.s.speed = 100; 318 break; 319 case 6: 320 result.s.link_up = 1; 321 result.s.full_duplex = 0; 322 result.s.speed = 1000; 323 break; 324 case 7: 325 result.s.link_up = 1; 326 result.s.full_duplex = 1; 327 result.s.speed = 1000; 328 break; 329 } 330 } else { 331 /* 332 * This code assumes we are using a Marvell 333 * Gigabit PHY. All the speed information can 334 * be read from register 17 in one 335 * go. Somebody using a different PHY will 336 * need to handle it above in the board 337 * specific area. 338 */ 339 int phy_status = 340 cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, 17); 341 342 /* 343 * If the resolve bit 11 isn't set, see if 344 * autoneg is turned off (bit 12, reg 0). The 345 * resolve bit doesn't get set properly when 346 * autoneg is off, so force it. 347 */ 348 if ((phy_status & (1 << 11)) == 0) { 349 int auto_status = 350 cvmx_mdio_read(phy_addr >> 8, 351 phy_addr & 0xff, 0); 352 if ((auto_status & (1 << 12)) == 0) 353 phy_status |= 1 << 11; 354 } 355 356 /* 357 * Only return a link if the PHY has finished 358 * auto negotiation and set the resolved bit 359 * (bit 11) 360 */ 361 if (phy_status & (1 << 11)) { 362 result.s.link_up = 1; 363 result.s.full_duplex = ((phy_status >> 13) & 1); 364 switch ((phy_status >> 14) & 3) { 365 case 0: /* 10 Mbps */ 366 result.s.speed = 10; 367 break; 368 case 1: /* 100 Mbps */ 369 result.s.speed = 100; 370 break; 371 case 2: /* 1 Gbps */ 372 result.s.speed = 1000; 373 break; 374 case 3: /* Illegal */ 375 result.u64 = 0; 376 break; 377 } 378 } 379 } 380 } else if (OCTEON_IS_MODEL(OCTEON_CN3XXX) 381 || OCTEON_IS_MODEL(OCTEON_CN58XX) 382 || OCTEON_IS_MODEL(OCTEON_CN50XX)) { 383 /* 384 * We don't have a PHY address, so attempt to use 385 * in-band status. It is really important that boards 386 * not supporting in-band status never get 387 * here. Reading broken in-band status tends to do bad 388 * things 389 */ 390 union cvmx_gmxx_rxx_rx_inbnd inband_status; 391 int interface = cvmx_helper_get_interface_num(ipd_port); 392 int index = cvmx_helper_get_interface_index_num(ipd_port); 393 inband_status.u64 = 394 cvmx_read_csr(CVMX_GMXX_RXX_RX_INBND(index, interface)); 395 396 result.s.link_up = inband_status.s.status; 397 result.s.full_duplex = inband_status.s.duplex; 398 switch (inband_status.s.speed) { 399 case 0: /* 10 Mbps */ 400 result.s.speed = 10; 401 break; 402 case 1: /* 100 Mbps */ 403 result.s.speed = 100; 404 break; 405 case 2: /* 1 Gbps */ 406 result.s.speed = 1000; 407 break; 408 case 3: /* Illegal */ 409 result.u64 = 0; 410 break; 411 } 412 } else { 413 /* 414 * We don't have a PHY address and we don't have 415 * in-band status. There is no way to determine the 416 * link speed. Return down assuming this port isn't 417 * wired 418 */ 419 result.u64 = 0; 420 } 421 422 /* If link is down, return all fields as zero. */ 423 if (!result.s.link_up) 424 result.u64 = 0; 425 426 return result; 427 } 428 429 /** 430 * This function as a board specific method of changing the PHY 431 * speed, duplex, and auto-negotiation. This programs the PHY and 432 * not Octeon. This can be used to force Octeon's links to 433 * specific settings. 434 * 435 * @phy_addr: The address of the PHY to program 436 * @enable_autoneg: 437 * Non zero if you want to enable auto-negotiation. 438 * @link_info: Link speed to program. If the speed is zero and auto-negotiation 439 * is enabled, all possible negotiation speeds are advertised. 440 * 441 * Returns Zero on success, negative on failure 442 */ 443 int cvmx_helper_board_link_set_phy(int phy_addr, 444 cvmx_helper_board_set_phy_link_flags_types_t 445 link_flags, 446 cvmx_helper_link_info_t link_info) 447 { 448 449 /* Set the flow control settings based on link_flags */ 450 if ((link_flags & set_phy_link_flags_flow_control_mask) != 451 set_phy_link_flags_flow_control_dont_touch) { 452 cvmx_mdio_phy_reg_autoneg_adver_t reg_autoneg_adver; 453 reg_autoneg_adver.u16 = 454 cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, 455 CVMX_MDIO_PHY_REG_AUTONEG_ADVER); 456 reg_autoneg_adver.s.asymmetric_pause = 457 (link_flags & set_phy_link_flags_flow_control_mask) == 458 set_phy_link_flags_flow_control_enable; 459 reg_autoneg_adver.s.pause = 460 (link_flags & set_phy_link_flags_flow_control_mask) == 461 set_phy_link_flags_flow_control_enable; 462 cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff, 463 CVMX_MDIO_PHY_REG_AUTONEG_ADVER, 464 reg_autoneg_adver.u16); 465 } 466 467 /* If speed isn't set and autoneg is on advertise all supported modes */ 468 if ((link_flags & set_phy_link_flags_autoneg) 469 && (link_info.s.speed == 0)) { 470 cvmx_mdio_phy_reg_control_t reg_control; 471 cvmx_mdio_phy_reg_status_t reg_status; 472 cvmx_mdio_phy_reg_autoneg_adver_t reg_autoneg_adver; 473 cvmx_mdio_phy_reg_extended_status_t reg_extended_status; 474 cvmx_mdio_phy_reg_control_1000_t reg_control_1000; 475 476 reg_status.u16 = 477 cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, 478 CVMX_MDIO_PHY_REG_STATUS); 479 reg_autoneg_adver.u16 = 480 cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, 481 CVMX_MDIO_PHY_REG_AUTONEG_ADVER); 482 reg_autoneg_adver.s.advert_100base_t4 = 483 reg_status.s.capable_100base_t4; 484 reg_autoneg_adver.s.advert_10base_tx_full = 485 reg_status.s.capable_10_full; 486 reg_autoneg_adver.s.advert_10base_tx_half = 487 reg_status.s.capable_10_half; 488 reg_autoneg_adver.s.advert_100base_tx_full = 489 reg_status.s.capable_100base_x_full; 490 reg_autoneg_adver.s.advert_100base_tx_half = 491 reg_status.s.capable_100base_x_half; 492 cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff, 493 CVMX_MDIO_PHY_REG_AUTONEG_ADVER, 494 reg_autoneg_adver.u16); 495 if (reg_status.s.capable_extended_status) { 496 reg_extended_status.u16 = 497 cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, 498 CVMX_MDIO_PHY_REG_EXTENDED_STATUS); 499 reg_control_1000.u16 = 500 cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, 501 CVMX_MDIO_PHY_REG_CONTROL_1000); 502 reg_control_1000.s.advert_1000base_t_full = 503 reg_extended_status.s.capable_1000base_t_full; 504 reg_control_1000.s.advert_1000base_t_half = 505 reg_extended_status.s.capable_1000base_t_half; 506 cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff, 507 CVMX_MDIO_PHY_REG_CONTROL_1000, 508 reg_control_1000.u16); 509 } 510 reg_control.u16 = 511 cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, 512 CVMX_MDIO_PHY_REG_CONTROL); 513 reg_control.s.autoneg_enable = 1; 514 reg_control.s.restart_autoneg = 1; 515 cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff, 516 CVMX_MDIO_PHY_REG_CONTROL, reg_control.u16); 517 } else if ((link_flags & set_phy_link_flags_autoneg)) { 518 cvmx_mdio_phy_reg_control_t reg_control; 519 cvmx_mdio_phy_reg_status_t reg_status; 520 cvmx_mdio_phy_reg_autoneg_adver_t reg_autoneg_adver; 521 cvmx_mdio_phy_reg_control_1000_t reg_control_1000; 522 523 reg_status.u16 = 524 cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, 525 CVMX_MDIO_PHY_REG_STATUS); 526 reg_autoneg_adver.u16 = 527 cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, 528 CVMX_MDIO_PHY_REG_AUTONEG_ADVER); 529 reg_autoneg_adver.s.advert_100base_t4 = 0; 530 reg_autoneg_adver.s.advert_10base_tx_full = 0; 531 reg_autoneg_adver.s.advert_10base_tx_half = 0; 532 reg_autoneg_adver.s.advert_100base_tx_full = 0; 533 reg_autoneg_adver.s.advert_100base_tx_half = 0; 534 if (reg_status.s.capable_extended_status) { 535 reg_control_1000.u16 = 536 cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, 537 CVMX_MDIO_PHY_REG_CONTROL_1000); 538 reg_control_1000.s.advert_1000base_t_full = 0; 539 reg_control_1000.s.advert_1000base_t_half = 0; 540 } 541 switch (link_info.s.speed) { 542 case 10: 543 reg_autoneg_adver.s.advert_10base_tx_full = 544 link_info.s.full_duplex; 545 reg_autoneg_adver.s.advert_10base_tx_half = 546 !link_info.s.full_duplex; 547 break; 548 case 100: 549 reg_autoneg_adver.s.advert_100base_tx_full = 550 link_info.s.full_duplex; 551 reg_autoneg_adver.s.advert_100base_tx_half = 552 !link_info.s.full_duplex; 553 break; 554 case 1000: 555 reg_control_1000.s.advert_1000base_t_full = 556 link_info.s.full_duplex; 557 reg_control_1000.s.advert_1000base_t_half = 558 !link_info.s.full_duplex; 559 break; 560 } 561 cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff, 562 CVMX_MDIO_PHY_REG_AUTONEG_ADVER, 563 reg_autoneg_adver.u16); 564 if (reg_status.s.capable_extended_status) 565 cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff, 566 CVMX_MDIO_PHY_REG_CONTROL_1000, 567 reg_control_1000.u16); 568 reg_control.u16 = 569 cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, 570 CVMX_MDIO_PHY_REG_CONTROL); 571 reg_control.s.autoneg_enable = 1; 572 reg_control.s.restart_autoneg = 1; 573 cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff, 574 CVMX_MDIO_PHY_REG_CONTROL, reg_control.u16); 575 } else { 576 cvmx_mdio_phy_reg_control_t reg_control; 577 reg_control.u16 = 578 cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, 579 CVMX_MDIO_PHY_REG_CONTROL); 580 reg_control.s.autoneg_enable = 0; 581 reg_control.s.restart_autoneg = 1; 582 reg_control.s.duplex = link_info.s.full_duplex; 583 if (link_info.s.speed == 1000) { 584 reg_control.s.speed_msb = 1; 585 reg_control.s.speed_lsb = 0; 586 } else if (link_info.s.speed == 100) { 587 reg_control.s.speed_msb = 0; 588 reg_control.s.speed_lsb = 1; 589 } else if (link_info.s.speed == 10) { 590 reg_control.s.speed_msb = 0; 591 reg_control.s.speed_lsb = 0; 592 } 593 cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff, 594 CVMX_MDIO_PHY_REG_CONTROL, reg_control.u16); 595 } 596 return 0; 597 } 598 599 /** 600 * This function is called by cvmx_helper_interface_probe() after it 601 * determines the number of ports Octeon can support on a specific 602 * interface. This function is the per board location to override 603 * this value. It is called with the number of ports Octeon might 604 * support and should return the number of actual ports on the 605 * board. 606 * 607 * This function must be modifed for every new Octeon board. 608 * Internally it uses switch statements based on the cvmx_sysinfo 609 * data to determine board types and revisions. It relys on the 610 * fact that every Octeon board receives a unique board type 611 * enumeration from the bootloader. 612 * 613 * @interface: Interface to probe 614 * @supported_ports: 615 * Number of ports Octeon supports. 616 * 617 * Returns Number of ports the actual board supports. Many times this will 618 * simple be "support_ports". 619 */ 620 int __cvmx_helper_board_interface_probe(int interface, int supported_ports) 621 { 622 switch (cvmx_sysinfo_get()->board_type) { 623 case CVMX_BOARD_TYPE_CN3005_EVB_HS5: 624 if (interface == 0) 625 return 2; 626 break; 627 case CVMX_BOARD_TYPE_BBGW_REF: 628 if (interface == 0) 629 return 2; 630 break; 631 case CVMX_BOARD_TYPE_NIC_XLE_4G: 632 if (interface == 0) 633 return 0; 634 break; 635 /* The 2nd interface on the EBH5600 is connected to the Marvel switch, 636 which we don't support. Disable ports connected to it */ 637 case CVMX_BOARD_TYPE_EBH5600: 638 if (interface == 1) 639 return 0; 640 break; 641 } 642 return supported_ports; 643 } 644 645 /** 646 * Enable packet input/output from the hardware. This function is 647 * called after by cvmx_helper_packet_hardware_enable() to 648 * perform board specific initialization. For most boards 649 * nothing is needed. 650 * 651 * @interface: Interface to enable 652 * 653 * Returns Zero on success, negative on failure 654 */ 655 int __cvmx_helper_board_hardware_enable(int interface) 656 { 657 if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_CN3005_EVB_HS5) { 658 if (interface == 0) { 659 /* Different config for switch port */ 660 cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(1, interface), 0); 661 cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(1, interface), 0); 662 /* 663 * Boards with gigabit WAN ports need a 664 * different setting that is compatible with 665 * 100 Mbit settings 666 */ 667 cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(0, interface), 668 0xc); 669 cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(0, interface), 670 0xc); 671 } 672 } else if (cvmx_sysinfo_get()->board_type == 673 CVMX_BOARD_TYPE_CN3010_EVB_HS5) { 674 /* 675 * Broadcom PHYs require differnet ASX 676 * clocks. Unfortunately many boards don't define a 677 * new board Id and simply mangle the 678 * CN3010_EVB_HS5 679 */ 680 if (interface == 0) { 681 /* 682 * Some boards use a hacked up bootloader that 683 * identifies them as CN3010_EVB_HS5 684 * evaluation boards. This leads to all kinds 685 * of configuration problems. Detect one 686 * case, and print warning, while trying to do 687 * the right thing. 688 */ 689 int phy_addr = cvmx_helper_board_get_mii_address(0); 690 if (phy_addr != -1) { 691 int phy_identifier = 692 cvmx_mdio_read(phy_addr >> 8, 693 phy_addr & 0xff, 0x2); 694 /* Is it a Broadcom PHY? */ 695 if (phy_identifier == 0x0143) { 696 cvmx_dprintf("\n"); 697 cvmx_dprintf("ERROR:\n"); 698 cvmx_dprintf 699 ("ERROR: Board type is CVMX_BOARD_TYPE_CN3010_EVB_HS5, but Broadcom PHY found.\n"); 700 cvmx_dprintf 701 ("ERROR: The board type is mis-configured, and software malfunctions are likely.\n"); 702 cvmx_dprintf 703 ("ERROR: All boards require a unique board type to identify them.\n"); 704 cvmx_dprintf("ERROR:\n"); 705 cvmx_dprintf("\n"); 706 cvmx_wait(1000000000); 707 cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX 708 (0, interface), 5); 709 cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX 710 (0, interface), 5); 711 } 712 } 713 } 714 } else if (cvmx_sysinfo_get()->board_type == 715 CVMX_BOARD_TYPE_UBNT_E100) { 716 cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(0, interface), 0); 717 cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(0, interface), 0x10); 718 cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(1, interface), 0); 719 cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(1, interface), 0x10); 720 cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(2, interface), 0); 721 cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(2, interface), 0x10); 722 } 723 return 0; 724 } 725