1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2000 Ani Joshi <ajoshi@unixbox.com> 7 * Copyright (C) 2000, 2001 Ralf Baechle <ralf@gnu.org> 8 * Copyright (C) 2005 Ilya A. Volynets-Evenbakh <ilya@total-knowledge.com> 9 * swiped from i386, and cloned for MIPS by Geert, polished by Ralf. 10 * IP32 changes by Ilya. 11 * Copyright (C) 2010 Cavium Networks, Inc. 12 */ 13 #include <linux/dma-direct.h> 14 #include <linux/scatterlist.h> 15 #include <linux/bootmem.h> 16 #include <linux/export.h> 17 #include <linux/swiotlb.h> 18 #include <linux/types.h> 19 #include <linux/init.h> 20 #include <linux/mm.h> 21 22 #include <asm/bootinfo.h> 23 24 #include <asm/octeon/octeon.h> 25 26 #ifdef CONFIG_PCI 27 #include <asm/octeon/pci-octeon.h> 28 #include <asm/octeon/cvmx-npi-defs.h> 29 #include <asm/octeon/cvmx-pci-defs.h> 30 31 static dma_addr_t octeon_hole_phys_to_dma(phys_addr_t paddr) 32 { 33 if (paddr >= CVMX_PCIE_BAR1_PHYS_BASE && paddr < (CVMX_PCIE_BAR1_PHYS_BASE + CVMX_PCIE_BAR1_PHYS_SIZE)) 34 return paddr - CVMX_PCIE_BAR1_PHYS_BASE + CVMX_PCIE_BAR1_RC_BASE; 35 else 36 return paddr; 37 } 38 39 static phys_addr_t octeon_hole_dma_to_phys(dma_addr_t daddr) 40 { 41 if (daddr >= CVMX_PCIE_BAR1_RC_BASE) 42 return daddr + CVMX_PCIE_BAR1_PHYS_BASE - CVMX_PCIE_BAR1_RC_BASE; 43 else 44 return daddr; 45 } 46 47 static dma_addr_t octeon_gen1_phys_to_dma(struct device *dev, phys_addr_t paddr) 48 { 49 if (paddr >= 0x410000000ull && paddr < 0x420000000ull) 50 paddr -= 0x400000000ull; 51 return octeon_hole_phys_to_dma(paddr); 52 } 53 54 static phys_addr_t octeon_gen1_dma_to_phys(struct device *dev, dma_addr_t daddr) 55 { 56 daddr = octeon_hole_dma_to_phys(daddr); 57 58 if (daddr >= 0x10000000ull && daddr < 0x20000000ull) 59 daddr += 0x400000000ull; 60 61 return daddr; 62 } 63 64 static dma_addr_t octeon_gen2_phys_to_dma(struct device *dev, phys_addr_t paddr) 65 { 66 return octeon_hole_phys_to_dma(paddr); 67 } 68 69 static phys_addr_t octeon_gen2_dma_to_phys(struct device *dev, dma_addr_t daddr) 70 { 71 return octeon_hole_dma_to_phys(daddr); 72 } 73 74 static dma_addr_t octeon_big_phys_to_dma(struct device *dev, phys_addr_t paddr) 75 { 76 if (paddr >= 0x410000000ull && paddr < 0x420000000ull) 77 paddr -= 0x400000000ull; 78 79 /* Anything in the BAR1 hole or above goes via BAR2 */ 80 if (paddr >= 0xf0000000ull) 81 paddr = OCTEON_BAR2_PCI_ADDRESS + paddr; 82 83 return paddr; 84 } 85 86 static phys_addr_t octeon_big_dma_to_phys(struct device *dev, dma_addr_t daddr) 87 { 88 if (daddr >= OCTEON_BAR2_PCI_ADDRESS) 89 daddr -= OCTEON_BAR2_PCI_ADDRESS; 90 91 if (daddr >= 0x10000000ull && daddr < 0x20000000ull) 92 daddr += 0x400000000ull; 93 return daddr; 94 } 95 96 static dma_addr_t octeon_small_phys_to_dma(struct device *dev, 97 phys_addr_t paddr) 98 { 99 if (paddr >= 0x410000000ull && paddr < 0x420000000ull) 100 paddr -= 0x400000000ull; 101 102 /* Anything not in the BAR1 range goes via BAR2 */ 103 if (paddr >= octeon_bar1_pci_phys && paddr < octeon_bar1_pci_phys + 0x8000000ull) 104 paddr = paddr - octeon_bar1_pci_phys; 105 else 106 paddr = OCTEON_BAR2_PCI_ADDRESS + paddr; 107 108 return paddr; 109 } 110 111 static phys_addr_t octeon_small_dma_to_phys(struct device *dev, 112 dma_addr_t daddr) 113 { 114 if (daddr >= OCTEON_BAR2_PCI_ADDRESS) 115 daddr -= OCTEON_BAR2_PCI_ADDRESS; 116 else 117 daddr += octeon_bar1_pci_phys; 118 119 if (daddr >= 0x10000000ull && daddr < 0x20000000ull) 120 daddr += 0x400000000ull; 121 return daddr; 122 } 123 124 #endif /* CONFIG_PCI */ 125 126 static dma_addr_t octeon_dma_map_page(struct device *dev, struct page *page, 127 unsigned long offset, size_t size, enum dma_data_direction direction, 128 unsigned long attrs) 129 { 130 dma_addr_t daddr = swiotlb_map_page(dev, page, offset, size, 131 direction, attrs); 132 mb(); 133 134 return daddr; 135 } 136 137 static int octeon_dma_map_sg(struct device *dev, struct scatterlist *sg, 138 int nents, enum dma_data_direction direction, unsigned long attrs) 139 { 140 int r = swiotlb_map_sg_attrs(dev, sg, nents, direction, attrs); 141 mb(); 142 return r; 143 } 144 145 static void octeon_dma_sync_single_for_device(struct device *dev, 146 dma_addr_t dma_handle, size_t size, enum dma_data_direction direction) 147 { 148 swiotlb_sync_single_for_device(dev, dma_handle, size, direction); 149 mb(); 150 } 151 152 static void octeon_dma_sync_sg_for_device(struct device *dev, 153 struct scatterlist *sg, int nelems, enum dma_data_direction direction) 154 { 155 swiotlb_sync_sg_for_device(dev, sg, nelems, direction); 156 mb(); 157 } 158 159 static void *octeon_dma_alloc_coherent(struct device *dev, size_t size, 160 dma_addr_t *dma_handle, gfp_t gfp, unsigned long attrs) 161 { 162 void *ret = swiotlb_alloc(dev, size, dma_handle, gfp, attrs); 163 164 mb(); 165 166 return ret; 167 } 168 169 static dma_addr_t octeon_unity_phys_to_dma(struct device *dev, phys_addr_t paddr) 170 { 171 return paddr; 172 } 173 174 static phys_addr_t octeon_unity_dma_to_phys(struct device *dev, dma_addr_t daddr) 175 { 176 return daddr; 177 } 178 179 struct octeon_dma_map_ops { 180 const struct dma_map_ops dma_map_ops; 181 dma_addr_t (*phys_to_dma)(struct device *dev, phys_addr_t paddr); 182 phys_addr_t (*dma_to_phys)(struct device *dev, dma_addr_t daddr); 183 }; 184 185 dma_addr_t __phys_to_dma(struct device *dev, phys_addr_t paddr) 186 { 187 struct octeon_dma_map_ops *ops = container_of(get_dma_ops(dev), 188 struct octeon_dma_map_ops, 189 dma_map_ops); 190 191 return ops->phys_to_dma(dev, paddr); 192 } 193 EXPORT_SYMBOL(__phys_to_dma); 194 195 phys_addr_t __dma_to_phys(struct device *dev, dma_addr_t daddr) 196 { 197 struct octeon_dma_map_ops *ops = container_of(get_dma_ops(dev), 198 struct octeon_dma_map_ops, 199 dma_map_ops); 200 201 return ops->dma_to_phys(dev, daddr); 202 } 203 EXPORT_SYMBOL(__dma_to_phys); 204 205 static struct octeon_dma_map_ops octeon_linear_dma_map_ops = { 206 .dma_map_ops = { 207 .alloc = octeon_dma_alloc_coherent, 208 .free = swiotlb_free, 209 .map_page = octeon_dma_map_page, 210 .unmap_page = swiotlb_unmap_page, 211 .map_sg = octeon_dma_map_sg, 212 .unmap_sg = swiotlb_unmap_sg_attrs, 213 .sync_single_for_cpu = swiotlb_sync_single_for_cpu, 214 .sync_single_for_device = octeon_dma_sync_single_for_device, 215 .sync_sg_for_cpu = swiotlb_sync_sg_for_cpu, 216 .sync_sg_for_device = octeon_dma_sync_sg_for_device, 217 .mapping_error = swiotlb_dma_mapping_error, 218 .dma_supported = swiotlb_dma_supported 219 }, 220 .phys_to_dma = octeon_unity_phys_to_dma, 221 .dma_to_phys = octeon_unity_dma_to_phys 222 }; 223 224 char *octeon_swiotlb; 225 226 void __init plat_swiotlb_setup(void) 227 { 228 int i; 229 phys_addr_t max_addr; 230 phys_addr_t addr_size; 231 size_t swiotlbsize; 232 unsigned long swiotlb_nslabs; 233 234 max_addr = 0; 235 addr_size = 0; 236 237 for (i = 0 ; i < boot_mem_map.nr_map; i++) { 238 struct boot_mem_map_entry *e = &boot_mem_map.map[i]; 239 if (e->type != BOOT_MEM_RAM && e->type != BOOT_MEM_INIT_RAM) 240 continue; 241 242 /* These addresses map low for PCI. */ 243 if (e->addr > 0x410000000ull && !OCTEON_IS_OCTEON2()) 244 continue; 245 246 addr_size += e->size; 247 248 if (max_addr < e->addr + e->size) 249 max_addr = e->addr + e->size; 250 251 } 252 253 swiotlbsize = PAGE_SIZE; 254 255 #ifdef CONFIG_PCI 256 /* 257 * For OCTEON_DMA_BAR_TYPE_SMALL, size the iotlb at 1/4 memory 258 * size to a maximum of 64MB 259 */ 260 if (OCTEON_IS_MODEL(OCTEON_CN31XX) 261 || OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2)) { 262 swiotlbsize = addr_size / 4; 263 if (swiotlbsize > 64 * (1<<20)) 264 swiotlbsize = 64 * (1<<20); 265 } else if (max_addr > 0xf0000000ul) { 266 /* 267 * Otherwise only allocate a big iotlb if there is 268 * memory past the BAR1 hole. 269 */ 270 swiotlbsize = 64 * (1<<20); 271 } 272 #endif 273 #ifdef CONFIG_USB_OHCI_HCD_PLATFORM 274 /* OCTEON II ohci is only 32-bit. */ 275 if (OCTEON_IS_OCTEON2() && max_addr >= 0x100000000ul) 276 swiotlbsize = 64 * (1<<20); 277 #endif 278 swiotlb_nslabs = swiotlbsize >> IO_TLB_SHIFT; 279 swiotlb_nslabs = ALIGN(swiotlb_nslabs, IO_TLB_SEGSIZE); 280 swiotlbsize = swiotlb_nslabs << IO_TLB_SHIFT; 281 282 octeon_swiotlb = alloc_bootmem_low_pages(swiotlbsize); 283 284 if (swiotlb_init_with_tbl(octeon_swiotlb, swiotlb_nslabs, 1) == -ENOMEM) 285 panic("Cannot allocate SWIOTLB buffer"); 286 287 mips_dma_map_ops = &octeon_linear_dma_map_ops.dma_map_ops; 288 } 289 290 #ifdef CONFIG_PCI 291 static struct octeon_dma_map_ops _octeon_pci_dma_map_ops = { 292 .dma_map_ops = { 293 .alloc = octeon_dma_alloc_coherent, 294 .free = swiotlb_free, 295 .map_page = octeon_dma_map_page, 296 .unmap_page = swiotlb_unmap_page, 297 .map_sg = octeon_dma_map_sg, 298 .unmap_sg = swiotlb_unmap_sg_attrs, 299 .sync_single_for_cpu = swiotlb_sync_single_for_cpu, 300 .sync_single_for_device = octeon_dma_sync_single_for_device, 301 .sync_sg_for_cpu = swiotlb_sync_sg_for_cpu, 302 .sync_sg_for_device = octeon_dma_sync_sg_for_device, 303 .mapping_error = swiotlb_dma_mapping_error, 304 .dma_supported = swiotlb_dma_supported 305 }, 306 }; 307 308 const struct dma_map_ops *octeon_pci_dma_map_ops; 309 310 void __init octeon_pci_dma_init(void) 311 { 312 switch (octeon_dma_bar_type) { 313 case OCTEON_DMA_BAR_TYPE_PCIE2: 314 _octeon_pci_dma_map_ops.phys_to_dma = octeon_gen2_phys_to_dma; 315 _octeon_pci_dma_map_ops.dma_to_phys = octeon_gen2_dma_to_phys; 316 break; 317 case OCTEON_DMA_BAR_TYPE_PCIE: 318 _octeon_pci_dma_map_ops.phys_to_dma = octeon_gen1_phys_to_dma; 319 _octeon_pci_dma_map_ops.dma_to_phys = octeon_gen1_dma_to_phys; 320 break; 321 case OCTEON_DMA_BAR_TYPE_BIG: 322 _octeon_pci_dma_map_ops.phys_to_dma = octeon_big_phys_to_dma; 323 _octeon_pci_dma_map_ops.dma_to_phys = octeon_big_dma_to_phys; 324 break; 325 case OCTEON_DMA_BAR_TYPE_SMALL: 326 _octeon_pci_dma_map_ops.phys_to_dma = octeon_small_phys_to_dma; 327 _octeon_pci_dma_map_ops.dma_to_phys = octeon_small_dma_to_phys; 328 break; 329 default: 330 BUG(); 331 } 332 octeon_pci_dma_map_ops = &_octeon_pci_dma_map_ops.dma_map_ops; 333 } 334 #endif /* CONFIG_PCI */ 335