1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2007 by Ralf Baechle 7 * Copyright (C) 2009, 2012 Cavium, Inc. 8 */ 9 #include <linux/clocksource.h> 10 #include <linux/export.h> 11 #include <linux/init.h> 12 #include <linux/smp.h> 13 14 #include <asm/cpu-info.h> 15 #include <asm/cpu-type.h> 16 #include <asm/time.h> 17 18 #include <asm/octeon/octeon.h> 19 #include <asm/octeon/cvmx-ipd-defs.h> 20 #include <asm/octeon/cvmx-mio-defs.h> 21 #include <asm/octeon/cvmx-rst-defs.h> 22 23 static u64 f; 24 static u64 rdiv; 25 static u64 sdiv; 26 static u64 octeon_udelay_factor; 27 static u64 octeon_ndelay_factor; 28 29 void __init octeon_setup_delays(void) 30 { 31 octeon_udelay_factor = octeon_get_clock_rate() / 1000000; 32 /* 33 * For __ndelay we divide by 2^16, so the factor is multiplied 34 * by the same amount. 35 */ 36 octeon_ndelay_factor = (octeon_udelay_factor * 0x10000ull) / 1000ull; 37 38 preset_lpj = octeon_get_clock_rate() / HZ; 39 40 if (current_cpu_type() == CPU_CAVIUM_OCTEON2) { 41 union cvmx_mio_rst_boot rst_boot; 42 43 rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT); 44 rdiv = rst_boot.s.c_mul; /* CPU clock */ 45 sdiv = rst_boot.s.pnr_mul; /* I/O clock */ 46 f = (0x8000000000000000ull / sdiv) * 2; 47 } else if (current_cpu_type() == CPU_CAVIUM_OCTEON3) { 48 union cvmx_rst_boot rst_boot; 49 50 rst_boot.u64 = cvmx_read_csr(CVMX_RST_BOOT); 51 rdiv = rst_boot.s.c_mul; /* CPU clock */ 52 sdiv = rst_boot.s.pnr_mul; /* I/O clock */ 53 f = (0x8000000000000000ull / sdiv) * 2; 54 } 55 56 } 57 58 /* 59 * Set the current core's cvmcount counter to the value of the 60 * IPD_CLK_COUNT. We do this on all cores as they are brought 61 * on-line. This allows for a read from a local cpu register to 62 * access a synchronized counter. 63 * 64 * On CPU_CAVIUM_OCTEON2 the IPD_CLK_COUNT is scaled by rdiv/sdiv. 65 */ 66 void octeon_init_cvmcount(void) 67 { 68 unsigned long flags; 69 unsigned loops = 2; 70 71 /* Clobber loops so GCC will not unroll the following while loop. */ 72 asm("" : "+r" (loops)); 73 74 local_irq_save(flags); 75 /* 76 * Loop several times so we are executing from the cache, 77 * which should give more deterministic timing. 78 */ 79 while (loops--) { 80 u64 ipd_clk_count = cvmx_read_csr(CVMX_IPD_CLK_COUNT); 81 if (rdiv != 0) { 82 ipd_clk_count *= rdiv; 83 if (f != 0) { 84 asm("dmultu\t%[cnt],%[f]\n\t" 85 "mfhi\t%[cnt]" 86 : [cnt] "+r" (ipd_clk_count) 87 : [f] "r" (f) 88 : "hi", "lo"); 89 } 90 } 91 write_c0_cvmcount(ipd_clk_count); 92 } 93 local_irq_restore(flags); 94 } 95 96 static cycle_t octeon_cvmcount_read(struct clocksource *cs) 97 { 98 return read_c0_cvmcount(); 99 } 100 101 static struct clocksource clocksource_mips = { 102 .name = "OCTEON_CVMCOUNT", 103 .read = octeon_cvmcount_read, 104 .mask = CLOCKSOURCE_MASK(64), 105 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 106 }; 107 108 unsigned long long notrace sched_clock(void) 109 { 110 /* 64-bit arithmatic can overflow, so use 128-bit. */ 111 u64 t1, t2, t3; 112 unsigned long long rv; 113 u64 mult = clocksource_mips.mult; 114 u64 shift = clocksource_mips.shift; 115 u64 cnt = read_c0_cvmcount(); 116 117 asm ( 118 "dmultu\t%[cnt],%[mult]\n\t" 119 "nor\t%[t1],$0,%[shift]\n\t" 120 "mfhi\t%[t2]\n\t" 121 "mflo\t%[t3]\n\t" 122 "dsll\t%[t2],%[t2],1\n\t" 123 "dsrlv\t%[rv],%[t3],%[shift]\n\t" 124 "dsllv\t%[t1],%[t2],%[t1]\n\t" 125 "or\t%[rv],%[t1],%[rv]\n\t" 126 : [rv] "=&r" (rv), [t1] "=&r" (t1), [t2] "=&r" (t2), [t3] "=&r" (t3) 127 : [cnt] "r" (cnt), [mult] "r" (mult), [shift] "r" (shift) 128 : "hi", "lo"); 129 return rv; 130 } 131 132 void __init plat_time_init(void) 133 { 134 clocksource_mips.rating = 300; 135 clocksource_register_hz(&clocksource_mips, octeon_get_clock_rate()); 136 } 137 138 void __udelay(unsigned long us) 139 { 140 u64 cur, end, inc; 141 142 cur = read_c0_cvmcount(); 143 144 inc = us * octeon_udelay_factor; 145 end = cur + inc; 146 147 while (end > cur) 148 cur = read_c0_cvmcount(); 149 } 150 EXPORT_SYMBOL(__udelay); 151 152 void __ndelay(unsigned long ns) 153 { 154 u64 cur, end, inc; 155 156 cur = read_c0_cvmcount(); 157 158 inc = ((ns * octeon_ndelay_factor) >> 16); 159 end = cur + inc; 160 161 while (end > cur) 162 cur = read_c0_cvmcount(); 163 } 164 EXPORT_SYMBOL(__ndelay); 165 166 void __delay(unsigned long loops) 167 { 168 u64 cur, end; 169 170 cur = read_c0_cvmcount(); 171 end = cur + loops; 172 173 while (end > cur) 174 cur = read_c0_cvmcount(); 175 } 176 EXPORT_SYMBOL(__delay); 177 178 179 /** 180 * octeon_io_clk_delay - wait for a given number of io clock cycles to pass. 181 * 182 * We scale the wait by the clock ratio, and then wait for the 183 * corresponding number of core clocks. 184 * 185 * @count: The number of clocks to wait. 186 */ 187 void octeon_io_clk_delay(unsigned long count) 188 { 189 u64 cur, end; 190 191 cur = read_c0_cvmcount(); 192 if (rdiv != 0) { 193 end = count * rdiv; 194 if (f != 0) { 195 asm("dmultu\t%[cnt],%[f]\n\t" 196 "mfhi\t%[cnt]" 197 : [cnt] "+r" (end) 198 : [f] "r" (f) 199 : "hi", "lo"); 200 } 201 end = cur + end; 202 } else { 203 end = cur + count; 204 } 205 while (end > cur) 206 cur = read_c0_cvmcount(); 207 } 208 EXPORT_SYMBOL(octeon_io_clk_delay); 209