1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2#include <dt-bindings/interrupt-controller/mips-gic.h> 3#include <dt-bindings/gpio/gpio.h> 4#include <dt-bindings/clock/mt7621-clk.h> 5#include <dt-bindings/reset/mt7621-reset.h> 6 7/ { 8 #address-cells = <1>; 9 #size-cells = <1>; 10 compatible = "mediatek,mt7621-soc"; 11 12 cpus { 13 #address-cells = <1>; 14 #size-cells = <0>; 15 16 cpu@0 { 17 device_type = "cpu"; 18 compatible = "mips,mips1004Kc"; 19 reg = <0>; 20 }; 21 22 cpu@1 { 23 device_type = "cpu"; 24 compatible = "mips,mips1004Kc"; 25 reg = <1>; 26 }; 27 }; 28 29 cpuintc: cpuintc { 30 #address-cells = <0>; 31 #interrupt-cells = <1>; 32 interrupt-controller; 33 compatible = "mti,cpu-interrupt-controller"; 34 }; 35 36 mmc_fixed_3v3: regulator-3v3 { 37 compatible = "regulator-fixed"; 38 regulator-name = "mmc_power"; 39 regulator-min-microvolt = <3300000>; 40 regulator-max-microvolt = <3300000>; 41 enable-active-high; 42 regulator-always-on; 43 }; 44 45 mmc_fixed_1v8_io: regulator-1v8 { 46 compatible = "regulator-fixed"; 47 regulator-name = "mmc_io"; 48 regulator-min-microvolt = <1800000>; 49 regulator-max-microvolt = <1800000>; 50 enable-active-high; 51 regulator-always-on; 52 }; 53 54 palmbus: palmbus@1e000000 { 55 compatible = "palmbus"; 56 reg = <0x1e000000 0x100000>; 57 ranges = <0x0 0x1e000000 0x0fffff>; 58 59 #address-cells = <1>; 60 #size-cells = <1>; 61 62 sysc: syscon@0 { 63 compatible = "mediatek,mt7621-sysc", "syscon"; 64 reg = <0x0 0x100>; 65 #clock-cells = <1>; 66 #reset-cells = <1>; 67 ralink,memctl = <&memc>; 68 clock-output-names = "xtal", "cpu", "bus", 69 "50m", "125m", "150m", 70 "250m", "270m"; 71 }; 72 73 wdt: wdt@100 { 74 compatible = "mediatek,mt7621-wdt"; 75 reg = <0x100 0x100>; 76 }; 77 78 gpio: gpio@600 { 79 #gpio-cells = <2>; 80 #interrupt-cells = <2>; 81 compatible = "mediatek,mt7621-gpio"; 82 gpio-controller; 83 gpio-ranges = <&pinctrl 0 0 95>; 84 interrupt-controller; 85 reg = <0x600 0x100>; 86 interrupt-parent = <&gic>; 87 interrupts = <GIC_SHARED 12 IRQ_TYPE_LEVEL_HIGH>; 88 }; 89 90 i2c: i2c@900 { 91 compatible = "mediatek,mt7621-i2c"; 92 reg = <0x900 0x100>; 93 94 clocks = <&sysc MT7621_CLK_I2C>; 95 clock-names = "i2c"; 96 resets = <&sysc MT7621_RST_I2C>; 97 reset-names = "i2c"; 98 99 #address-cells = <1>; 100 #size-cells = <0>; 101 102 status = "disabled"; 103 104 pinctrl-names = "default"; 105 pinctrl-0 = <&i2c_pins>; 106 }; 107 108 memc: memory-controller@5000 { 109 compatible = "mediatek,mt7621-memc", "syscon"; 110 reg = <0x5000 0x1000>; 111 }; 112 113 serial0: serial@c00 { 114 compatible = "ns16550a"; 115 reg = <0xc00 0x100>; 116 117 clocks = <&sysc MT7621_CLK_UART1>; 118 119 interrupt-parent = <&gic>; 120 interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>; 121 122 reg-shift = <2>; 123 reg-io-width = <4>; 124 no-loopback-test; 125 }; 126 127 spi0: spi@b00 { 128 status = "disabled"; 129 130 compatible = "ralink,mt7621-spi"; 131 reg = <0xb00 0x100>; 132 133 clocks = <&sysc MT7621_CLK_SPI>; 134 clock-names = "spi"; 135 136 resets = <&sysc MT7621_RST_SPI>; 137 reset-names = "spi"; 138 139 #address-cells = <1>; 140 #size-cells = <0>; 141 142 pinctrl-names = "default"; 143 pinctrl-0 = <&spi_pins>; 144 }; 145 }; 146 147 pinctrl: pinctrl { 148 compatible = "ralink,mt7621-pinctrl"; 149 150 i2c_pins: i2c0-pins { 151 pinmux { 152 groups = "i2c"; 153 function = "i2c"; 154 }; 155 }; 156 157 spi_pins: spi0-pins { 158 pinmux { 159 groups = "spi"; 160 function = "spi"; 161 }; 162 }; 163 164 uart1_pins: uart1-pins { 165 pinmux { 166 groups = "uart1"; 167 function = "uart1"; 168 }; 169 }; 170 171 uart2_pins: uart2-pins { 172 pinmux { 173 groups = "uart2"; 174 function = "uart2"; 175 }; 176 }; 177 178 uart3_pins: uart3-pins { 179 pinmux { 180 groups = "uart3"; 181 function = "uart3"; 182 }; 183 }; 184 185 rgmii1_pins: rgmii1-pins { 186 pinmux { 187 groups = "rgmii1"; 188 function = "rgmii1"; 189 }; 190 }; 191 192 rgmii2_pins: rgmii2-pins { 193 pinmux { 194 groups = "rgmii2"; 195 function = "rgmii2"; 196 }; 197 }; 198 199 mdio_pins: mdio0-pins { 200 pinmux { 201 groups = "mdio"; 202 function = "mdio"; 203 }; 204 }; 205 206 pcie_pins: pcie0-pins { 207 pinmux { 208 groups = "pcie"; 209 function = "gpio"; 210 }; 211 }; 212 213 nand_pins: nand0-pins { 214 spi-pinmux { 215 groups = "spi"; 216 function = "nand1"; 217 }; 218 219 sdhci-pinmux { 220 groups = "sdhci"; 221 function = "nand2"; 222 }; 223 }; 224 225 sdhci_pins: sdhci0-pins { 226 pinmux { 227 groups = "sdhci"; 228 function = "sdhci"; 229 }; 230 }; 231 }; 232 233 mmc: mmc@1e130000 { 234 status = "disabled"; 235 236 compatible = "mediatek,mt7620-mmc"; 237 reg = <0x1e130000 0x4000>; 238 239 bus-width = <4>; 240 max-frequency = <48000000>; 241 cap-sd-highspeed; 242 cap-mmc-highspeed; 243 vmmc-supply = <&mmc_fixed_3v3>; 244 vqmmc-supply = <&mmc_fixed_1v8_io>; 245 disable-wp; 246 247 pinctrl-names = "default", "state_uhs"; 248 pinctrl-0 = <&sdhci_pins>; 249 pinctrl-1 = <&sdhci_pins>; 250 251 clocks = <&sysc MT7621_CLK_SHXC>, 252 <&sysc MT7621_CLK_50M>; 253 clock-names = "source", "hclk"; 254 255 interrupt-parent = <&gic>; 256 interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>; 257 }; 258 259 usb: usb@1e1c0000 { 260 compatible = "mediatek,mt8173-xhci", "mediatek,mtk-xhci"; 261 reg = <0x1e1c0000 0x1000 262 0x1e1d0700 0x0100>; 263 reg-names = "mac", "ippc"; 264 265 clocks = <&sysc MT7621_CLK_XTAL>; 266 clock-names = "sys_ck"; 267 268 interrupt-parent = <&gic>; 269 interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>; 270 }; 271 272 gic: interrupt-controller@1fbc0000 { 273 compatible = "mti,gic"; 274 reg = <0x1fbc0000 0x2000>; 275 276 interrupt-controller; 277 #interrupt-cells = <3>; 278 279 mti,reserved-cpu-vectors = <7>; 280 281 timer { 282 compatible = "mti,gic-timer"; 283 interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>; 284 clocks = <&sysc MT7621_CLK_CPU>; 285 }; 286 }; 287 288 cpc: cpc@1fbf0000 { 289 compatible = "mti,mips-cpc"; 290 reg = <0x1fbf0000 0x8000>; 291 }; 292 293 cdmm: cdmm@1fbf8000 { 294 compatible = "mti,mips-cdmm"; 295 reg = <0x1fbf8000 0x8000>; 296 }; 297 298 ethernet: ethernet@1e100000 { 299 compatible = "mediatek,mt7621-eth"; 300 reg = <0x1e100000 0x10000>; 301 302 clocks = <&sysc MT7621_CLK_FE>, 303 <&sysc MT7621_CLK_ETH>; 304 clock-names = "fe", "ethif"; 305 306 #address-cells = <1>; 307 #size-cells = <0>; 308 309 resets = <&sysc MT7621_RST_FE &sysc MT7621_RST_ETH>; 310 reset-names = "fe", "eth"; 311 312 interrupt-parent = <&gic>; 313 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>; 314 315 mediatek,ethsys = <&sysc>; 316 317 pinctrl-names = "default"; 318 pinctrl-0 = <&mdio_pins>, <&rgmii1_pins>, <&rgmii2_pins>; 319 320 gmac0: mac@0 { 321 compatible = "mediatek,eth-mac"; 322 reg = <0>; 323 phy-mode = "trgmii"; 324 325 fixed-link { 326 speed = <1000>; 327 full-duplex; 328 pause; 329 }; 330 }; 331 332 gmac1: mac@1 { 333 compatible = "mediatek,eth-mac"; 334 reg = <1>; 335 status = "disabled"; 336 phy-mode = "rgmii"; 337 }; 338 339 mdio: mdio-bus { 340 #address-cells = <1>; 341 #size-cells = <0>; 342 343 switch0: switch@1f { 344 compatible = "mediatek,mt7621"; 345 reg = <0x1f>; 346 mediatek,mcm; 347 resets = <&sysc MT7621_RST_MCM>; 348 reset-names = "mcm"; 349 interrupt-controller; 350 #interrupt-cells = <1>; 351 interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>; 352 353 ports { 354 #address-cells = <1>; 355 #size-cells = <0>; 356 357 port@0 { 358 status = "disabled"; 359 reg = <0>; 360 label = "lan0"; 361 }; 362 363 port@1 { 364 status = "disabled"; 365 reg = <1>; 366 label = "lan1"; 367 }; 368 369 port@2 { 370 status = "disabled"; 371 reg = <2>; 372 label = "lan2"; 373 }; 374 375 port@3 { 376 status = "disabled"; 377 reg = <3>; 378 label = "lan3"; 379 }; 380 381 port@4 { 382 status = "disabled"; 383 reg = <4>; 384 label = "lan4"; 385 }; 386 387 port@6 { 388 reg = <6>; 389 label = "cpu"; 390 ethernet = <&gmac0>; 391 phy-mode = "trgmii"; 392 393 fixed-link { 394 speed = <1000>; 395 full-duplex; 396 pause; 397 }; 398 }; 399 }; 400 }; 401 }; 402 }; 403 404 pcie: pcie@1e140000 { 405 compatible = "mediatek,mt7621-pci"; 406 reg = <0x1e140000 0x100>, /* host-pci bridge registers */ 407 <0x1e142000 0x100>, /* pcie port 0 RC control registers */ 408 <0x1e143000 0x100>, /* pcie port 1 RC control registers */ 409 <0x1e144000 0x100>; /* pcie port 2 RC control registers */ 410 #address-cells = <3>; 411 #size-cells = <2>; 412 413 pinctrl-names = "default"; 414 pinctrl-0 = <&pcie_pins>; 415 416 device_type = "pci"; 417 418 ranges = <0x02000000 0 0x60000000 0x60000000 0 0x10000000>, /* pci memory */ 419 <0x01000000 0 0x00000000 0x1e160000 0 0x00010000>; /* io space */ 420 421 #interrupt-cells = <1>; 422 interrupt-map-mask = <0xF800 0 0 0>; 423 interrupt-map = <0x0000 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>, 424 <0x0800 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>, 425 <0x1000 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>; 426 427 status = "disabled"; 428 429 reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>; 430 431 pcie@0,0 { 432 reg = <0x0000 0 0 0 0>; 433 #address-cells = <3>; 434 #size-cells = <2>; 435 device_type = "pci"; 436 #interrupt-cells = <1>; 437 interrupt-map-mask = <0 0 0 0>; 438 interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>; 439 resets = <&sysc MT7621_RST_PCIE0>; 440 clocks = <&sysc MT7621_CLK_PCIE0>; 441 phys = <&pcie0_phy 1>; 442 phy-names = "pcie-phy0"; 443 ranges; 444 }; 445 446 pcie@1,0 { 447 reg = <0x0800 0 0 0 0>; 448 #address-cells = <3>; 449 #size-cells = <2>; 450 device_type = "pci"; 451 #interrupt-cells = <1>; 452 interrupt-map-mask = <0 0 0 0>; 453 interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>; 454 resets = <&sysc MT7621_RST_PCIE1>; 455 clocks = <&sysc MT7621_CLK_PCIE1>; 456 phys = <&pcie0_phy 1>; 457 phy-names = "pcie-phy1"; 458 ranges; 459 }; 460 461 pcie@2,0 { 462 reg = <0x1000 0 0 0 0>; 463 #address-cells = <3>; 464 #size-cells = <2>; 465 device_type = "pci"; 466 #interrupt-cells = <1>; 467 interrupt-map-mask = <0 0 0 0>; 468 interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>; 469 resets = <&sysc MT7621_RST_PCIE2>; 470 clocks = <&sysc MT7621_CLK_PCIE2>; 471 phys = <&pcie2_phy 0>; 472 phy-names = "pcie-phy2"; 473 ranges; 474 }; 475 }; 476 477 pcie0_phy: pcie-phy@1e149000 { 478 compatible = "mediatek,mt7621-pci-phy"; 479 reg = <0x1e149000 0x0700>; 480 clocks = <&sysc MT7621_CLK_XTAL>; 481 #phy-cells = <1>; 482 }; 483 484 pcie2_phy: pcie-phy@1e14a000 { 485 compatible = "mediatek,mt7621-pci-phy"; 486 reg = <0x1e14a000 0x0700>; 487 clocks = <&sysc MT7621_CLK_XTAL>; 488 #phy-cells = <1>; 489 }; 490}; 491