1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2#include <dt-bindings/interrupt-controller/mips-gic.h> 3#include <dt-bindings/gpio/gpio.h> 4#include <dt-bindings/clock/mt7621-clk.h> 5#include <dt-bindings/reset/mt7621-reset.h> 6 7/ { 8 #address-cells = <1>; 9 #size-cells = <1>; 10 compatible = "mediatek,mt7621-soc"; 11 12 cpus { 13 #address-cells = <1>; 14 #size-cells = <0>; 15 16 cpu@0 { 17 device_type = "cpu"; 18 compatible = "mips,mips1004Kc"; 19 reg = <0>; 20 }; 21 22 cpu@1 { 23 device_type = "cpu"; 24 compatible = "mips,mips1004Kc"; 25 reg = <1>; 26 }; 27 }; 28 29 cpuintc: cpuintc { 30 #address-cells = <0>; 31 #interrupt-cells = <1>; 32 interrupt-controller; 33 compatible = "mti,cpu-interrupt-controller"; 34 }; 35 36 mmc_fixed_3v3: regulator-3v3 { 37 compatible = "regulator-fixed"; 38 regulator-name = "mmc_power"; 39 regulator-min-microvolt = <3300000>; 40 regulator-max-microvolt = <3300000>; 41 enable-active-high; 42 regulator-always-on; 43 }; 44 45 mmc_fixed_1v8_io: regulator-1v8 { 46 compatible = "regulator-fixed"; 47 regulator-name = "mmc_io"; 48 regulator-min-microvolt = <1800000>; 49 regulator-max-microvolt = <1800000>; 50 enable-active-high; 51 regulator-always-on; 52 }; 53 54 palmbus: palmbus@1e000000 { 55 compatible = "palmbus"; 56 reg = <0x1e000000 0x100000>; 57 ranges = <0x0 0x1e000000 0x0fffff>; 58 59 #address-cells = <1>; 60 #size-cells = <1>; 61 62 sysc: syscon@0 { 63 compatible = "mediatek,mt7621-sysc", "syscon"; 64 reg = <0x0 0x100>; 65 #clock-cells = <1>; 66 #reset-cells = <1>; 67 ralink,memctl = <&memc>; 68 clock-output-names = "xtal", "cpu", "bus", 69 "50m", "125m", "150m", 70 "250m", "270m"; 71 }; 72 73 wdt: watchdog@100 { 74 compatible = "mediatek,mt7621-wdt"; 75 reg = <0x100 0x100>; 76 mediatek,sysctl = <&sysc>; 77 }; 78 79 gpio: gpio@600 { 80 #gpio-cells = <2>; 81 #interrupt-cells = <2>; 82 compatible = "mediatek,mt7621-gpio"; 83 gpio-controller; 84 gpio-ranges = <&pinctrl 0 0 95>; 85 interrupt-controller; 86 reg = <0x600 0x100>; 87 interrupt-parent = <&gic>; 88 interrupts = <GIC_SHARED 12 IRQ_TYPE_LEVEL_HIGH>; 89 }; 90 91 i2c: i2c@900 { 92 compatible = "mediatek,mt7621-i2c"; 93 reg = <0x900 0x100>; 94 95 clocks = <&sysc MT7621_CLK_I2C>; 96 clock-names = "i2c"; 97 resets = <&sysc MT7621_RST_I2C>; 98 reset-names = "i2c"; 99 100 #address-cells = <1>; 101 #size-cells = <0>; 102 103 status = "disabled"; 104 105 pinctrl-names = "default"; 106 pinctrl-0 = <&i2c_pins>; 107 }; 108 109 memc: memory-controller@5000 { 110 compatible = "mediatek,mt7621-memc", "syscon"; 111 reg = <0x5000 0x1000>; 112 }; 113 114 serial0: serial@c00 { 115 compatible = "ns16550a"; 116 reg = <0xc00 0x100>; 117 118 clocks = <&sysc MT7621_CLK_UART1>; 119 120 interrupt-parent = <&gic>; 121 interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>; 122 123 reg-shift = <2>; 124 reg-io-width = <4>; 125 no-loopback-test; 126 }; 127 128 spi0: spi@b00 { 129 status = "disabled"; 130 131 compatible = "ralink,mt7621-spi"; 132 reg = <0xb00 0x100>; 133 134 clocks = <&sysc MT7621_CLK_SPI>; 135 clock-names = "spi"; 136 137 resets = <&sysc MT7621_RST_SPI>; 138 reset-names = "spi"; 139 140 #address-cells = <1>; 141 #size-cells = <0>; 142 143 pinctrl-names = "default"; 144 pinctrl-0 = <&spi_pins>; 145 }; 146 }; 147 148 pinctrl: pinctrl { 149 compatible = "ralink,mt7621-pinctrl"; 150 151 i2c_pins: i2c0-pins { 152 pinmux { 153 groups = "i2c"; 154 function = "i2c"; 155 }; 156 }; 157 158 spi_pins: spi0-pins { 159 pinmux { 160 groups = "spi"; 161 function = "spi"; 162 }; 163 }; 164 165 uart1_pins: uart1-pins { 166 pinmux { 167 groups = "uart1"; 168 function = "uart1"; 169 }; 170 }; 171 172 uart2_pins: uart2-pins { 173 pinmux { 174 groups = "uart2"; 175 function = "uart2"; 176 }; 177 }; 178 179 uart3_pins: uart3-pins { 180 pinmux { 181 groups = "uart3"; 182 function = "uart3"; 183 }; 184 }; 185 186 rgmii1_pins: rgmii1-pins { 187 pinmux { 188 groups = "rgmii1"; 189 function = "rgmii1"; 190 }; 191 }; 192 193 rgmii2_pins: rgmii2-pins { 194 pinmux { 195 groups = "rgmii2"; 196 function = "rgmii2"; 197 }; 198 }; 199 200 mdio_pins: mdio0-pins { 201 pinmux { 202 groups = "mdio"; 203 function = "mdio"; 204 }; 205 }; 206 207 pcie_pins: pcie0-pins { 208 pinmux { 209 groups = "pcie"; 210 function = "gpio"; 211 }; 212 }; 213 214 nand_pins: nand0-pins { 215 spi-pinmux { 216 groups = "spi"; 217 function = "nand1"; 218 }; 219 220 sdhci-pinmux { 221 groups = "sdhci"; 222 function = "nand2"; 223 }; 224 }; 225 226 sdhci_pins: sdhci0-pins { 227 pinmux { 228 groups = "sdhci"; 229 function = "sdhci"; 230 }; 231 }; 232 }; 233 234 mmc: mmc@1e130000 { 235 status = "disabled"; 236 237 compatible = "mediatek,mt7620-mmc"; 238 reg = <0x1e130000 0x4000>; 239 240 bus-width = <4>; 241 max-frequency = <48000000>; 242 cap-sd-highspeed; 243 cap-mmc-highspeed; 244 vmmc-supply = <&mmc_fixed_3v3>; 245 vqmmc-supply = <&mmc_fixed_1v8_io>; 246 disable-wp; 247 248 pinctrl-names = "default", "state_uhs"; 249 pinctrl-0 = <&sdhci_pins>; 250 pinctrl-1 = <&sdhci_pins>; 251 252 clocks = <&sysc MT7621_CLK_SHXC>, 253 <&sysc MT7621_CLK_50M>; 254 clock-names = "source", "hclk"; 255 256 interrupt-parent = <&gic>; 257 interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>; 258 }; 259 260 usb: usb@1e1c0000 { 261 compatible = "mediatek,mt8173-xhci", "mediatek,mtk-xhci"; 262 reg = <0x1e1c0000 0x1000 263 0x1e1d0700 0x0100>; 264 reg-names = "mac", "ippc"; 265 266 clocks = <&sysc MT7621_CLK_XTAL>; 267 clock-names = "sys_ck"; 268 269 interrupt-parent = <&gic>; 270 interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>; 271 }; 272 273 gic: interrupt-controller@1fbc0000 { 274 compatible = "mti,gic"; 275 reg = <0x1fbc0000 0x2000>; 276 277 interrupt-controller; 278 #interrupt-cells = <3>; 279 280 mti,reserved-cpu-vectors = <7>; 281 282 timer { 283 compatible = "mti,gic-timer"; 284 interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>; 285 clocks = <&sysc MT7621_CLK_CPU>; 286 }; 287 }; 288 289 cpc: cpc@1fbf0000 { 290 compatible = "mti,mips-cpc"; 291 reg = <0x1fbf0000 0x8000>; 292 }; 293 294 cdmm: cdmm@1fbf8000 { 295 compatible = "mti,mips-cdmm"; 296 reg = <0x1fbf8000 0x8000>; 297 }; 298 299 ethernet: ethernet@1e100000 { 300 compatible = "mediatek,mt7621-eth"; 301 reg = <0x1e100000 0x10000>; 302 303 clocks = <&sysc MT7621_CLK_FE>, 304 <&sysc MT7621_CLK_ETH>; 305 clock-names = "fe", "ethif"; 306 307 #address-cells = <1>; 308 #size-cells = <0>; 309 310 resets = <&sysc MT7621_RST_FE &sysc MT7621_RST_ETH>; 311 reset-names = "fe", "eth"; 312 313 interrupt-parent = <&gic>; 314 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>; 315 316 mediatek,ethsys = <&sysc>; 317 318 pinctrl-names = "default"; 319 pinctrl-0 = <&mdio_pins>, <&rgmii1_pins>, <&rgmii2_pins>; 320 321 gmac0: mac@0 { 322 compatible = "mediatek,eth-mac"; 323 reg = <0>; 324 phy-mode = "trgmii"; 325 326 fixed-link { 327 speed = <1000>; 328 full-duplex; 329 pause; 330 }; 331 }; 332 333 gmac1: mac@1 { 334 compatible = "mediatek,eth-mac"; 335 reg = <1>; 336 phy-mode = "rgmii"; 337 338 fixed-link { 339 speed = <1000>; 340 full-duplex; 341 pause; 342 }; 343 }; 344 345 mdio: mdio-bus { 346 #address-cells = <1>; 347 #size-cells = <0>; 348 349 switch0: switch@1f { 350 compatible = "mediatek,mt7621"; 351 reg = <0x1f>; 352 mediatek,mcm; 353 resets = <&sysc MT7621_RST_MCM>; 354 reset-names = "mcm"; 355 interrupt-controller; 356 #interrupt-cells = <1>; 357 interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>; 358 359 ports { 360 #address-cells = <1>; 361 #size-cells = <0>; 362 363 port@0 { 364 status = "disabled"; 365 reg = <0>; 366 label = "swp0"; 367 }; 368 369 port@1 { 370 status = "disabled"; 371 reg = <1>; 372 label = "swp1"; 373 }; 374 375 port@2 { 376 status = "disabled"; 377 reg = <2>; 378 label = "swp2"; 379 }; 380 381 port@3 { 382 status = "disabled"; 383 reg = <3>; 384 label = "swp3"; 385 }; 386 387 port@4 { 388 status = "disabled"; 389 reg = <4>; 390 label = "swp4"; 391 }; 392 393 port@5 { 394 reg = <5>; 395 ethernet = <&gmac1>; 396 phy-mode = "rgmii"; 397 398 fixed-link { 399 speed = <1000>; 400 full-duplex; 401 pause; 402 }; 403 }; 404 405 port@6 { 406 reg = <6>; 407 ethernet = <&gmac0>; 408 phy-mode = "trgmii"; 409 410 fixed-link { 411 speed = <1000>; 412 full-duplex; 413 pause; 414 }; 415 }; 416 }; 417 }; 418 }; 419 }; 420 421 pcie: pcie@1e140000 { 422 compatible = "mediatek,mt7621-pci"; 423 reg = <0x1e140000 0x100>, /* host-pci bridge registers */ 424 <0x1e142000 0x100>, /* pcie port 0 RC control registers */ 425 <0x1e143000 0x100>, /* pcie port 1 RC control registers */ 426 <0x1e144000 0x100>; /* pcie port 2 RC control registers */ 427 #address-cells = <3>; 428 #size-cells = <2>; 429 430 pinctrl-names = "default"; 431 pinctrl-0 = <&pcie_pins>; 432 433 device_type = "pci"; 434 435 ranges = <0x02000000 0 0x60000000 0x60000000 0 0x10000000>, /* pci memory */ 436 <0x01000000 0 0x00000000 0x1e160000 0 0x00010000>; /* io space */ 437 438 #interrupt-cells = <1>; 439 interrupt-map-mask = <0xF800 0 0 0>; 440 interrupt-map = <0x0000 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>, 441 <0x0800 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>, 442 <0x1000 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>; 443 444 status = "disabled"; 445 446 reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>; 447 448 pcie@0,0 { 449 reg = <0x0000 0 0 0 0>; 450 #address-cells = <3>; 451 #size-cells = <2>; 452 device_type = "pci"; 453 #interrupt-cells = <1>; 454 interrupt-map-mask = <0 0 0 0>; 455 interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>; 456 resets = <&sysc MT7621_RST_PCIE0>; 457 clocks = <&sysc MT7621_CLK_PCIE0>; 458 phys = <&pcie0_phy 1>; 459 phy-names = "pcie-phy0"; 460 ranges; 461 }; 462 463 pcie@1,0 { 464 reg = <0x0800 0 0 0 0>; 465 #address-cells = <3>; 466 #size-cells = <2>; 467 device_type = "pci"; 468 #interrupt-cells = <1>; 469 interrupt-map-mask = <0 0 0 0>; 470 interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>; 471 resets = <&sysc MT7621_RST_PCIE1>; 472 clocks = <&sysc MT7621_CLK_PCIE1>; 473 phys = <&pcie0_phy 1>; 474 phy-names = "pcie-phy1"; 475 ranges; 476 }; 477 478 pcie@2,0 { 479 reg = <0x1000 0 0 0 0>; 480 #address-cells = <3>; 481 #size-cells = <2>; 482 device_type = "pci"; 483 #interrupt-cells = <1>; 484 interrupt-map-mask = <0 0 0 0>; 485 interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>; 486 resets = <&sysc MT7621_RST_PCIE2>; 487 clocks = <&sysc MT7621_CLK_PCIE2>; 488 phys = <&pcie2_phy 0>; 489 phy-names = "pcie-phy2"; 490 ranges; 491 }; 492 }; 493 494 pcie0_phy: pcie-phy@1e149000 { 495 compatible = "mediatek,mt7621-pci-phy"; 496 reg = <0x1e149000 0x0700>; 497 clocks = <&sysc MT7621_CLK_XTAL>; 498 #phy-cells = <1>; 499 }; 500 501 pcie2_phy: pcie-phy@1e14a000 { 502 compatible = "mediatek,mt7621-pci-phy"; 503 reg = <0x1e14a000 0x0700>; 504 clocks = <&sysc MT7621_CLK_XTAL>; 505 #phy-cells = <1>; 506 }; 507}; 508