1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/ath79-clk.h> 3 4/ { 5 compatible = "qca,ar9331"; 6 7 #address-cells = <1>; 8 #size-cells = <1>; 9 10 cpus { 11 #address-cells = <1>; 12 #size-cells = <0>; 13 14 cpu@0 { 15 device_type = "cpu"; 16 compatible = "mips,mips24Kc"; 17 clocks = <&pll ATH79_CLK_CPU>; 18 reg = <0>; 19 }; 20 }; 21 22 cpuintc: interrupt-controller { 23 compatible = "qca,ar7100-cpu-intc"; 24 25 interrupt-controller; 26 #interrupt-cells = <1>; 27 28 qca,ddr-wb-channel-interrupts = <2>, <3>; 29 qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>; 30 }; 31 32 ref: ref { 33 compatible = "fixed-clock"; 34 #clock-cells = <0>; 35 }; 36 37 ahb { 38 compatible = "simple-bus"; 39 ranges; 40 41 #address-cells = <1>; 42 #size-cells = <1>; 43 44 interrupt-parent = <&cpuintc>; 45 46 apb { 47 compatible = "simple-bus"; 48 ranges; 49 50 #address-cells = <1>; 51 #size-cells = <1>; 52 53 interrupt-parent = <&miscintc>; 54 55 ddr_ctrl: memory-controller@18000000 { 56 compatible = "qca,ar7240-ddr-controller"; 57 reg = <0x18000000 0x100>; 58 59 #qca,ddr-wb-channel-cells = <1>; 60 }; 61 62 uart: serial@18020000 { 63 compatible = "qca,ar9330-uart"; 64 reg = <0x18020000 0x14>; 65 66 interrupts = <3>; 67 68 clocks = <&ref>; 69 clock-names = "uart"; 70 71 status = "disabled"; 72 }; 73 74 gpio: gpio@18040000 { 75 compatible = "qca,ar7100-gpio"; 76 reg = <0x18040000 0x34>; 77 interrupts = <2>; 78 79 ngpios = <30>; 80 81 gpio-controller; 82 #gpio-cells = <2>; 83 84 interrupt-controller; 85 #interrupt-cells = <2>; 86 87 status = "disabled"; 88 }; 89 90 pll: pll-controller@18050000 { 91 compatible = "qca,ar9330-pll"; 92 reg = <0x18050000 0x100>; 93 94 clocks = <&ref>; 95 clock-names = "ref"; 96 97 #clock-cells = <1>; 98 }; 99 100 miscintc: interrupt-controller@18060010 { 101 compatible = "qca,ar7240-misc-intc"; 102 reg = <0x18060010 0x8>; 103 104 interrupt-parent = <&cpuintc>; 105 interrupts = <6>; 106 107 interrupt-controller; 108 #interrupt-cells = <1>; 109 }; 110 111 rst: reset-controller@1806001c { 112 compatible = "qca,ar7100-reset"; 113 reg = <0x1806001c 0x4>; 114 115 #reset-cells = <1>; 116 }; 117 }; 118 119 eth0: ethernet@19000000 { 120 compatible = "qca,ar9330-eth"; 121 reg = <0x19000000 0x200>; 122 interrupts = <4>; 123 124 resets = <&rst 9>, <&rst 22>; 125 reset-names = "mac", "mdio"; 126 clocks = <&pll ATH79_CLK_AHB>, <&pll ATH79_CLK_AHB>; 127 clock-names = "eth", "mdio"; 128 129 phy-mode = "mii"; 130 phy-handle = <&phy_port4>; 131 132 status = "disabled"; 133 }; 134 135 eth1: ethernet@1a000000 { 136 compatible = "qca,ar9330-eth"; 137 reg = <0x1a000000 0x200>; 138 interrupts = <5>; 139 resets = <&rst 13>, <&rst 23>; 140 reset-names = "mac", "mdio"; 141 clocks = <&pll ATH79_CLK_AHB>, <&pll ATH79_CLK_AHB>; 142 clock-names = "eth", "mdio"; 143 144 phy-mode = "gmii"; 145 146 status = "disabled"; 147 148 fixed-link { 149 speed = <1000>; 150 full-duplex; 151 pause; 152 }; 153 154 mdio { 155 #address-cells = <1>; 156 #size-cells = <0>; 157 158 switch10: switch@10 { 159 #address-cells = <1>; 160 #size-cells = <0>; 161 162 compatible = "qca,ar9331-switch"; 163 reg = <0x10>; 164 resets = <&rst 8>; 165 reset-names = "switch"; 166 167 interrupt-parent = <&miscintc>; 168 interrupts = <12>; 169 170 interrupt-controller; 171 #interrupt-cells = <1>; 172 173 ports { 174 #address-cells = <1>; 175 #size-cells = <0>; 176 177 switch_port0: port@0 { 178 reg = <0x0>; 179 label = "cpu"; 180 ethernet = <ð1>; 181 182 phy-mode = "gmii"; 183 184 fixed-link { 185 speed = <1000>; 186 full-duplex; 187 pause; 188 }; 189 }; 190 191 switch_port1: port@1 { 192 reg = <0x1>; 193 phy-handle = <&phy_port0>; 194 phy-mode = "internal"; 195 196 status = "disabled"; 197 }; 198 199 switch_port2: port@2 { 200 reg = <0x2>; 201 phy-handle = <&phy_port1>; 202 phy-mode = "internal"; 203 204 status = "disabled"; 205 }; 206 207 switch_port3: port@3 { 208 reg = <0x3>; 209 phy-handle = <&phy_port2>; 210 phy-mode = "internal"; 211 212 status = "disabled"; 213 }; 214 215 switch_port4: port@4 { 216 reg = <0x4>; 217 phy-handle = <&phy_port3>; 218 phy-mode = "internal"; 219 220 status = "disabled"; 221 }; 222 }; 223 224 mdio { 225 #address-cells = <1>; 226 #size-cells = <0>; 227 228 interrupt-parent = <&switch10>; 229 230 phy_port0: phy@0 { 231 reg = <0x0>; 232 interrupts = <0>; 233 status = "disabled"; 234 }; 235 236 phy_port1: phy@1 { 237 reg = <0x1>; 238 interrupts = <0>; 239 status = "disabled"; 240 }; 241 242 phy_port2: phy@2 { 243 reg = <0x2>; 244 interrupts = <0>; 245 status = "disabled"; 246 }; 247 248 phy_port3: phy@3 { 249 reg = <0x3>; 250 interrupts = <0>; 251 status = "disabled"; 252 }; 253 254 phy_port4: phy@4 { 255 reg = <0x4>; 256 interrupts = <0>; 257 status = "disabled"; 258 }; 259 }; 260 }; 261 }; 262 }; 263 264 usb: usb@1b000100 { 265 compatible = "chipidea,usb2"; 266 reg = <0x1b000000 0x200>; 267 268 interrupts = <3>; 269 resets = <&rst 5>; 270 271 phy-names = "usb-phy"; 272 phys = <&usb_phy>; 273 274 status = "disabled"; 275 }; 276 277 spi: spi@1f000000 { 278 compatible = "qca,ar7100-spi"; 279 reg = <0x1f000000 0x10>; 280 281 clocks = <&pll ATH79_CLK_AHB>; 282 clock-names = "ahb"; 283 284 #address-cells = <1>; 285 #size-cells = <0>; 286 287 status = "disabled"; 288 }; 289 }; 290 291 usb_phy: usb-phy { 292 compatible = "qca,ar7100-usb-phy"; 293 294 reset-names = "phy", "suspend-override"; 295 resets = <&rst 4>, <&rst 3>; 296 297 #phy-cells = <0>; 298 299 status = "disabled"; 300 }; 301}; 302