1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/ath79-clk.h> 3 4/ { 5 compatible = "qca,ar9132"; 6 7 #address-cells = <1>; 8 #size-cells = <1>; 9 10 cpus { 11 #address-cells = <1>; 12 #size-cells = <0>; 13 14 cpu@0 { 15 device_type = "cpu"; 16 compatible = "mips,mips24Kc"; 17 clocks = <&pll ATH79_CLK_CPU>; 18 reg = <0>; 19 }; 20 }; 21 22 cpuintc: interrupt-controller { 23 compatible = "qca,ar9132-cpu-intc", "qca,ar7100-cpu-intc"; 24 25 interrupt-controller; 26 #interrupt-cells = <1>; 27 28 qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>; 29 qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>, 30 <&ddr_ctrl 0>, <&ddr_ctrl 1>; 31 }; 32 33 ahb { 34 compatible = "simple-bus"; 35 ranges; 36 37 #address-cells = <1>; 38 #size-cells = <1>; 39 40 interrupt-parent = <&cpuintc>; 41 42 apb { 43 compatible = "simple-bus"; 44 ranges; 45 46 #address-cells = <1>; 47 #size-cells = <1>; 48 49 interrupt-parent = <&miscintc>; 50 51 ddr_ctrl: memory-controller@18000000 { 52 compatible = "qca,ar9132-ddr-controller", 53 "qca,ar7240-ddr-controller"; 54 reg = <0x18000000 0x100>; 55 56 #qca,ddr-wb-channel-cells = <1>; 57 }; 58 59 uart: uart@18020000 { 60 compatible = "ns8250"; 61 reg = <0x18020000 0x20>; 62 interrupts = <3>; 63 64 clocks = <&pll ATH79_CLK_AHB>; 65 clock-names = "uart"; 66 67 reg-io-width = <4>; 68 reg-shift = <2>; 69 no-loopback-test; 70 71 status = "disabled"; 72 }; 73 74 gpio: gpio@18040000 { 75 compatible = "qca,ar9132-gpio", 76 "qca,ar7100-gpio"; 77 reg = <0x18040000 0x30>; 78 interrupts = <2>; 79 80 ngpios = <22>; 81 82 gpio-controller; 83 #gpio-cells = <2>; 84 85 interrupt-controller; 86 #interrupt-cells = <2>; 87 }; 88 89 pll: pll-controller@18050000 { 90 compatible = "qca,ar9132-pll", 91 "qca,ar9130-pll"; 92 reg = <0x18050000 0x20>; 93 94 clock-names = "ref"; 95 /* The board must provides the ref clock */ 96 97 #clock-cells = <1>; 98 clock-output-names = "cpu", "ddr", "ahb"; 99 }; 100 101 wdt: wdt@18060008 { 102 compatible = "qca,ar7130-wdt"; 103 reg = <0x18060008 0x8>; 104 105 interrupts = <4>; 106 107 clocks = <&pll ATH79_CLK_AHB>; 108 clock-names = "wdt"; 109 }; 110 111 miscintc: interrupt-controller@18060010 { 112 compatible = "qca,ar9132-misc-intc", 113 "qca,ar7100-misc-intc"; 114 reg = <0x18060010 0x8>; 115 116 interrupt-parent = <&cpuintc>; 117 interrupts = <6>; 118 119 interrupt-controller; 120 #interrupt-cells = <1>; 121 }; 122 123 rst: reset-controller@1806001c { 124 compatible = "qca,ar9132-reset", 125 "qca,ar7100-reset"; 126 reg = <0x1806001c 0x4>; 127 128 #reset-cells = <1>; 129 }; 130 }; 131 132 usb: usb@1b000100 { 133 compatible = "qca,ar7100-ehci", "generic-ehci"; 134 reg = <0x1b000100 0x100>; 135 136 interrupts = <3>; 137 resets = <&rst 5>; 138 139 has-transaction-translator; 140 141 phy-names = "usb"; 142 phys = <&usb_phy>; 143 144 status = "disabled"; 145 }; 146 147 spi: spi@1f000000 { 148 compatible = "qca,ar9132-spi", "qca,ar7100-spi"; 149 reg = <0x1f000000 0x10>; 150 151 clocks = <&pll ATH79_CLK_AHB>; 152 clock-names = "ahb"; 153 154 status = "disabled"; 155 156 #address-cells = <1>; 157 #size-cells = <0>; 158 }; 159 }; 160 161 usb_phy: usb-phy { 162 compatible = "qca,ar7100-usb-phy"; 163 164 reset-names = "phy", "suspend-override"; 165 resets = <&rst 4>, <&rst 3>; 166 167 #phy-cells = <0>; 168 169 status = "disabled"; 170 }; 171}; 172