1/dts-v1/; 2 3/memreserve/ 0x00000000 0x00001000; // reserved 4/memreserve/ 0x00001000 0x000ef000; // ROM data 5/memreserve/ 0x000f0000 0x004cc000; // reserved 6 7#include <dt-bindings/interrupt-controller/mips-gic.h> 8 9/ { 10 #address-cells = <1>; 11 #size-cells = <1>; 12 compatible = "mti,sead-3"; 13 interrupt-parent = <&gic>; 14 15 chosen { 16 stdout-path = "uart1:115200"; 17 }; 18 19 aliases { 20 uart0 = &uart0; 21 uart1 = &uart1; 22 }; 23 24 cpus { 25 cpu@0 { 26 compatible = "mti,mips14KEc", "mti,mips14Kc"; 27 }; 28 }; 29 30 memory { 31 device_type = "memory"; 32 reg = <0x0 0x08000000>; 33 }; 34 35 cpu_intc: interrupt-controller { 36 compatible = "mti,cpu-interrupt-controller"; 37 38 interrupt-controller; 39 #interrupt-cells = <1>; 40 }; 41 42 gic: interrupt-controller@1b1c0000 { 43 compatible = "mti,gic"; 44 reg = <0x1b1c0000 0x20000>; 45 46 interrupt-controller; 47 #interrupt-cells = <3>; 48 49 /* 50 * Declare the interrupt-parent even though the mti,gic 51 * binding doesn't require it, such that the kernel can 52 * figure out that cpu_intc is the root interrupt 53 * controller & should be probed first. 54 */ 55 interrupt-parent = <&cpu_intc>; 56 57 timer { 58 compatible = "mti,gic-timer"; 59 interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>; 60 }; 61 }; 62 63 /* UART connected to FTDI & miniUSB socket */ 64 uart0: uart@1f000900 { 65 compatible = "ns16550a"; 66 reg = <0x1f000900 0x20>; 67 reg-io-width = <4>; 68 reg-shift = <2>; 69 70 clock-frequency = <14745600>; 71 72 interrupts = <3>; /* GIC 3 or CPU 4 */ 73 74 no-loopback-test; 75 }; 76 77 /* UART connected to RS232 socket */ 78 uart1: uart@1f000800 { 79 compatible = "ns16550a"; 80 reg = <0x1f000800 0x20>; 81 reg-io-width = <4>; 82 reg-shift = <2>; 83 84 clock-frequency = <14745600>; 85 86 interrupts = <2>; /* GIC 2 or CPU 4 */ 87 88 no-loopback-test; 89 }; 90}; 91