1/dts-v1/; 2 3/memreserve/ 0x00000000 0x00001000; // reserved 4/memreserve/ 0x00001000 0x000ef000; // ROM data 5/memreserve/ 0x000f0000 0x004cc000; // reserved 6 7#include <dt-bindings/interrupt-controller/mips-gic.h> 8 9/ { 10 #address-cells = <1>; 11 #size-cells = <1>; 12 compatible = "mti,sead-3"; 13 interrupt-parent = <&gic>; 14 15 cpus { 16 cpu@0 { 17 compatible = "mti,mips14KEc", "mti,mips14Kc"; 18 }; 19 }; 20 21 memory { 22 device_type = "memory"; 23 reg = <0x0 0x08000000>; 24 }; 25 26 cpu_intc: interrupt-controller { 27 compatible = "mti,cpu-interrupt-controller"; 28 29 interrupt-controller; 30 #interrupt-cells = <1>; 31 }; 32 33 gic: interrupt-controller@1b1c0000 { 34 compatible = "mti,gic"; 35 reg = <0x1b1c0000 0x20000>; 36 37 interrupt-controller; 38 #interrupt-cells = <3>; 39 40 /* 41 * Declare the interrupt-parent even though the mti,gic 42 * binding doesn't require it, such that the kernel can 43 * figure out that cpu_intc is the root interrupt 44 * controller & should be probed first. 45 */ 46 interrupt-parent = <&cpu_intc>; 47 48 timer { 49 compatible = "mti,gic-timer"; 50 interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>; 51 }; 52 }; 53}; 54