xref: /openbmc/linux/arch/mips/boot/dts/mscc/ocelot.dtsi (revision bdeeed09)
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/* Copyright (c) 2017 Microsemi Corporation */
3
4/ {
5	#address-cells = <1>;
6	#size-cells = <1>;
7	compatible = "mscc,ocelot";
8
9	cpus {
10		#address-cells = <1>;
11		#size-cells = <0>;
12
13		cpu@0 {
14			compatible = "mips,mips24KEc";
15			device_type = "cpu";
16			clocks = <&cpu_clk>;
17			reg = <0>;
18		};
19	};
20
21	aliases {
22		serial0 = &uart0;
23	};
24
25	cpuintc: interrupt-controller {
26		#address-cells = <0>;
27		#interrupt-cells = <1>;
28		interrupt-controller;
29		compatible = "mti,cpu-interrupt-controller";
30	};
31
32	cpu_clk: cpu-clock {
33		compatible = "fixed-clock";
34		#clock-cells = <0>;
35		clock-frequency = <500000000>;
36	};
37
38	ahb_clk: ahb-clk {
39		compatible = "fixed-factor-clock";
40		#clock-cells = <0>;
41		clocks = <&cpu_clk>;
42		clock-div = <2>;
43		clock-mult = <1>;
44	};
45
46	ahb@70000000 {
47		compatible = "simple-bus";
48		#address-cells = <1>;
49		#size-cells = <1>;
50		ranges = <0 0x70000000 0x2000000>;
51
52		interrupt-parent = <&intc>;
53
54		cpu_ctrl: syscon@0 {
55			compatible = "mscc,ocelot-cpu-syscon", "syscon";
56			reg = <0x0 0x2c>;
57		};
58
59		intc: interrupt-controller@70 {
60			compatible = "mscc,ocelot-icpu-intr";
61			reg = <0x70 0x70>;
62			#interrupt-cells = <1>;
63			interrupt-controller;
64			interrupt-parent = <&cpuintc>;
65			interrupts = <2>;
66		};
67
68		uart0: serial@100000 {
69			pinctrl-0 = <&uart_pins>;
70			pinctrl-names = "default";
71			compatible = "ns16550a";
72			reg = <0x100000 0x20>;
73			interrupts = <6>;
74			clocks = <&ahb_clk>;
75			reg-io-width = <4>;
76			reg-shift = <2>;
77
78			status = "disabled";
79		};
80
81		uart2: serial@100800 {
82			pinctrl-0 = <&uart2_pins>;
83			pinctrl-names = "default";
84			compatible = "ns16550a";
85			reg = <0x100800 0x20>;
86			interrupts = <7>;
87			clocks = <&ahb_clk>;
88			reg-io-width = <4>;
89			reg-shift = <2>;
90
91			status = "disabled";
92		};
93
94		reset@1070008 {
95			compatible = "mscc,ocelot-chip-reset";
96			reg = <0x1070008 0x4>;
97		};
98
99		gpio: pinctrl@1070034 {
100			compatible = "mscc,ocelot-pinctrl";
101			reg = <0x1070034 0x68>;
102			gpio-controller;
103			#gpio-cells = <2>;
104			gpio-ranges = <&gpio 0 0 22>;
105
106			uart_pins: uart-pins {
107				pins = "GPIO_6", "GPIO_7";
108				function = "uart";
109			};
110
111			uart2_pins: uart2-pins {
112				pins = "GPIO_12", "GPIO_13";
113				function = "uart2";
114			};
115		};
116	};
117};
118