xref: /openbmc/linux/arch/mips/boot/dts/mscc/ocelot.dtsi (revision 9726bfcd) 
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/* Copyright (c) 2017 Microsemi Corporation */
3
4/ {
5	#address-cells = <1>;
6	#size-cells = <1>;
7	compatible = "mscc,ocelot";
8
9	cpus {
10		#address-cells = <1>;
11		#size-cells = <0>;
12
13		cpu@0 {
14			compatible = "mips,mips24KEc";
15			device_type = "cpu";
16			clocks = <&cpu_clk>;
17			reg = <0>;
18		};
19	};
20
21	aliases {
22		serial0 = &uart0;
23	};
24
25	cpuintc: interrupt-controller {
26		#address-cells = <0>;
27		#interrupt-cells = <1>;
28		interrupt-controller;
29		compatible = "mti,cpu-interrupt-controller";
30	};
31
32	cpu_clk: cpu-clock {
33		compatible = "fixed-clock";
34		#clock-cells = <0>;
35		clock-frequency = <500000000>;
36	};
37
38	ahb_clk: ahb-clk {
39		compatible = "fixed-factor-clock";
40		#clock-cells = <0>;
41		clocks = <&cpu_clk>;
42		clock-div = <2>;
43		clock-mult = <1>;
44	};
45
46	ahb@70000000 {
47		compatible = "simple-bus";
48		#address-cells = <1>;
49		#size-cells = <1>;
50		ranges = <0 0x70000000 0x2000000>;
51
52		interrupt-parent = <&intc>;
53
54		cpu_ctrl: syscon@0 {
55			compatible = "mscc,ocelot-cpu-syscon", "syscon";
56			reg = <0x0 0x2c>;
57		};
58
59		intc: interrupt-controller@70 {
60			compatible = "mscc,ocelot-icpu-intr";
61			reg = <0x70 0x70>;
62			#interrupt-cells = <1>;
63			interrupt-controller;
64			interrupt-parent = <&cpuintc>;
65			interrupts = <2>;
66		};
67
68		uart0: serial@100000 {
69			pinctrl-0 = <&uart_pins>;
70			pinctrl-names = "default";
71			compatible = "ns16550a";
72			reg = <0x100000 0x20>;
73			interrupts = <6>;
74			clocks = <&ahb_clk>;
75			reg-io-width = <4>;
76			reg-shift = <2>;
77
78			status = "disabled";
79		};
80
81		i2c: i2c@100400 {
82			compatible = "mscc,ocelot-i2c", "snps,designware-i2c";
83			pinctrl-0 = <&i2c_pins>;
84			pinctrl-names = "default";
85			reg = <0x100400 0x100>, <0x198 0x8>;
86			#address-cells = <1>;
87			#size-cells = <0>;
88			interrupts = <8>;
89			clocks = <&ahb_clk>;
90
91			status = "disabled";
92		};
93
94		uart2: serial@100800 {
95			pinctrl-0 = <&uart2_pins>;
96			pinctrl-names = "default";
97			compatible = "ns16550a";
98			reg = <0x100800 0x20>;
99			interrupts = <7>;
100			clocks = <&ahb_clk>;
101			reg-io-width = <4>;
102			reg-shift = <2>;
103
104			status = "disabled";
105		};
106
107		spi: spi@101000 {
108			compatible = "mscc,ocelot-spi", "snps,dw-apb-ssi";
109			#address-cells = <1>;
110			#size-cells = <0>;
111			reg = <0x101000 0x100>, <0x3c 0x18>;
112			interrupts = <9>;
113			clocks = <&ahb_clk>;
114
115			status = "disabled";
116		};
117
118		switch@1010000 {
119			compatible = "mscc,vsc7514-switch";
120			reg = <0x1010000 0x10000>,
121			      <0x1030000 0x10000>,
122			      <0x1080000 0x100>,
123			      <0x11e0000 0x100>,
124			      <0x11f0000 0x100>,
125			      <0x1200000 0x100>,
126			      <0x1210000 0x100>,
127			      <0x1220000 0x100>,
128			      <0x1230000 0x100>,
129			      <0x1240000 0x100>,
130			      <0x1250000 0x100>,
131			      <0x1260000 0x100>,
132			      <0x1270000 0x100>,
133			      <0x1280000 0x100>,
134			      <0x1800000 0x80000>,
135			      <0x1880000 0x10000>,
136			      <0x1060000 0x10000>;
137			reg-names = "sys", "rew", "qs", "port0", "port1",
138				    "port2", "port3", "port4", "port5", "port6",
139				    "port7", "port8", "port9", "port10", "qsys",
140				    "ana", "s2";
141			interrupts = <21 22>;
142			interrupt-names = "xtr", "inj";
143
144			ethernet-ports {
145				#address-cells = <1>;
146				#size-cells = <0>;
147
148				port0: port@0 {
149					reg = <0>;
150				};
151				port1: port@1 {
152					reg = <1>;
153				};
154				port2: port@2 {
155					reg = <2>;
156				};
157				port3: port@3 {
158					reg = <3>;
159				};
160				port4: port@4 {
161					reg = <4>;
162				};
163				port5: port@5 {
164					reg = <5>;
165				};
166				port6: port@6 {
167					reg = <6>;
168				};
169				port7: port@7 {
170					reg = <7>;
171				};
172				port8: port@8 {
173					reg = <8>;
174				};
175				port9: port@9 {
176					reg = <9>;
177				};
178				port10: port@10 {
179					reg = <10>;
180				};
181			};
182		};
183
184		reset@1070008 {
185			compatible = "mscc,ocelot-chip-reset";
186			reg = <0x1070008 0x4>;
187		};
188
189		gpio: pinctrl@1070034 {
190			compatible = "mscc,ocelot-pinctrl";
191			reg = <0x1070034 0x68>;
192			gpio-controller;
193			#gpio-cells = <2>;
194			gpio-ranges = <&gpio 0 0 22>;
195			interrupt-controller;
196			interrupts = <13>;
197			#interrupt-cells = <2>;
198
199			i2c_pins: i2c-pins {
200				pins = "GPIO_16", "GPIO_17";
201				function = "twi";
202			};
203
204			uart_pins: uart-pins {
205				pins = "GPIO_6", "GPIO_7";
206				function = "uart";
207			};
208
209			uart2_pins: uart2-pins {
210				pins = "GPIO_12", "GPIO_13";
211				function = "uart2";
212			};
213
214			miim1: miim1 {
215				pins = "GPIO_14", "GPIO_15";
216				function = "miim1";
217			};
218
219		};
220
221		mdio0: mdio@107009c {
222			#address-cells = <1>;
223			#size-cells = <0>;
224			compatible = "mscc,ocelot-miim";
225			reg = <0x107009c 0x24>, <0x10700f0 0x8>;
226			interrupts = <14>;
227			status = "disabled";
228
229			phy0: ethernet-phy@0 {
230				reg = <0>;
231			};
232			phy1: ethernet-phy@1 {
233				reg = <1>;
234			};
235			phy2: ethernet-phy@2 {
236				reg = <2>;
237			};
238			phy3: ethernet-phy@3 {
239				reg = <3>;
240			};
241		};
242
243		mdio1: mdio@10700c0 {
244			#address-cells = <1>;
245			#size-cells = <0>;
246			compatible = "mscc,ocelot-miim";
247			reg = <0x10700c0 0x24>;
248			interrupts = <15>;
249			pinctrl-names = "default";
250			pinctrl-0 = <&miim1>;
251			status = "disabled";
252		};
253
254		hsio: syscon@10d0000 {
255			compatible = "mscc,ocelot-hsio", "syscon", "simple-mfd";
256			reg = <0x10d0000 0x10000>;
257
258			serdes: serdes {
259				compatible = "mscc,vsc7514-serdes";
260				#phy-cells = <2>;
261			};
262		};
263	};
264};
265