xref: /openbmc/linux/arch/mips/boot/dts/mscc/ocelot.dtsi (revision 5d331b7f) 
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/* Copyright (c) 2017 Microsemi Corporation */
3
4/ {
5	#address-cells = <1>;
6	#size-cells = <1>;
7	compatible = "mscc,ocelot";
8
9	cpus {
10		#address-cells = <1>;
11		#size-cells = <0>;
12
13		cpu@0 {
14			compatible = "mips,mips24KEc";
15			device_type = "cpu";
16			clocks = <&cpu_clk>;
17			reg = <0>;
18		};
19	};
20
21	aliases {
22		serial0 = &uart0;
23	};
24
25	cpuintc: interrupt-controller {
26		#address-cells = <0>;
27		#interrupt-cells = <1>;
28		interrupt-controller;
29		compatible = "mti,cpu-interrupt-controller";
30	};
31
32	cpu_clk: cpu-clock {
33		compatible = "fixed-clock";
34		#clock-cells = <0>;
35		clock-frequency = <500000000>;
36	};
37
38	ahb_clk: ahb-clk {
39		compatible = "fixed-factor-clock";
40		#clock-cells = <0>;
41		clocks = <&cpu_clk>;
42		clock-div = <2>;
43		clock-mult = <1>;
44	};
45
46	ahb@70000000 {
47		compatible = "simple-bus";
48		#address-cells = <1>;
49		#size-cells = <1>;
50		ranges = <0 0x70000000 0x2000000>;
51
52		interrupt-parent = <&intc>;
53
54		cpu_ctrl: syscon@0 {
55			compatible = "mscc,ocelot-cpu-syscon", "syscon";
56			reg = <0x0 0x2c>;
57		};
58
59		intc: interrupt-controller@70 {
60			compatible = "mscc,ocelot-icpu-intr";
61			reg = <0x70 0x70>;
62			#interrupt-cells = <1>;
63			interrupt-controller;
64			interrupt-parent = <&cpuintc>;
65			interrupts = <2>;
66		};
67
68		uart0: serial@100000 {
69			pinctrl-0 = <&uart_pins>;
70			pinctrl-names = "default";
71			compatible = "ns16550a";
72			reg = <0x100000 0x20>;
73			interrupts = <6>;
74			clocks = <&ahb_clk>;
75			reg-io-width = <4>;
76			reg-shift = <2>;
77
78			status = "disabled";
79		};
80
81		i2c: i2c@100400 {
82			compatible = "mscc,ocelot-i2c", "snps,designware-i2c";
83			pinctrl-0 = <&i2c_pins>;
84			pinctrl-names = "default";
85			reg = <0x100400 0x100>, <0x198 0x8>;
86			#address-cells = <1>;
87			#size-cells = <0>;
88			interrupts = <8>;
89			clocks = <&ahb_clk>;
90
91			status = "disabled";
92		};
93
94		uart2: serial@100800 {
95			pinctrl-0 = <&uart2_pins>;
96			pinctrl-names = "default";
97			compatible = "ns16550a";
98			reg = <0x100800 0x20>;
99			interrupts = <7>;
100			clocks = <&ahb_clk>;
101			reg-io-width = <4>;
102			reg-shift = <2>;
103
104			status = "disabled";
105		};
106
107		spi: spi@101000 {
108			compatible = "mscc,ocelot-spi", "snps,dw-apb-ssi";
109			#address-cells = <1>;
110			#size-cells = <0>;
111			reg = <0x101000 0x100>, <0x3c 0x18>;
112			interrupts = <9>;
113			clocks = <&ahb_clk>;
114
115			status = "disabled";
116		};
117
118		switch@1010000 {
119			compatible = "mscc,vsc7514-switch";
120			reg = <0x1010000 0x10000>,
121			      <0x1030000 0x10000>,
122			      <0x1080000 0x100>,
123			      <0x11e0000 0x100>,
124			      <0x11f0000 0x100>,
125			      <0x1200000 0x100>,
126			      <0x1210000 0x100>,
127			      <0x1220000 0x100>,
128			      <0x1230000 0x100>,
129			      <0x1240000 0x100>,
130			      <0x1250000 0x100>,
131			      <0x1260000 0x100>,
132			      <0x1270000 0x100>,
133			      <0x1280000 0x100>,
134			      <0x1800000 0x80000>,
135			      <0x1880000 0x10000>;
136			reg-names = "sys", "rew", "qs", "port0", "port1",
137				    "port2", "port3", "port4", "port5", "port6",
138				    "port7", "port8", "port9", "port10", "qsys",
139				    "ana";
140			interrupts = <21 22>;
141			interrupt-names = "xtr", "inj";
142
143			ethernet-ports {
144				#address-cells = <1>;
145				#size-cells = <0>;
146
147				port0: port@0 {
148					reg = <0>;
149				};
150				port1: port@1 {
151					reg = <1>;
152				};
153				port2: port@2 {
154					reg = <2>;
155				};
156				port3: port@3 {
157					reg = <3>;
158				};
159				port4: port@4 {
160					reg = <4>;
161				};
162				port5: port@5 {
163					reg = <5>;
164				};
165				port6: port@6 {
166					reg = <6>;
167				};
168				port7: port@7 {
169					reg = <7>;
170				};
171				port8: port@8 {
172					reg = <8>;
173				};
174				port9: port@9 {
175					reg = <9>;
176				};
177				port10: port@10 {
178					reg = <10>;
179				};
180			};
181		};
182
183		reset@1070008 {
184			compatible = "mscc,ocelot-chip-reset";
185			reg = <0x1070008 0x4>;
186		};
187
188		gpio: pinctrl@1070034 {
189			compatible = "mscc,ocelot-pinctrl";
190			reg = <0x1070034 0x68>;
191			gpio-controller;
192			#gpio-cells = <2>;
193			gpio-ranges = <&gpio 0 0 22>;
194			interrupt-controller;
195			interrupts = <13>;
196			#interrupt-cells = <2>;
197
198			i2c_pins: i2c-pins {
199				pins = "GPIO_16", "GPIO_17";
200				function = "twi";
201			};
202
203			uart_pins: uart-pins {
204				pins = "GPIO_6", "GPIO_7";
205				function = "uart";
206			};
207
208			uart2_pins: uart2-pins {
209				pins = "GPIO_12", "GPIO_13";
210				function = "uart2";
211			};
212
213			miim1: miim1 {
214				pins = "GPIO_14", "GPIO_15";
215				function = "miim1";
216			};
217
218		};
219
220		mdio0: mdio@107009c {
221			#address-cells = <1>;
222			#size-cells = <0>;
223			compatible = "mscc,ocelot-miim";
224			reg = <0x107009c 0x24>, <0x10700f0 0x8>;
225			interrupts = <14>;
226			status = "disabled";
227
228			phy0: ethernet-phy@0 {
229				reg = <0>;
230			};
231			phy1: ethernet-phy@1 {
232				reg = <1>;
233			};
234			phy2: ethernet-phy@2 {
235				reg = <2>;
236			};
237			phy3: ethernet-phy@3 {
238				reg = <3>;
239			};
240		};
241
242		mdio1: mdio@10700c0 {
243			#address-cells = <1>;
244			#size-cells = <0>;
245			compatible = "mscc,ocelot-miim";
246			reg = <0x10700c0 0x24>;
247			interrupts = <15>;
248			pinctrl-names = "default";
249			pinctrl-0 = <&miim1>;
250			status = "disabled";
251		};
252
253		hsio: syscon@10d0000 {
254			compatible = "mscc,ocelot-hsio", "syscon", "simple-mfd";
255			reg = <0x10d0000 0x10000>;
256
257			serdes: serdes {
258				compatible = "mscc,vsc7514-serdes";
259				#phy-cells = <2>;
260			};
261		};
262	};
263};
264