xref: /openbmc/linux/arch/mips/boot/dts/mscc/ocelot.dtsi (revision 217188d9) 
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/* Copyright (c) 2017 Microsemi Corporation */
3
4/ {
5	#address-cells = <1>;
6	#size-cells = <1>;
7	compatible = "mscc,ocelot";
8
9	cpus {
10		#address-cells = <1>;
11		#size-cells = <0>;
12
13		cpu@0 {
14			compatible = "mips,mips24KEc";
15			device_type = "cpu";
16			clocks = <&cpu_clk>;
17			reg = <0>;
18		};
19	};
20
21	aliases {
22		serial0 = &uart0;
23	};
24
25	cpuintc: interrupt-controller {
26		#address-cells = <0>;
27		#interrupt-cells = <1>;
28		interrupt-controller;
29		compatible = "mti,cpu-interrupt-controller";
30	};
31
32	cpu_clk: cpu-clock {
33		compatible = "fixed-clock";
34		#clock-cells = <0>;
35		clock-frequency = <500000000>;
36	};
37
38	ahb_clk: ahb-clk {
39		compatible = "fixed-factor-clock";
40		#clock-cells = <0>;
41		clocks = <&cpu_clk>;
42		clock-div = <2>;
43		clock-mult = <1>;
44	};
45
46	ahb@70000000 {
47		compatible = "simple-bus";
48		#address-cells = <1>;
49		#size-cells = <1>;
50		ranges = <0 0x70000000 0x2000000>;
51
52		interrupt-parent = <&intc>;
53
54		cpu_ctrl: syscon@0 {
55			compatible = "mscc,ocelot-cpu-syscon", "syscon";
56			reg = <0x0 0x2c>;
57		};
58
59		intc: interrupt-controller@70 {
60			compatible = "mscc,ocelot-icpu-intr";
61			reg = <0x70 0x70>;
62			#interrupt-cells = <1>;
63			interrupt-controller;
64			interrupt-parent = <&cpuintc>;
65			interrupts = <2>;
66		};
67
68		uart0: serial@100000 {
69			pinctrl-0 = <&uart_pins>;
70			pinctrl-names = "default";
71			compatible = "ns16550a";
72			reg = <0x100000 0x20>;
73			interrupts = <6>;
74			clocks = <&ahb_clk>;
75			reg-io-width = <4>;
76			reg-shift = <2>;
77
78			status = "disabled";
79		};
80
81		uart2: serial@100800 {
82			pinctrl-0 = <&uart2_pins>;
83			pinctrl-names = "default";
84			compatible = "ns16550a";
85			reg = <0x100800 0x20>;
86			interrupts = <7>;
87			clocks = <&ahb_clk>;
88			reg-io-width = <4>;
89			reg-shift = <2>;
90
91			status = "disabled";
92		};
93
94		spi: spi@101000 {
95			compatible = "mscc,ocelot-spi", "snps,dw-apb-ssi";
96			#address-cells = <1>;
97			#size-cells = <0>;
98			reg = <0x101000 0x100>, <0x3c 0x18>;
99			interrupts = <9>;
100			clocks = <&ahb_clk>;
101
102			status = "disabled";
103		};
104
105		switch@1010000 {
106			compatible = "mscc,vsc7514-switch";
107			reg = <0x1010000 0x10000>,
108			      <0x1030000 0x10000>,
109			      <0x1080000 0x100>,
110			      <0x10d0000 0x10000>,
111			      <0x11e0000 0x100>,
112			      <0x11f0000 0x100>,
113			      <0x1200000 0x100>,
114			      <0x1210000 0x100>,
115			      <0x1220000 0x100>,
116			      <0x1230000 0x100>,
117			      <0x1240000 0x100>,
118			      <0x1250000 0x100>,
119			      <0x1260000 0x100>,
120			      <0x1270000 0x100>,
121			      <0x1280000 0x100>,
122			      <0x1800000 0x80000>,
123			      <0x1880000 0x10000>;
124			reg-names = "sys", "rew", "qs", "hsio", "port0",
125				    "port1", "port2", "port3", "port4", "port5",
126				    "port6", "port7", "port8", "port9", "port10",
127				    "qsys", "ana";
128			interrupts = <21 22>;
129			interrupt-names = "xtr", "inj";
130
131			ethernet-ports {
132				#address-cells = <1>;
133				#size-cells = <0>;
134
135				port0: port@0 {
136					reg = <0>;
137				};
138				port1: port@1 {
139					reg = <1>;
140				};
141				port2: port@2 {
142					reg = <2>;
143				};
144				port3: port@3 {
145					reg = <3>;
146				};
147				port4: port@4 {
148					reg = <4>;
149				};
150				port5: port@5 {
151					reg = <5>;
152				};
153				port6: port@6 {
154					reg = <6>;
155				};
156				port7: port@7 {
157					reg = <7>;
158				};
159				port8: port@8 {
160					reg = <8>;
161				};
162				port9: port@9 {
163					reg = <9>;
164				};
165				port10: port@10 {
166					reg = <10>;
167				};
168			};
169		};
170
171		reset@1070008 {
172			compatible = "mscc,ocelot-chip-reset";
173			reg = <0x1070008 0x4>;
174		};
175
176		gpio: pinctrl@1070034 {
177			compatible = "mscc,ocelot-pinctrl";
178			reg = <0x1070034 0x68>;
179			gpio-controller;
180			#gpio-cells = <2>;
181			gpio-ranges = <&gpio 0 0 22>;
182			interrupt-controller;
183			interrupts = <13>;
184			#interrupt-cells = <2>;
185
186			uart_pins: uart-pins {
187				pins = "GPIO_6", "GPIO_7";
188				function = "uart";
189			};
190
191			uart2_pins: uart2-pins {
192				pins = "GPIO_12", "GPIO_13";
193				function = "uart2";
194			};
195
196			miim1: miim1 {
197				pins = "GPIO_14", "GPIO_15";
198				function = "miim1";
199			};
200		};
201
202		mdio0: mdio@107009c {
203			#address-cells = <1>;
204			#size-cells = <0>;
205			compatible = "mscc,ocelot-miim";
206			reg = <0x107009c 0x24>, <0x10700f0 0x8>;
207			interrupts = <14>;
208			status = "disabled";
209
210			phy0: ethernet-phy@0 {
211				reg = <0>;
212			};
213			phy1: ethernet-phy@1 {
214				reg = <1>;
215			};
216			phy2: ethernet-phy@2 {
217				reg = <2>;
218			};
219			phy3: ethernet-phy@3 {
220				reg = <3>;
221			};
222		};
223
224		mdio1: mdio@10700c0 {
225			#address-cells = <1>;
226			#size-cells = <0>;
227			compatible = "mscc,ocelot-miim";
228			reg = <0x10700c0 0x24>;
229			interrupts = <15>;
230			pinctrl-names = "default";
231			pinctrl-0 = <&miim1>;
232			status = "disabled";
233		};
234	};
235};
236