xref: /openbmc/linux/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi (revision 690d62d1ebb9233019e33ed307a719826652a04b) 
1// SPDX-License-Identifier: GPL-2.0
2
3/dts-v1/;
4
5#include <dt-bindings/interrupt-controller/irq.h>
6
7/ {
8	compatible = "loongson,loongson2k1000";
9
10	#address-cells = <2>;
11	#size-cells = <2>;
12
13	cpus {
14		#address-cells = <1>;
15		#size-cells = <0>;
16
17		cpu0: cpu@0 {
18			device_type = "cpu";
19			compatible = "loongson,gs264";
20			reg = <0x0>;
21			#clock-cells = <1>;
22			clocks = <&cpu_clk>;
23		};
24	};
25
26	cpu_clk: cpu_clk {
27		#clock-cells = <0>;
28		compatible = "fixed-clock";
29		clock-frequency = <800000000>;
30	};
31
32	cpuintc: interrupt-controller {
33		#address-cells = <0>;
34		#interrupt-cells = <1>;
35		interrupt-controller;
36		compatible = "mti,cpu-interrupt-controller";
37	};
38
39	package0: bus@10000000 {
40		compatible = "simple-bus";
41		#address-cells = <2>;
42		#size-cells = <2>;
43		ranges = <0 0x10000000 0 0x10000000 0 0x10000000 /* ioports */
44			0 0x40000000 0 0x40000000 0 0x40000000
45			0xfe 0x00000000 0xfe 0x00000000 0 0x40000000>;
46
47		isa@18000000 {
48			compatible = "isa";
49			#size-cells = <1>;
50			#address-cells = <2>;
51			ranges = <1 0x0 0x0 0x18000000 0x4000>;
52		};
53
54		pm: reset-controller@1fe07000 {
55			compatible = "loongson,ls2k-pm";
56			reg = <0 0x1fe07000 0 0x422>;
57		};
58
59		liointc0: interrupt-controller@1fe11400 {
60			compatible = "loongson,liointc-2.0";
61			reg = <0 0x1fe11400 0 0x40>,
62				<0 0x1fe11040 0 0x8>,
63				<0 0x1fe11140 0 0x8>;
64			reg-names = "main", "isr0", "isr1";
65
66			interrupt-controller;
67			#interrupt-cells = <2>;
68
69			interrupt-parent = <&cpuintc>;
70			interrupts = <2>;
71			interrupt-names = "int0";
72
73			loongson,parent_int_map = <0xffffffff>, /* int0 */
74						<0x00000000>, /* int1 */
75						<0x00000000>, /* int2 */
76						<0x00000000>; /* int3 */
77		};
78
79		liointc1: interrupt-controller@1fe11440 {
80			compatible = "loongson,liointc-2.0";
81			reg = <0 0x1fe11440 0 0x40>,
82				<0 0x1fe11048 0 0x8>,
83				<0 0x1fe11148 0 0x8>;
84			reg-names = "main", "isr0", "isr1";
85
86			interrupt-controller;
87			#interrupt-cells = <2>;
88
89			interrupt-parent = <&cpuintc>;
90			interrupts = <3>;
91			interrupt-names = "int1";
92
93			loongson,parent_int_map = <0x00000000>, /* int0 */
94						<0xffffffff>, /* int1 */
95						<0x00000000>, /* int2 */
96						<0x00000000>; /* int3 */
97		};
98
99		rtc0: rtc@1fe07800 {
100			compatible = "loongson,ls2k1000-rtc";
101			reg = <0 0x1fe07800 0 0x78>;
102			interrupt-parent = <&liointc0>;
103			interrupts = <60 IRQ_TYPE_LEVEL_LOW>;
104		};
105
106		uart0: serial@1fe00000 {
107			compatible = "ns16550a";
108			reg = <0 0x1fe00000 0 0x8>;
109			clock-frequency = <125000000>;
110			interrupt-parent = <&liointc0>;
111			interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
112			no-loopback-test;
113		};
114
115		pci@1a000000 {
116			compatible = "loongson,ls2k-pci";
117			device_type = "pci";
118			#address-cells = <3>;
119			#size-cells = <2>;
120			#interrupt-cells = <2>;
121
122			reg = <0 0x1a000000 0 0x02000000>,
123				<0xfe 0x00000000 0 0x20000000>;
124
125			ranges = <0x01000000 0x0 0x00000000 0x0 0x18000000  0x0 0x00010000>,
126				 <0x02000000 0x0 0x40000000 0x0 0x40000000  0x0 0x40000000>;
127
128			gmac@3,0 {
129				compatible = "pci0014,7a03.0",
130						   "pci0014,7a03",
131						   "pciclass0c0320",
132						   "pciclass0c03";
133
134				reg = <0x1800 0x0 0x0 0x0 0x0>;
135				interrupts = <12 IRQ_TYPE_LEVEL_LOW>,
136					     <13 IRQ_TYPE_LEVEL_LOW>;
137				interrupt-names = "macirq", "eth_lpi";
138				interrupt-parent = <&liointc0>;
139				phy-mode = "rgmii-id";
140				phy-handle = <&phy1>;
141				mdio {
142					#address-cells = <1>;
143					#size-cells = <0>;
144					compatible = "snps,dwmac-mdio";
145					phy0: ethernet-phy@0 {
146						reg = <0>;
147					};
148				};
149			};
150
151			gmac@3,1 {
152				compatible = "pci0014,7a03.0",
153						   "pci0014,7a03",
154						   "pciclass0c0320",
155						   "pciclass0c03",
156						   "loongson, pci-gmac";
157
158				reg = <0x1900 0x0 0x0 0x0 0x0>;
159				interrupts = <14 IRQ_TYPE_LEVEL_LOW>,
160					     <15 IRQ_TYPE_LEVEL_LOW>;
161				interrupt-names = "macirq", "eth_lpi";
162				interrupt-parent = <&liointc0>;
163				phy-mode = "rgmii-id";
164				phy-handle = <&phy1>;
165				mdio {
166					#address-cells = <1>;
167					#size-cells = <0>;
168					compatible = "snps,dwmac-mdio";
169					phy1: ethernet-phy@1 {
170						reg = <0>;
171					};
172				};
173			};
174
175			ehci@4,1 {
176				compatible = "pci0014,7a14.0",
177						   "pci0014,7a14",
178						   "pciclass0c0320",
179						   "pciclass0c03";
180
181				reg = <0x2100 0x0 0x0 0x0 0x0>;
182				interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
183				interrupt-parent = <&liointc1>;
184			};
185
186			ohci@4,2 {
187				compatible = "pci0014,7a24.0",
188						   "pci0014,7a24",
189						   "pciclass0c0310",
190						   "pciclass0c03";
191
192				reg = <0x2200 0x0 0x0 0x0 0x0>;
193				interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
194				interrupt-parent = <&liointc1>;
195			};
196
197			sata@8,0 {
198				compatible = "pci0014,7a08.0",
199						   "pci0014,7a08",
200						   "pciclass010601",
201						   "pciclass0106";
202
203				reg = <0x4000 0x0 0x0 0x0 0x0>;
204				interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
205				interrupt-parent = <&liointc0>;
206			};
207
208			pci_bridge@9,0 {
209				compatible = "pci0014,7a19.0",
210						   "pci0014,7a19",
211						   "pciclass060400",
212						   "pciclass0604";
213
214				reg = <0x4800 0x0 0x0 0x0 0x0>;
215				#interrupt-cells = <1>;
216				interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
217				interrupt-parent = <&liointc1>;
218				interrupt-map-mask = <0 0 0 0>;
219				interrupt-map = <0 0 0 0 &liointc1 0 IRQ_TYPE_LEVEL_LOW>;
220				external-facing;
221			};
222
223			pci_bridge@a,0 {
224				compatible = "pci0014,7a09.0",
225						   "pci0014,7a09",
226						   "pciclass060400",
227						   "pciclass0604";
228
229				reg = <0x5000 0x0 0x0 0x0 0x0>;
230				#interrupt-cells = <1>;
231				interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
232				interrupt-parent = <&liointc1>;
233				interrupt-map-mask = <0 0 0 0>;
234				interrupt-map = <0 0 0 0 &liointc1 1 IRQ_TYPE_LEVEL_LOW>;
235				external-facing;
236			};
237
238			pci_bridge@b,0 {
239				compatible = "pci0014,7a09.0",
240						   "pci0014,7a09",
241						   "pciclass060400",
242						   "pciclass0604";
243
244				reg = <0x5800 0x0 0x0 0x0 0x0>;
245				#interrupt-cells = <1>;
246				interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
247				interrupt-parent = <&liointc1>;
248				interrupt-map-mask = <0 0 0 0>;
249				interrupt-map = <0 0 0 0 &liointc1 2 IRQ_TYPE_LEVEL_LOW>;
250				external-facing;
251			};
252
253			pci_bridge@c,0 {
254				compatible = "pci0014,7a09.0",
255						   "pci0014,7a09",
256						   "pciclass060400",
257						   "pciclass0604";
258
259				reg = <0x6000 0x0 0x0 0x0 0x0>;
260				#interrupt-cells = <1>;
261				interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
262				interrupt-parent = <&liointc1>;
263				interrupt-map-mask = <0 0 0 0>;
264				interrupt-map = <0 0 0 0 &liointc1 3 IRQ_TYPE_LEVEL_LOW>;
265				external-facing;
266			};
267
268			pci_bridge@d,0 {
269				compatible = "pci0014,7a19.0",
270						   "pci0014,7a19",
271						   "pciclass060400",
272						   "pciclass0604";
273
274				reg = <0x6800 0x0 0x0 0x0 0x0>;
275				#interrupt-cells = <1>;
276				interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
277				interrupt-parent = <&liointc1>;
278				interrupt-map-mask = <0 0 0 0>;
279				interrupt-map = <0 0 0 0 &liointc1 4 IRQ_TYPE_LEVEL_LOW>;
280				external-facing;
281			};
282
283			pci_bridge@e,0 {
284				compatible = "pci0014,7a09.0",
285						   "pci0014,7a09",
286						   "pciclass060400",
287						   "pciclass0604";
288
289				reg = <0x7000 0x0 0x0 0x0 0x0>;
290				#interrupt-cells = <1>;
291				interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
292				interrupt-parent = <&liointc1>;
293				interrupt-map-mask = <0 0 0 0>;
294				interrupt-map = <0 0 0 0 &liointc1 5 IRQ_TYPE_LEVEL_LOW>;
295				external-facing;
296			};
297
298		};
299	};
300};
301
302