1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/ingenic,tcu.h> 3#include <dt-bindings/clock/x1000-cgu.h> 4#include <dt-bindings/dma/x1000-dma.h> 5 6/ { 7 #address-cells = <1>; 8 #size-cells = <1>; 9 compatible = "ingenic,x1000", "ingenic,x1000e"; 10 11 cpuintc: interrupt-controller { 12 #address-cells = <0>; 13 #interrupt-cells = <1>; 14 interrupt-controller; 15 compatible = "mti,cpu-interrupt-controller"; 16 }; 17 18 intc: interrupt-controller@10001000 { 19 compatible = "ingenic,x1000-intc", "ingenic,jz4780-intc"; 20 reg = <0x10001000 0x50>; 21 22 interrupt-controller; 23 #interrupt-cells = <1>; 24 25 interrupt-parent = <&cpuintc>; 26 interrupts = <2>; 27 }; 28 29 exclk: ext { 30 compatible = "fixed-clock"; 31 #clock-cells = <0>; 32 }; 33 34 rtclk: rtc { 35 compatible = "fixed-clock"; 36 #clock-cells = <0>; 37 clock-frequency = <32768>; 38 }; 39 40 cgu: x1000-cgu@10000000 { 41 compatible = "ingenic,x1000-cgu"; 42 reg = <0x10000000 0x100>; 43 44 #clock-cells = <1>; 45 46 clocks = <&exclk>, <&rtclk>; 47 clock-names = "ext", "rtc"; 48 }; 49 50 tcu: timer@10002000 { 51 compatible = "ingenic,x1000-tcu", 52 "ingenic,jz4770-tcu", 53 "simple-mfd"; 54 reg = <0x10002000 0x1000>; 55 #address-cells = <1>; 56 #size-cells = <1>; 57 ranges = <0x0 0x10002000 0x1000>; 58 59 #clock-cells = <1>; 60 61 clocks = <&cgu X1000_CLK_RTCLK>, 62 <&cgu X1000_CLK_EXCLK>, 63 <&cgu X1000_CLK_PCLK>; 64 clock-names = "rtc", "ext", "pclk"; 65 66 interrupt-controller; 67 #interrupt-cells = <1>; 68 69 interrupt-parent = <&intc>; 70 interrupts = <27 26 25>; 71 72 wdt: watchdog@0 { 73 compatible = "ingenic,x1000-watchdog", "ingenic,jz4780-watchdog"; 74 reg = <0x0 0x10>; 75 76 clocks = <&tcu TCU_CLK_WDT>; 77 clock-names = "wdt"; 78 }; 79 }; 80 81 rtc: rtc@10003000 { 82 compatible = "ingenic,x1000-rtc", "ingenic,jz4780-rtc"; 83 reg = <0x10003000 0x4c>; 84 85 interrupt-parent = <&intc>; 86 interrupts = <32>; 87 88 clocks = <&cgu X1000_CLK_RTCLK>; 89 clock-names = "rtc"; 90 }; 91 92 pinctrl: pin-controller@10010000 { 93 compatible = "ingenic,x1000-pinctrl"; 94 reg = <0x10010000 0x800>; 95 #address-cells = <1>; 96 #size-cells = <0>; 97 98 gpa: gpio@0 { 99 compatible = "ingenic,x1000-gpio"; 100 reg = <0>; 101 102 gpio-controller; 103 gpio-ranges = <&pinctrl 0 0 32>; 104 #gpio-cells = <2>; 105 106 interrupt-controller; 107 #interrupt-cells = <2>; 108 109 interrupt-parent = <&intc>; 110 interrupts = <17>; 111 }; 112 113 gpb: gpio@1 { 114 compatible = "ingenic,x1000-gpio"; 115 reg = <1>; 116 117 gpio-controller; 118 gpio-ranges = <&pinctrl 0 32 32>; 119 #gpio-cells = <2>; 120 121 interrupt-controller; 122 #interrupt-cells = <2>; 123 124 interrupt-parent = <&intc>; 125 interrupts = <16>; 126 }; 127 128 gpc: gpio@2 { 129 compatible = "ingenic,x1000-gpio"; 130 reg = <2>; 131 132 gpio-controller; 133 gpio-ranges = <&pinctrl 0 64 32>; 134 #gpio-cells = <2>; 135 136 interrupt-controller; 137 #interrupt-cells = <2>; 138 139 interrupt-parent = <&intc>; 140 interrupts = <15>; 141 }; 142 143 gpd: gpio@3 { 144 compatible = "ingenic,x1000-gpio"; 145 reg = <3>; 146 147 gpio-controller; 148 gpio-ranges = <&pinctrl 0 96 32>; 149 #gpio-cells = <2>; 150 151 interrupt-controller; 152 #interrupt-cells = <2>; 153 154 interrupt-parent = <&intc>; 155 interrupts = <14>; 156 }; 157 }; 158 159 i2c0: i2c-controller@10050000 { 160 compatible = "ingenic,x1000-i2c"; 161 reg = <0x10050000 0x1000>; 162 #address-cells = <1>; 163 #size-cells = <0>; 164 165 interrupt-parent = <&intc>; 166 interrupts = <60>; 167 168 clocks = <&cgu X1000_CLK_I2C0>; 169 170 status = "disabled"; 171 }; 172 173 i2c1: i2c-controller@10051000 { 174 compatible = "ingenic,x1000-i2c"; 175 reg = <0x10051000 0x1000>; 176 #address-cells = <1>; 177 #size-cells = <0>; 178 179 interrupt-parent = <&intc>; 180 interrupts = <59>; 181 182 clocks = <&cgu X1000_CLK_I2C1>; 183 184 status = "disabled"; 185 }; 186 187 i2c2: i2c-controller@10052000 { 188 compatible = "ingenic,x1000-i2c"; 189 reg = <0x10052000 0x1000>; 190 #address-cells = <1>; 191 #size-cells = <0>; 192 193 interrupt-parent = <&intc>; 194 interrupts = <58>; 195 196 clocks = <&cgu X1000_CLK_I2C2>; 197 198 status = "disabled"; 199 }; 200 201 uart0: serial@10030000 { 202 compatible = "ingenic,x1000-uart"; 203 reg = <0x10030000 0x100>; 204 205 interrupt-parent = <&intc>; 206 interrupts = <51>; 207 208 clocks = <&exclk>, <&cgu X1000_CLK_UART0>; 209 clock-names = "baud", "module"; 210 211 status = "disabled"; 212 }; 213 214 uart1: serial@10031000 { 215 compatible = "ingenic,x1000-uart"; 216 reg = <0x10031000 0x100>; 217 218 interrupt-parent = <&intc>; 219 interrupts = <50>; 220 221 clocks = <&exclk>, <&cgu X1000_CLK_UART1>; 222 clock-names = "baud", "module"; 223 224 status = "disabled"; 225 }; 226 227 uart2: serial@10032000 { 228 compatible = "ingenic,x1000-uart"; 229 reg = <0x10032000 0x100>; 230 231 interrupt-parent = <&intc>; 232 interrupts = <49>; 233 234 clocks = <&exclk>, <&cgu X1000_CLK_UART2>; 235 clock-names = "baud", "module"; 236 237 status = "disabled"; 238 }; 239 240 pdma: dma-controller@13420000 { 241 compatible = "ingenic,x1000-dma"; 242 reg = <0x13420000 0x400>, <0x13421000 0x40>; 243 #dma-cells = <2>; 244 245 interrupt-parent = <&intc>; 246 interrupts = <10>; 247 248 clocks = <&cgu X1000_CLK_PDMA>; 249 }; 250 251 mac: ethernet@134b0000 { 252 compatible = "ingenic,x1000-mac", "snps,dwmac"; 253 reg = <0x134b0000 0x2000>; 254 255 interrupt-parent = <&intc>; 256 interrupts = <55>; 257 interrupt-names = "macirq"; 258 259 clocks = <&cgu X1000_CLK_MAC>; 260 clock-names = "stmmaceth"; 261 262 status = "disabled"; 263 264 mdio: mdio { 265 compatible = "snps,dwmac-mdio"; 266 #address-cells = <1>; 267 #size-cells = <0>; 268 269 status = "disabled"; 270 }; 271 }; 272 273 msc0: mmc@13450000 { 274 compatible = "ingenic,x1000-mmc"; 275 reg = <0x13450000 0x1000>; 276 277 interrupt-parent = <&intc>; 278 interrupts = <37>; 279 280 clocks = <&cgu X1000_CLK_MSC0>; 281 clock-names = "mmc"; 282 283 cap-sd-highspeed; 284 cap-mmc-highspeed; 285 cap-sdio-irq; 286 287 dmas = <&pdma X1000_DMA_MSC0_RX 0xffffffff>, 288 <&pdma X1000_DMA_MSC0_TX 0xffffffff>; 289 dma-names = "rx", "tx"; 290 291 status = "disabled"; 292 }; 293 294 msc1: mmc@13460000 { 295 compatible = "ingenic,x1000-mmc"; 296 reg = <0x13460000 0x1000>; 297 298 interrupt-parent = <&intc>; 299 interrupts = <36>; 300 301 clocks = <&cgu X1000_CLK_MSC1>; 302 clock-names = "mmc"; 303 304 cap-sd-highspeed; 305 cap-mmc-highspeed; 306 cap-sdio-irq; 307 308 dmas = <&pdma X1000_DMA_MSC1_RX 0xffffffff>, 309 <&pdma X1000_DMA_MSC1_TX 0xffffffff>; 310 dma-names = "rx", "tx"; 311 312 status = "disabled"; 313 }; 314}; 315