1// SPDX-License-Identifier: GPL-2.0
2#include <dt-bindings/clock/jz4780-cgu.h>
3#include <dt-bindings/dma/jz4780-dma.h>
4
5/ {
6	#address-cells = <1>;
7	#size-cells = <1>;
8	compatible = "ingenic,jz4780";
9
10	cpuintc: interrupt-controller {
11		#address-cells = <0>;
12		#interrupt-cells = <1>;
13		interrupt-controller;
14		compatible = "mti,cpu-interrupt-controller";
15	};
16
17	intc: interrupt-controller@10001000 {
18		compatible = "ingenic,jz4780-intc";
19		reg = <0x10001000 0x50>;
20
21		interrupt-controller;
22		#interrupt-cells = <1>;
23
24		interrupt-parent = <&cpuintc>;
25		interrupts = <2>;
26	};
27
28	ext: ext {
29		compatible = "fixed-clock";
30		#clock-cells = <0>;
31	};
32
33	rtc: rtc {
34		compatible = "fixed-clock";
35		#clock-cells = <0>;
36		clock-frequency = <32768>;
37	};
38
39	cgu: jz4780-cgu@10000000 {
40		compatible = "ingenic,jz4780-cgu";
41		reg = <0x10000000 0x100>;
42
43		clocks = <&ext>, <&rtc>;
44		clock-names = "ext", "rtc";
45
46		#clock-cells = <1>;
47	};
48
49	tcu: timer@10002000 {
50		compatible = "ingenic,jz4780-tcu",
51			     "ingenic,jz4770-tcu",
52			     "simple-mfd";
53		reg = <0x10002000 0x1000>;
54		#address-cells = <1>;
55		#size-cells = <1>;
56		ranges = <0x0 0x10002000 0x1000>;
57
58		#clock-cells = <1>;
59
60		clocks = <&cgu JZ4780_CLK_RTCLK
61			  &cgu JZ4780_CLK_EXCLK
62			  &cgu JZ4780_CLK_PCLK>;
63		clock-names = "rtc", "ext", "pclk";
64
65		interrupt-controller;
66		#interrupt-cells = <1>;
67
68		interrupt-parent = <&intc>;
69		interrupts = <27 26 25>;
70	};
71
72	rtc_dev: rtc@10003000 {
73		compatible = "ingenic,jz4780-rtc";
74		reg = <0x10003000 0x4c>;
75
76		interrupt-parent = <&intc>;
77		interrupts = <32>;
78
79		clocks = <&cgu JZ4780_CLK_RTCLK>;
80		clock-names = "rtc";
81	};
82
83	pinctrl: pin-controller@10010000 {
84		compatible = "ingenic,jz4780-pinctrl";
85		reg = <0x10010000 0x600>;
86
87		#address-cells = <1>;
88		#size-cells = <0>;
89
90		gpa: gpio@0 {
91			compatible = "ingenic,jz4780-gpio";
92			reg = <0>;
93
94			gpio-controller;
95			gpio-ranges = <&pinctrl 0 0 32>;
96			#gpio-cells = <2>;
97
98			interrupt-controller;
99			#interrupt-cells = <2>;
100
101			interrupt-parent = <&intc>;
102			interrupts = <17>;
103		};
104
105		gpb: gpio@1 {
106			compatible = "ingenic,jz4780-gpio";
107			reg = <1>;
108
109			gpio-controller;
110			gpio-ranges = <&pinctrl 0 32 32>;
111			#gpio-cells = <2>;
112
113			interrupt-controller;
114			#interrupt-cells = <2>;
115
116			interrupt-parent = <&intc>;
117			interrupts = <16>;
118		};
119
120		gpc: gpio@2 {
121			compatible = "ingenic,jz4780-gpio";
122			reg = <2>;
123
124			gpio-controller;
125			gpio-ranges = <&pinctrl 0 64 32>;
126			#gpio-cells = <2>;
127
128			interrupt-controller;
129			#interrupt-cells = <2>;
130
131			interrupt-parent = <&intc>;
132			interrupts = <15>;
133		};
134
135		gpd: gpio@3 {
136			compatible = "ingenic,jz4780-gpio";
137			reg = <3>;
138
139			gpio-controller;
140			gpio-ranges = <&pinctrl 0 96 32>;
141			#gpio-cells = <2>;
142
143			interrupt-controller;
144			#interrupt-cells = <2>;
145
146			interrupt-parent = <&intc>;
147			interrupts = <14>;
148		};
149
150		gpe: gpio@4 {
151			compatible = "ingenic,jz4780-gpio";
152			reg = <4>;
153
154			gpio-controller;
155			gpio-ranges = <&pinctrl 0 128 32>;
156			#gpio-cells = <2>;
157
158			interrupt-controller;
159			#interrupt-cells = <2>;
160
161			interrupt-parent = <&intc>;
162			interrupts = <13>;
163		};
164
165		gpf: gpio@5 {
166			compatible = "ingenic,jz4780-gpio";
167			reg = <5>;
168
169			gpio-controller;
170			gpio-ranges = <&pinctrl 0 160 32>;
171			#gpio-cells = <2>;
172
173			interrupt-controller;
174			#interrupt-cells = <2>;
175
176			interrupt-parent = <&intc>;
177			interrupts = <12>;
178		};
179	};
180
181	spi_gpio {
182		compatible = "spi-gpio";
183		#address-cells = <1>;
184		#size-cells = <0>;
185		num-chipselects = <2>;
186
187		gpio-miso = <&gpe 14 0>;
188		gpio-sck = <&gpe 15 0>;
189		gpio-mosi = <&gpe 17 0>;
190		cs-gpios = <&gpe 16 0
191			    &gpe 18 0>;
192
193		spidev@0 {
194			compatible = "spidev";
195			reg = <0>;
196			spi-max-frequency = <1000000>;
197		};
198	};
199
200	uart0: serial@10030000 {
201		compatible = "ingenic,jz4780-uart";
202		reg = <0x10030000 0x100>;
203
204		interrupt-parent = <&intc>;
205		interrupts = <51>;
206
207		clocks = <&ext>, <&cgu JZ4780_CLK_UART0>;
208		clock-names = "baud", "module";
209
210		status = "disabled";
211	};
212
213	uart1: serial@10031000 {
214		compatible = "ingenic,jz4780-uart";
215		reg = <0x10031000 0x100>;
216
217		interrupt-parent = <&intc>;
218		interrupts = <50>;
219
220		clocks = <&ext>, <&cgu JZ4780_CLK_UART1>;
221		clock-names = "baud", "module";
222
223		status = "disabled";
224	};
225
226	uart2: serial@10032000 {
227		compatible = "ingenic,jz4780-uart";
228		reg = <0x10032000 0x100>;
229
230		interrupt-parent = <&intc>;
231		interrupts = <49>;
232
233		clocks = <&ext>, <&cgu JZ4780_CLK_UART2>;
234		clock-names = "baud", "module";
235
236		status = "disabled";
237	};
238
239	uart3: serial@10033000 {
240		compatible = "ingenic,jz4780-uart";
241		reg = <0x10033000 0x100>;
242
243		interrupt-parent = <&intc>;
244		interrupts = <48>;
245
246		clocks = <&ext>, <&cgu JZ4780_CLK_UART3>;
247		clock-names = "baud", "module";
248
249		status = "disabled";
250	};
251
252	uart4: serial@10034000 {
253		compatible = "ingenic,jz4780-uart";
254		reg = <0x10034000 0x100>;
255
256		interrupt-parent = <&intc>;
257		interrupts = <34>;
258
259		clocks = <&ext>, <&cgu JZ4780_CLK_UART4>;
260		clock-names = "baud", "module";
261
262		status = "disabled";
263	};
264
265	watchdog: watchdog@10002000 {
266		compatible = "ingenic,jz4780-watchdog";
267		reg = <0x10002000 0x10>;
268
269		clocks = <&cgu JZ4780_CLK_RTCLK>;
270		clock-names = "rtc";
271	};
272
273	nemc: nemc@13410000 {
274		compatible = "ingenic,jz4780-nemc";
275		reg = <0x13410000 0x10000>;
276		#address-cells = <2>;
277		#size-cells = <1>;
278		ranges = <1 0 0x1b000000 0x1000000
279			  2 0 0x1a000000 0x1000000
280			  3 0 0x19000000 0x1000000
281			  4 0 0x18000000 0x1000000
282			  5 0 0x17000000 0x1000000
283			  6 0 0x16000000 0x1000000>;
284
285		clocks = <&cgu JZ4780_CLK_NEMC>;
286
287		status = "disabled";
288	};
289
290	dma: dma@13420000 {
291		compatible = "ingenic,jz4780-dma";
292		reg = <0x13420000 0x400
293		       0x13421000 0x40>;
294		#dma-cells = <2>;
295
296		interrupt-parent = <&intc>;
297		interrupts = <10>;
298
299		clocks = <&cgu JZ4780_CLK_PDMA>;
300	};
301
302	mmc0: mmc@13450000 {
303		compatible = "ingenic,jz4780-mmc";
304		reg = <0x13450000 0x1000>;
305
306		interrupt-parent = <&intc>;
307		interrupts = <37>;
308
309		clocks = <&cgu JZ4780_CLK_MSC0>;
310		clock-names = "mmc";
311
312		cap-sd-highspeed;
313		cap-mmc-highspeed;
314		cap-sdio-irq;
315		dmas = <&dma JZ4780_DMA_MSC0_RX 0xffffffff>,
316		       <&dma JZ4780_DMA_MSC0_TX 0xffffffff>;
317		dma-names = "rx", "tx";
318
319		status = "disabled";
320	};
321
322	mmc1: mmc@13460000 {
323		compatible = "ingenic,jz4780-mmc";
324		reg = <0x13460000 0x1000>;
325
326		interrupt-parent = <&intc>;
327		interrupts = <36>;
328
329		clocks = <&cgu JZ4780_CLK_MSC1>;
330		clock-names = "mmc";
331
332		cap-sd-highspeed;
333		cap-mmc-highspeed;
334		cap-sdio-irq;
335		dmas = <&dma JZ4780_DMA_MSC1_RX 0xffffffff>,
336		       <&dma JZ4780_DMA_MSC1_TX 0xffffffff>;
337		dma-names = "rx", "tx";
338
339		status = "disabled";
340	};
341
342	bch: bch@134d0000 {
343		compatible = "ingenic,jz4780-bch";
344		reg = <0x134d0000 0x10000>;
345
346		clocks = <&cgu JZ4780_CLK_BCH>;
347
348		status = "disabled";
349	};
350};
351