1// SPDX-License-Identifier: GPL-2.0
2#include <dt-bindings/clock/jz4780-cgu.h>
3#include <dt-bindings/dma/jz4780-dma.h>
4
5/ {
6	#address-cells = <1>;
7	#size-cells = <1>;
8	compatible = "ingenic,jz4780";
9
10	cpuintc: interrupt-controller {
11		#address-cells = <0>;
12		#interrupt-cells = <1>;
13		interrupt-controller;
14		compatible = "mti,cpu-interrupt-controller";
15	};
16
17	intc: interrupt-controller@10001000 {
18		compatible = "ingenic,jz4780-intc";
19		reg = <0x10001000 0x50>;
20
21		interrupt-controller;
22		#interrupt-cells = <1>;
23
24		interrupt-parent = <&cpuintc>;
25		interrupts = <2>;
26	};
27
28	ext: ext {
29		compatible = "fixed-clock";
30		#clock-cells = <0>;
31	};
32
33	rtc: rtc {
34		compatible = "fixed-clock";
35		#clock-cells = <0>;
36		clock-frequency = <32768>;
37	};
38
39	cgu: jz4780-cgu@10000000 {
40		compatible = "ingenic,jz4780-cgu";
41		reg = <0x10000000 0x100>;
42
43		clocks = <&ext>, <&rtc>;
44		clock-names = "ext", "rtc";
45
46		#clock-cells = <1>;
47	};
48
49	rtc_dev: rtc@10003000 {
50		compatible = "ingenic,jz4780-rtc";
51		reg = <0x10003000 0x4c>;
52
53		interrupt-parent = <&intc>;
54		interrupts = <32>;
55
56		clocks = <&cgu JZ4780_CLK_RTCLK>;
57		clock-names = "rtc";
58	};
59
60	pinctrl: pin-controller@10010000 {
61		compatible = "ingenic,jz4780-pinctrl";
62		reg = <0x10010000 0x600>;
63
64		#address-cells = <1>;
65		#size-cells = <0>;
66
67		gpa: gpio@0 {
68			compatible = "ingenic,jz4780-gpio";
69			reg = <0>;
70
71			gpio-controller;
72			gpio-ranges = <&pinctrl 0 0 32>;
73			#gpio-cells = <2>;
74
75			interrupt-controller;
76			#interrupt-cells = <2>;
77
78			interrupt-parent = <&intc>;
79			interrupts = <17>;
80		};
81
82		gpb: gpio@1 {
83			compatible = "ingenic,jz4780-gpio";
84			reg = <1>;
85
86			gpio-controller;
87			gpio-ranges = <&pinctrl 0 32 32>;
88			#gpio-cells = <2>;
89
90			interrupt-controller;
91			#interrupt-cells = <2>;
92
93			interrupt-parent = <&intc>;
94			interrupts = <16>;
95		};
96
97		gpc: gpio@2 {
98			compatible = "ingenic,jz4780-gpio";
99			reg = <2>;
100
101			gpio-controller;
102			gpio-ranges = <&pinctrl 0 64 32>;
103			#gpio-cells = <2>;
104
105			interrupt-controller;
106			#interrupt-cells = <2>;
107
108			interrupt-parent = <&intc>;
109			interrupts = <15>;
110		};
111
112		gpd: gpio@3 {
113			compatible = "ingenic,jz4780-gpio";
114			reg = <3>;
115
116			gpio-controller;
117			gpio-ranges = <&pinctrl 0 96 32>;
118			#gpio-cells = <2>;
119
120			interrupt-controller;
121			#interrupt-cells = <2>;
122
123			interrupt-parent = <&intc>;
124			interrupts = <14>;
125		};
126
127		gpe: gpio@4 {
128			compatible = "ingenic,jz4780-gpio";
129			reg = <4>;
130
131			gpio-controller;
132			gpio-ranges = <&pinctrl 0 128 32>;
133			#gpio-cells = <2>;
134
135			interrupt-controller;
136			#interrupt-cells = <2>;
137
138			interrupt-parent = <&intc>;
139			interrupts = <13>;
140		};
141
142		gpf: gpio@5 {
143			compatible = "ingenic,jz4780-gpio";
144			reg = <5>;
145
146			gpio-controller;
147			gpio-ranges = <&pinctrl 0 160 32>;
148			#gpio-cells = <2>;
149
150			interrupt-controller;
151			#interrupt-cells = <2>;
152
153			interrupt-parent = <&intc>;
154			interrupts = <12>;
155		};
156	};
157
158	uart0: serial@10030000 {
159		compatible = "ingenic,jz4780-uart";
160		reg = <0x10030000 0x100>;
161
162		interrupt-parent = <&intc>;
163		interrupts = <51>;
164
165		clocks = <&ext>, <&cgu JZ4780_CLK_UART0>;
166		clock-names = "baud", "module";
167
168		status = "disabled";
169	};
170
171	uart1: serial@10031000 {
172		compatible = "ingenic,jz4780-uart";
173		reg = <0x10031000 0x100>;
174
175		interrupt-parent = <&intc>;
176		interrupts = <50>;
177
178		clocks = <&ext>, <&cgu JZ4780_CLK_UART1>;
179		clock-names = "baud", "module";
180
181		status = "disabled";
182	};
183
184	uart2: serial@10032000 {
185		compatible = "ingenic,jz4780-uart";
186		reg = <0x10032000 0x100>;
187
188		interrupt-parent = <&intc>;
189		interrupts = <49>;
190
191		clocks = <&ext>, <&cgu JZ4780_CLK_UART2>;
192		clock-names = "baud", "module";
193
194		status = "disabled";
195	};
196
197	uart3: serial@10033000 {
198		compatible = "ingenic,jz4780-uart";
199		reg = <0x10033000 0x100>;
200
201		interrupt-parent = <&intc>;
202		interrupts = <48>;
203
204		clocks = <&ext>, <&cgu JZ4780_CLK_UART3>;
205		clock-names = "baud", "module";
206
207		status = "disabled";
208	};
209
210	uart4: serial@10034000 {
211		compatible = "ingenic,jz4780-uart";
212		reg = <0x10034000 0x100>;
213
214		interrupt-parent = <&intc>;
215		interrupts = <34>;
216
217		clocks = <&ext>, <&cgu JZ4780_CLK_UART4>;
218		clock-names = "baud", "module";
219
220		status = "disabled";
221	};
222
223	watchdog: watchdog@10002000 {
224		compatible = "ingenic,jz4780-watchdog";
225		reg = <0x10002000 0x10>;
226
227		clocks = <&cgu JZ4780_CLK_RTCLK>;
228		clock-names = "rtc";
229	};
230
231	nemc: nemc@13410000 {
232		compatible = "ingenic,jz4780-nemc";
233		reg = <0x13410000 0x10000>;
234		#address-cells = <2>;
235		#size-cells = <1>;
236		ranges = <1 0 0x1b000000 0x1000000
237			  2 0 0x1a000000 0x1000000
238			  3 0 0x19000000 0x1000000
239			  4 0 0x18000000 0x1000000
240			  5 0 0x17000000 0x1000000
241			  6 0 0x16000000 0x1000000>;
242
243		clocks = <&cgu JZ4780_CLK_NEMC>;
244
245		status = "disabled";
246	};
247
248	dma: dma@13420000 {
249		compatible = "ingenic,jz4780-dma";
250		reg = <0x13420000 0x10000>;
251		#dma-cells = <2>;
252
253		interrupt-parent = <&intc>;
254		interrupts = <10>;
255
256		clocks = <&cgu JZ4780_CLK_PDMA>;
257	};
258
259	mmc0: mmc@13450000 {
260		compatible = "ingenic,jz4780-mmc";
261		reg = <0x13450000 0x1000>;
262
263		interrupt-parent = <&intc>;
264		interrupts = <37>;
265
266		clocks = <&cgu JZ4780_CLK_MSC0>;
267		clock-names = "mmc";
268
269		cap-sd-highspeed;
270		cap-mmc-highspeed;
271		cap-sdio-irq;
272		dmas = <&dma JZ4780_DMA_MSC0_RX 0xffffffff>,
273		       <&dma JZ4780_DMA_MSC0_TX 0xffffffff>;
274		dma-names = "rx", "tx";
275
276		status = "disabled";
277	};
278
279	mmc1: mmc@13460000 {
280		compatible = "ingenic,jz4780-mmc";
281		reg = <0x13460000 0x1000>;
282
283		interrupt-parent = <&intc>;
284		interrupts = <36>;
285
286		clocks = <&cgu JZ4780_CLK_MSC1>;
287		clock-names = "mmc";
288
289		cap-sd-highspeed;
290		cap-mmc-highspeed;
291		cap-sdio-irq;
292		dmas = <&dma JZ4780_DMA_MSC1_RX 0xffffffff>,
293		       <&dma JZ4780_DMA_MSC1_TX 0xffffffff>;
294		dma-names = "rx", "tx";
295
296		status = "disabled";
297	};
298
299	bch: bch@134d0000 {
300		compatible = "ingenic,jz4780-bch";
301		reg = <0x134d0000 0x10000>;
302
303		clocks = <&cgu JZ4780_CLK_BCH>;
304
305		status = "disabled";
306	};
307};
308