1// SPDX-License-Identifier: GPL-2.0
2#include <dt-bindings/clock/jz4780-cgu.h>
3#include <dt-bindings/clock/ingenic,tcu.h>
4#include <dt-bindings/dma/jz4780-dma.h>
5
6/ {
7	#address-cells = <1>;
8	#size-cells = <1>;
9	compatible = "ingenic,jz4780";
10
11	cpuintc: interrupt-controller {
12		#address-cells = <0>;
13		#interrupt-cells = <1>;
14		interrupt-controller;
15		compatible = "mti,cpu-interrupt-controller";
16	};
17
18	intc: interrupt-controller@10001000 {
19		compatible = "ingenic,jz4780-intc";
20		reg = <0x10001000 0x50>;
21
22		interrupt-controller;
23		#interrupt-cells = <1>;
24
25		interrupt-parent = <&cpuintc>;
26		interrupts = <2>;
27	};
28
29	ext: ext {
30		compatible = "fixed-clock";
31		#clock-cells = <0>;
32	};
33
34	rtc: rtc {
35		compatible = "fixed-clock";
36		#clock-cells = <0>;
37		clock-frequency = <32768>;
38	};
39
40	cgu: jz4780-cgu@10000000 {
41		compatible = "ingenic,jz4780-cgu";
42		reg = <0x10000000 0x100>;
43
44		clocks = <&ext>, <&rtc>;
45		clock-names = "ext", "rtc";
46
47		#clock-cells = <1>;
48	};
49
50	tcu: timer@10002000 {
51		compatible = "ingenic,jz4780-tcu",
52			     "ingenic,jz4770-tcu",
53			     "simple-mfd";
54		reg = <0x10002000 0x1000>;
55		#address-cells = <1>;
56		#size-cells = <1>;
57		ranges = <0x0 0x10002000 0x1000>;
58
59		#clock-cells = <1>;
60
61		clocks = <&cgu JZ4780_CLK_RTCLK
62			  &cgu JZ4780_CLK_EXCLK
63			  &cgu JZ4780_CLK_PCLK>;
64		clock-names = "rtc", "ext", "pclk";
65
66		interrupt-controller;
67		#interrupt-cells = <1>;
68
69		interrupt-parent = <&intc>;
70		interrupts = <27 26 25>;
71
72		watchdog: watchdog@0 {
73			compatible = "ingenic,jz4780-watchdog";
74			reg = <0x0 0xc>;
75
76			clocks = <&tcu TCU_CLK_WDT>;
77			clock-names = "wdt";
78		};
79	};
80
81	rtc_dev: rtc@10003000 {
82		compatible = "ingenic,jz4780-rtc";
83		reg = <0x10003000 0x4c>;
84
85		interrupt-parent = <&intc>;
86		interrupts = <32>;
87
88		clocks = <&cgu JZ4780_CLK_RTCLK>;
89		clock-names = "rtc";
90	};
91
92	pinctrl: pin-controller@10010000 {
93		compatible = "ingenic,jz4780-pinctrl";
94		reg = <0x10010000 0x600>;
95
96		#address-cells = <1>;
97		#size-cells = <0>;
98
99		gpa: gpio@0 {
100			compatible = "ingenic,jz4780-gpio";
101			reg = <0>;
102
103			gpio-controller;
104			gpio-ranges = <&pinctrl 0 0 32>;
105			#gpio-cells = <2>;
106
107			interrupt-controller;
108			#interrupt-cells = <2>;
109
110			interrupt-parent = <&intc>;
111			interrupts = <17>;
112		};
113
114		gpb: gpio@1 {
115			compatible = "ingenic,jz4780-gpio";
116			reg = <1>;
117
118			gpio-controller;
119			gpio-ranges = <&pinctrl 0 32 32>;
120			#gpio-cells = <2>;
121
122			interrupt-controller;
123			#interrupt-cells = <2>;
124
125			interrupt-parent = <&intc>;
126			interrupts = <16>;
127		};
128
129		gpc: gpio@2 {
130			compatible = "ingenic,jz4780-gpio";
131			reg = <2>;
132
133			gpio-controller;
134			gpio-ranges = <&pinctrl 0 64 32>;
135			#gpio-cells = <2>;
136
137			interrupt-controller;
138			#interrupt-cells = <2>;
139
140			interrupt-parent = <&intc>;
141			interrupts = <15>;
142		};
143
144		gpd: gpio@3 {
145			compatible = "ingenic,jz4780-gpio";
146			reg = <3>;
147
148			gpio-controller;
149			gpio-ranges = <&pinctrl 0 96 32>;
150			#gpio-cells = <2>;
151
152			interrupt-controller;
153			#interrupt-cells = <2>;
154
155			interrupt-parent = <&intc>;
156			interrupts = <14>;
157		};
158
159		gpe: gpio@4 {
160			compatible = "ingenic,jz4780-gpio";
161			reg = <4>;
162
163			gpio-controller;
164			gpio-ranges = <&pinctrl 0 128 32>;
165			#gpio-cells = <2>;
166
167			interrupt-controller;
168			#interrupt-cells = <2>;
169
170			interrupt-parent = <&intc>;
171			interrupts = <13>;
172		};
173
174		gpf: gpio@5 {
175			compatible = "ingenic,jz4780-gpio";
176			reg = <5>;
177
178			gpio-controller;
179			gpio-ranges = <&pinctrl 0 160 32>;
180			#gpio-cells = <2>;
181
182			interrupt-controller;
183			#interrupt-cells = <2>;
184
185			interrupt-parent = <&intc>;
186			interrupts = <12>;
187		};
188	};
189
190	spi_gpio {
191		compatible = "spi-gpio";
192		#address-cells = <1>;
193		#size-cells = <0>;
194		num-chipselects = <2>;
195
196		gpio-miso = <&gpe 14 0>;
197		gpio-sck = <&gpe 15 0>;
198		gpio-mosi = <&gpe 17 0>;
199		cs-gpios = <&gpe 16 0
200			    &gpe 18 0>;
201
202		spidev@0 {
203			compatible = "spidev";
204			reg = <0>;
205			spi-max-frequency = <1000000>;
206		};
207	};
208
209	uart0: serial@10030000 {
210		compatible = "ingenic,jz4780-uart";
211		reg = <0x10030000 0x100>;
212
213		interrupt-parent = <&intc>;
214		interrupts = <51>;
215
216		clocks = <&ext>, <&cgu JZ4780_CLK_UART0>;
217		clock-names = "baud", "module";
218
219		status = "disabled";
220	};
221
222	uart1: serial@10031000 {
223		compatible = "ingenic,jz4780-uart";
224		reg = <0x10031000 0x100>;
225
226		interrupt-parent = <&intc>;
227		interrupts = <50>;
228
229		clocks = <&ext>, <&cgu JZ4780_CLK_UART1>;
230		clock-names = "baud", "module";
231
232		status = "disabled";
233	};
234
235	uart2: serial@10032000 {
236		compatible = "ingenic,jz4780-uart";
237		reg = <0x10032000 0x100>;
238
239		interrupt-parent = <&intc>;
240		interrupts = <49>;
241
242		clocks = <&ext>, <&cgu JZ4780_CLK_UART2>;
243		clock-names = "baud", "module";
244
245		status = "disabled";
246	};
247
248	uart3: serial@10033000 {
249		compatible = "ingenic,jz4780-uart";
250		reg = <0x10033000 0x100>;
251
252		interrupt-parent = <&intc>;
253		interrupts = <48>;
254
255		clocks = <&ext>, <&cgu JZ4780_CLK_UART3>;
256		clock-names = "baud", "module";
257
258		status = "disabled";
259	};
260
261	uart4: serial@10034000 {
262		compatible = "ingenic,jz4780-uart";
263		reg = <0x10034000 0x100>;
264
265		interrupt-parent = <&intc>;
266		interrupts = <34>;
267
268		clocks = <&ext>, <&cgu JZ4780_CLK_UART4>;
269		clock-names = "baud", "module";
270
271		status = "disabled";
272	};
273
274	i2c0: i2c@10050000 {
275		compatible = "ingenic,jz4780-i2c";
276		#address-cells = <1>;
277		#size-cells = <0>;
278
279		reg = <0x10050000 0x1000>;
280
281		interrupt-parent = <&intc>;
282		interrupts = <60>;
283
284		clocks = <&cgu JZ4780_CLK_SMB0>;
285		clock-frequency = <100000>;
286		pinctrl-names = "default";
287		pinctrl-0 = <&pins_i2c0_data>;
288
289		status = "disabled";
290	};
291
292	i2c1: i2c@10051000 {
293		compatible = "ingenic,jz4780-i2c";
294		#address-cells = <1>;
295		#size-cells = <0>;
296		reg = <0x10051000 0x1000>;
297
298		interrupt-parent = <&intc>;
299		interrupts = <59>;
300
301		clocks = <&cgu JZ4780_CLK_SMB1>;
302		clock-frequency = <100000>;
303		pinctrl-names = "default";
304		pinctrl-0 = <&pins_i2c1_data>;
305
306		status = "disabled";
307	};
308
309	i2c2: i2c@10052000 {
310		compatible = "ingenic,jz4780-i2c";
311		#address-cells = <1>;
312		#size-cells = <0>;
313		reg = <0x10052000 0x1000>;
314
315		interrupt-parent = <&intc>;
316		interrupts = <58>;
317
318		clocks = <&cgu JZ4780_CLK_SMB2>;
319		clock-frequency = <100000>;
320		pinctrl-names = "default";
321		pinctrl-0 = <&pins_i2c2_data>;
322
323		status = "disabled";
324	};
325
326	i2c3: i2c@10053000 {
327		compatible = "ingenic,jz4780-i2c";
328		#address-cells = <1>;
329		#size-cells = <0>;
330		reg = <0x10053000 0x1000>;
331
332		interrupt-parent = <&intc>;
333		interrupts = <57>;
334
335		clocks = <&cgu JZ4780_CLK_SMB3>;
336		clock-frequency = <100000>;
337		pinctrl-names = "default";
338		pinctrl-0 = <&pins_i2c3_data>;
339
340		status = "disabled";
341	};
342
343	i2c4: i2c@10054000 {
344		compatible = "ingenic,jz4780-i2c";
345		#address-cells = <1>;
346		#size-cells = <0>;
347		reg = <0x10054000 0x1000>;
348
349		interrupt-parent = <&intc>;
350		interrupts = <56>;
351
352		clocks = <&cgu JZ4780_CLK_SMB4>;
353		clock-frequency = <100000>;
354		pinctrl-names = "default";
355		pinctrl-0 = <&pins_i2c4_data>;
356
357		status = "disabled";
358	};
359
360	nemc: nemc@13410000 {
361		compatible = "ingenic,jz4780-nemc";
362		reg = <0x13410000 0x10000>;
363		#address-cells = <2>;
364		#size-cells = <1>;
365		ranges = <1 0 0x1b000000 0x1000000
366			  2 0 0x1a000000 0x1000000
367			  3 0 0x19000000 0x1000000
368			  4 0 0x18000000 0x1000000
369			  5 0 0x17000000 0x1000000
370			  6 0 0x16000000 0x1000000>;
371
372		clocks = <&cgu JZ4780_CLK_NEMC>;
373
374		status = "disabled";
375	};
376
377	dma: dma@13420000 {
378		compatible = "ingenic,jz4780-dma";
379		reg = <0x13420000 0x400
380		       0x13421000 0x40>;
381		#dma-cells = <2>;
382
383		interrupt-parent = <&intc>;
384		interrupts = <10>;
385
386		clocks = <&cgu JZ4780_CLK_PDMA>;
387	};
388
389	mmc0: mmc@13450000 {
390		compatible = "ingenic,jz4780-mmc";
391		reg = <0x13450000 0x1000>;
392
393		interrupt-parent = <&intc>;
394		interrupts = <37>;
395
396		clocks = <&cgu JZ4780_CLK_MSC0>;
397		clock-names = "mmc";
398
399		cap-sd-highspeed;
400		cap-mmc-highspeed;
401		cap-sdio-irq;
402		dmas = <&dma JZ4780_DMA_MSC0_RX 0xffffffff>,
403		       <&dma JZ4780_DMA_MSC0_TX 0xffffffff>;
404		dma-names = "rx", "tx";
405
406		status = "disabled";
407	};
408
409	mmc1: mmc@13460000 {
410		compatible = "ingenic,jz4780-mmc";
411		reg = <0x13460000 0x1000>;
412
413		interrupt-parent = <&intc>;
414		interrupts = <36>;
415
416		clocks = <&cgu JZ4780_CLK_MSC1>;
417		clock-names = "mmc";
418
419		cap-sd-highspeed;
420		cap-mmc-highspeed;
421		cap-sdio-irq;
422		dmas = <&dma JZ4780_DMA_MSC1_RX 0xffffffff>,
423		       <&dma JZ4780_DMA_MSC1_TX 0xffffffff>;
424		dma-names = "rx", "tx";
425
426		status = "disabled";
427	};
428
429	bch: bch@134d0000 {
430		compatible = "ingenic,jz4780-bch";
431		reg = <0x134d0000 0x10000>;
432
433		clocks = <&cgu JZ4780_CLK_BCH>;
434
435		status = "disabled";
436	};
437};
438