1// SPDX-License-Identifier: GPL-2.0 2 3#include <dt-bindings/clock/jz4770-cgu.h> 4#include <dt-bindings/clock/ingenic,tcu.h> 5 6/ { 7 #address-cells = <1>; 8 #size-cells = <1>; 9 compatible = "ingenic,jz4770"; 10 11 cpuintc: interrupt-controller { 12 #address-cells = <0>; 13 #interrupt-cells = <1>; 14 interrupt-controller; 15 compatible = "mti,cpu-interrupt-controller"; 16 }; 17 18 intc: interrupt-controller@10001000 { 19 compatible = "ingenic,jz4770-intc"; 20 reg = <0x10001000 0x40>; 21 22 interrupt-controller; 23 #interrupt-cells = <1>; 24 25 interrupt-parent = <&cpuintc>; 26 interrupts = <2>; 27 }; 28 29 ext: ext { 30 compatible = "fixed-clock"; 31 #clock-cells = <0>; 32 }; 33 34 osc32k: osc32k { 35 compatible = "fixed-clock"; 36 #clock-cells = <0>; 37 clock-frequency = <32768>; 38 }; 39 40 cgu: jz4770-cgu@10000000 { 41 compatible = "ingenic,jz4770-cgu", "simple-mfd"; 42 reg = <0x10000000 0x100>; 43 #address-cells = <1>; 44 #size-cells = <1>; 45 ranges = <0x0 0x10000000 0x100>; 46 47 clocks = <&ext>, <&osc32k>; 48 clock-names = "ext", "osc32k"; 49 50 #clock-cells = <1>; 51 52 otg_phy: usb-phy@3c { 53 compatible = "ingenic,jz4770-phy"; 54 reg = <0x3c 0x10>; 55 56 clocks = <&cgu JZ4770_CLK_OTG_PHY>; 57 58 #phy-cells = <0>; 59 }; 60 }; 61 62 tcu: timer@10002000 { 63 compatible = "ingenic,jz4770-tcu", "simple-mfd"; 64 reg = <0x10002000 0x1000>; 65 #address-cells = <1>; 66 #size-cells = <1>; 67 ranges = <0x0 0x10002000 0x1000>; 68 69 #clock-cells = <1>; 70 71 clocks = <&cgu JZ4770_CLK_RTC>, 72 <&cgu JZ4770_CLK_EXT>, 73 <&cgu JZ4770_CLK_PCLK>; 74 clock-names = "rtc", "ext", "pclk"; 75 76 interrupt-controller; 77 #interrupt-cells = <1>; 78 79 interrupt-parent = <&intc>; 80 interrupts = <27 26 25>; 81 82 watchdog: watchdog@0 { 83 compatible = "ingenic,jz4770-watchdog", 84 "ingenic,jz4740-watchdog"; 85 reg = <0x0 0xc>; 86 87 clocks = <&tcu TCU_CLK_WDT>; 88 clock-names = "wdt"; 89 }; 90 91 pwm: pwm@40 { 92 compatible = "ingenic,jz4770-pwm", "ingenic,jz4740-pwm"; 93 reg = <0x40 0x80>; 94 95 #pwm-cells = <3>; 96 97 clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>, 98 <&tcu TCU_CLK_TIMER2>, <&tcu TCU_CLK_TIMER3>, 99 <&tcu TCU_CLK_TIMER4>, <&tcu TCU_CLK_TIMER5>, 100 <&tcu TCU_CLK_TIMER6>, <&tcu TCU_CLK_TIMER7>; 101 clock-names = "timer0", "timer1", "timer2", "timer3", 102 "timer4", "timer5", "timer6", "timer7"; 103 }; 104 105 ost: timer@e0 { 106 compatible = "ingenic,jz4770-ost"; 107 reg = <0xe0 0x20>; 108 109 clocks = <&tcu TCU_CLK_OST>; 110 clock-names = "ost"; 111 112 interrupts = <15>; 113 }; 114 }; 115 116 rtc: rtc@10003000 { 117 compatible = "ingenic,jz4770-rtc", "ingenic,jz4760-rtc"; 118 reg = <0x10003000 0x40>; 119 120 interrupt-parent = <&intc>; 121 interrupts = <32>; 122 }; 123 124 pinctrl: pin-controller@10010000 { 125 compatible = "ingenic,jz4770-pinctrl"; 126 reg = <0x10010000 0x600>; 127 128 #address-cells = <1>; 129 #size-cells = <0>; 130 131 gpa: gpio@0 { 132 compatible = "ingenic,jz4770-gpio"; 133 reg = <0>; 134 135 gpio-controller; 136 gpio-ranges = <&pinctrl 0 0 32>; 137 #gpio-cells = <2>; 138 139 interrupt-controller; 140 #interrupt-cells = <2>; 141 142 interrupt-parent = <&intc>; 143 interrupts = <17>; 144 }; 145 146 gpb: gpio@1 { 147 compatible = "ingenic,jz4770-gpio"; 148 reg = <1>; 149 150 gpio-controller; 151 gpio-ranges = <&pinctrl 0 32 32>; 152 #gpio-cells = <2>; 153 154 interrupt-controller; 155 #interrupt-cells = <2>; 156 157 interrupt-parent = <&intc>; 158 interrupts = <16>; 159 }; 160 161 gpc: gpio@2 { 162 compatible = "ingenic,jz4770-gpio"; 163 reg = <2>; 164 165 gpio-controller; 166 gpio-ranges = <&pinctrl 0 64 32>; 167 #gpio-cells = <2>; 168 169 interrupt-controller; 170 #interrupt-cells = <2>; 171 172 interrupt-parent = <&intc>; 173 interrupts = <15>; 174 }; 175 176 gpd: gpio@3 { 177 compatible = "ingenic,jz4770-gpio"; 178 reg = <3>; 179 180 gpio-controller; 181 gpio-ranges = <&pinctrl 0 96 32>; 182 #gpio-cells = <2>; 183 184 interrupt-controller; 185 #interrupt-cells = <2>; 186 187 interrupt-parent = <&intc>; 188 interrupts = <14>; 189 }; 190 191 gpe: gpio@4 { 192 compatible = "ingenic,jz4770-gpio"; 193 reg = <4>; 194 195 gpio-controller; 196 gpio-ranges = <&pinctrl 0 128 32>; 197 #gpio-cells = <2>; 198 199 interrupt-controller; 200 #interrupt-cells = <2>; 201 202 interrupt-parent = <&intc>; 203 interrupts = <13>; 204 }; 205 206 gpf: gpio@5 { 207 compatible = "ingenic,jz4770-gpio"; 208 reg = <5>; 209 210 gpio-controller; 211 gpio-ranges = <&pinctrl 0 160 32>; 212 #gpio-cells = <2>; 213 214 interrupt-controller; 215 #interrupt-cells = <2>; 216 217 interrupt-parent = <&intc>; 218 interrupts = <12>; 219 }; 220 }; 221 222 aic: audio-controller@10020000 { 223 compatible = "ingenic,jz4770-i2s"; 224 reg = <0x10020000 0x94>; 225 226 #sound-dai-cells = <0>; 227 228 clocks = <&cgu JZ4770_CLK_AIC>, <&cgu JZ4770_CLK_I2S>, 229 <&cgu JZ4770_CLK_EXT>, <&cgu JZ4770_CLK_PLL0>; 230 clock-names = "aic", "i2s", "ext", "pll half"; 231 232 interrupt-parent = <&intc>; 233 interrupts = <34>; 234 235 dmas = <&dmac0 25 0xffffffff>, <&dmac0 24 0xffffffff>; 236 dma-names = "rx", "tx"; 237 }; 238 239 codec: audio-codec@100200a0 { 240 compatible = "ingenic,jz4770-codec"; 241 reg = <0x100200a4 0x8>; 242 243 #sound-dai-cells = <0>; 244 245 clocks = <&cgu JZ4770_CLK_AIC>; 246 clock-names = "aic"; 247 }; 248 249 mmc0: mmc@10021000 { 250 compatible = "ingenic,jz4770-mmc", "ingenic,jz4760-mmc"; 251 reg = <0x10021000 0x1000>; 252 253 clocks = <&cgu JZ4770_CLK_MMC0>; 254 clock-names = "mmc"; 255 256 interrupt-parent = <&intc>; 257 interrupts = <37>; 258 259 dmas = <&dmac1 27 0xffffffff>, <&dmac1 26 0xffffffff>; 260 dma-names = "rx", "tx"; 261 262 cap-sd-highspeed; 263 cap-mmc-highspeed; 264 cap-sdio-irq; 265 266 status = "disabled"; 267 }; 268 269 mmc1: mmc@10022000 { 270 compatible = "ingenic,jz4770-mmc", "ingenic,jz4760-mmc"; 271 reg = <0x10022000 0x1000>; 272 273 clocks = <&cgu JZ4770_CLK_MMC1>; 274 clock-names = "mmc"; 275 276 interrupt-parent = <&intc>; 277 interrupts = <36>; 278 279 dmas = <&dmac1 31 0xffffffff>, <&dmac1 30 0xffffffff>; 280 dma-names = "rx", "tx"; 281 282 cap-sd-highspeed; 283 cap-mmc-highspeed; 284 cap-sdio-irq; 285 286 status = "disabled"; 287 }; 288 289 mmc2: mmc@10023000 { 290 compatible = "ingenic,jz4770-mmc", "ingenic,jz4760-mmc"; 291 reg = <0x10023000 0x1000>; 292 293 clocks = <&cgu JZ4770_CLK_MMC2>; 294 clock-names = "mmc"; 295 296 interrupt-parent = <&intc>; 297 interrupts = <35>; 298 299 dmas = <&dmac1 37 0xffffffff>, <&dmac1 36 0xffffffff>; 300 dma-names = "rx", "tx"; 301 302 cap-sd-highspeed; 303 cap-mmc-highspeed; 304 cap-sdio-irq; 305 306 status = "disabled"; 307 }; 308 309 uart0: serial@10030000 { 310 compatible = "ingenic,jz4770-uart"; 311 reg = <0x10030000 0x100>; 312 313 clocks = <&ext>, <&cgu JZ4770_CLK_UART0>; 314 clock-names = "baud", "module"; 315 316 interrupt-parent = <&intc>; 317 interrupts = <5>; 318 319 status = "disabled"; 320 }; 321 322 uart1: serial@10031000 { 323 compatible = "ingenic,jz4770-uart"; 324 reg = <0x10031000 0x100>; 325 326 clocks = <&ext>, <&cgu JZ4770_CLK_UART1>; 327 clock-names = "baud", "module"; 328 329 interrupt-parent = <&intc>; 330 interrupts = <4>; 331 332 status = "disabled"; 333 }; 334 335 uart2: serial@10032000 { 336 compatible = "ingenic,jz4770-uart"; 337 reg = <0x10032000 0x100>; 338 339 clocks = <&ext>, <&cgu JZ4770_CLK_UART2>; 340 clock-names = "baud", "module"; 341 342 interrupt-parent = <&intc>; 343 interrupts = <3>; 344 345 status = "disabled"; 346 }; 347 348 uart3: serial@10033000 { 349 compatible = "ingenic,jz4770-uart"; 350 reg = <0x10033000 0x100>; 351 352 clocks = <&ext>, <&cgu JZ4770_CLK_UART3>; 353 clock-names = "baud", "module"; 354 355 interrupt-parent = <&intc>; 356 interrupts = <2>; 357 358 status = "disabled"; 359 }; 360 361 adc: adc@10070000 { 362 compatible = "ingenic,jz4770-adc"; 363 reg = <0x10070000 0x30>; 364 365 #io-channel-cells = <1>; 366 367 clocks = <&cgu JZ4770_CLK_ADC>; 368 clock-names = "adc"; 369 370 interrupt-parent = <&intc>; 371 interrupts = <18>; 372 }; 373 374 gpu: gpu@13040000 { 375 compatible = "vivante,gc"; 376 reg = <0x13040000 0x10000>; 377 378 clocks = <&cgu JZ4770_CLK_GPU>, 379 <&cgu JZ4770_CLK_GPU>, 380 <&cgu JZ4770_CLK_GPU>; 381 clock-names = "bus", "core", "shader"; 382 383 interrupt-parent = <&intc>; 384 interrupts = <6>; 385 }; 386 387 lcd: lcd-controller@13050000 { 388 compatible = "ingenic,jz4770-lcd"; 389 reg = <0x13050000 0x300>; 390 391 interrupt-parent = <&intc>; 392 interrupts = <31>; 393 394 clocks = <&cgu JZ4770_CLK_LPCLK_MUX>; 395 clock-names = "lcd_pclk"; 396 }; 397 398 dmac0: dma-controller@13420000 { 399 compatible = "ingenic,jz4770-dma"; 400 reg = <0x13420000 0xC0>, <0x13420300 0x20>; 401 402 #dma-cells = <2>; 403 404 clocks = <&cgu JZ4770_CLK_DMA>; 405 interrupt-parent = <&intc>; 406 interrupts = <24>; 407 }; 408 409 dmac1: dma-controller@13420100 { 410 compatible = "ingenic,jz4770-dma"; 411 reg = <0x13420100 0xC0>, <0x13420400 0x20>; 412 413 #dma-cells = <2>; 414 415 clocks = <&cgu JZ4770_CLK_DMA>; 416 interrupt-parent = <&intc>; 417 interrupts = <23>; 418 }; 419 420 uhc: uhc@13430000 { 421 compatible = "generic-ohci"; 422 reg = <0x13430000 0x1000>; 423 424 clocks = <&cgu JZ4770_CLK_UHC>, <&cgu JZ4770_CLK_UHC_PHY>; 425 assigned-clocks = <&cgu JZ4770_CLK_UHC>; 426 assigned-clock-rates = <48000000>; 427 428 interrupt-parent = <&intc>; 429 interrupts = <20>; 430 431 status = "disabled"; 432 }; 433 434 usb_otg: usb@13440000 { 435 compatible = "ingenic,jz4770-musb"; 436 reg = <0x13440000 0x10000>; 437 438 clocks = <&cgu JZ4770_CLK_OTG>; 439 clock-names = "udc"; 440 441 interrupt-parent = <&intc>; 442 interrupts = <21>; 443 interrupt-names = "mc"; 444 445 phys = <&otg_phy>; 446 447 usb-role-switch; 448 }; 449 450 rom: memory@1fc00000 { 451 compatible = "mtd-rom"; 452 probe-type = "map_rom"; 453 reg = <0x1fc00000 0x2000>; 454 455 bank-width = <4>; 456 device-width = <1>; 457 }; 458}; 459