1// SPDX-License-Identifier: GPL-2.0
2#include <dt-bindings/clock/jz4740-cgu.h>
3
4/ {
5	#address-cells = <1>;
6	#size-cells = <1>;
7	compatible = "ingenic,jz4740";
8
9	cpuintc: interrupt-controller {
10		#address-cells = <0>;
11		#interrupt-cells = <1>;
12		interrupt-controller;
13		compatible = "mti,cpu-interrupt-controller";
14	};
15
16	intc: interrupt-controller@10001000 {
17		compatible = "ingenic,jz4740-intc";
18		reg = <0x10001000 0x14>;
19
20		interrupt-controller;
21		#interrupt-cells = <1>;
22
23		interrupt-parent = <&cpuintc>;
24		interrupts = <2>;
25	};
26
27	ext: ext {
28		compatible = "fixed-clock";
29		#clock-cells = <0>;
30	};
31
32	rtc: rtc {
33		compatible = "fixed-clock";
34		#clock-cells = <0>;
35		clock-frequency = <32768>;
36	};
37
38	cgu: jz4740-cgu@10000000 {
39		compatible = "ingenic,jz4740-cgu";
40		reg = <0x10000000 0x100>;
41
42		clocks = <&ext>, <&rtc>;
43		clock-names = "ext", "rtc";
44
45		#clock-cells = <1>;
46	};
47
48	watchdog: watchdog@10002000 {
49		compatible = "ingenic,jz4740-watchdog";
50		reg = <0x10002000 0x10>;
51
52		clocks = <&cgu JZ4740_CLK_RTC>;
53		clock-names = "rtc";
54	};
55
56	tcu: timer@10002000 {
57		compatible = "ingenic,jz4740-tcu", "simple-mfd";
58		reg = <0x10002000 0x1000>;
59		#address-cells = <1>;
60		#size-cells = <1>;
61		ranges = <0x0 0x10002000 0x1000>;
62
63		#clock-cells = <1>;
64
65		clocks = <&cgu JZ4740_CLK_RTC
66			  &cgu JZ4740_CLK_EXT
67			  &cgu JZ4740_CLK_PCLK
68			  &cgu JZ4740_CLK_TCU>;
69		clock-names = "rtc", "ext", "pclk", "tcu";
70
71		interrupt-controller;
72		#interrupt-cells = <1>;
73
74		interrupt-parent = <&intc>;
75		interrupts = <23 22 21>;
76	};
77
78	rtc_dev: rtc@10003000 {
79		compatible = "ingenic,jz4740-rtc";
80		reg = <0x10003000 0x40>;
81
82		interrupt-parent = <&intc>;
83		interrupts = <15>;
84
85		clocks = <&cgu JZ4740_CLK_RTC>;
86		clock-names = "rtc";
87	};
88
89	pinctrl: pin-controller@10010000 {
90		compatible = "ingenic,jz4740-pinctrl";
91		reg = <0x10010000 0x400>;
92
93		#address-cells = <1>;
94		#size-cells = <0>;
95
96		gpa: gpio@0 {
97			compatible = "ingenic,jz4740-gpio";
98			reg = <0>;
99
100			gpio-controller;
101			gpio-ranges = <&pinctrl 0 0 32>;
102			#gpio-cells = <2>;
103
104			interrupt-controller;
105			#interrupt-cells = <2>;
106
107			interrupt-parent = <&intc>;
108			interrupts = <28>;
109		};
110
111		gpb: gpio@1 {
112			compatible = "ingenic,jz4740-gpio";
113			reg = <1>;
114
115			gpio-controller;
116			gpio-ranges = <&pinctrl 0 32 32>;
117			#gpio-cells = <2>;
118
119			interrupt-controller;
120			#interrupt-cells = <2>;
121
122			interrupt-parent = <&intc>;
123			interrupts = <27>;
124		};
125
126		gpc: gpio@2 {
127			compatible = "ingenic,jz4740-gpio";
128			reg = <2>;
129
130			gpio-controller;
131			gpio-ranges = <&pinctrl 0 64 32>;
132			#gpio-cells = <2>;
133
134			interrupt-controller;
135			#interrupt-cells = <2>;
136
137			interrupt-parent = <&intc>;
138			interrupts = <26>;
139		};
140
141		gpd: gpio@3 {
142			compatible = "ingenic,jz4740-gpio";
143			reg = <3>;
144
145			gpio-controller;
146			gpio-ranges = <&pinctrl 0 96 32>;
147			#gpio-cells = <2>;
148
149			interrupt-controller;
150			#interrupt-cells = <2>;
151
152			interrupt-parent = <&intc>;
153			interrupts = <25>;
154		};
155	};
156
157	aic: audio-controller@10020000 {
158		compatible = "ingenic,jz4740-i2s";
159		reg = <0x10020000 0x38>;
160
161		#sound-dai-cells = <0>;
162
163		interrupt-parent = <&intc>;
164		interrupts = <18>;
165
166		clocks = <&cgu JZ4740_CLK_AIC>,
167			 <&cgu JZ4740_CLK_I2S>,
168			 <&cgu JZ4740_CLK_EXT>,
169			 <&cgu JZ4740_CLK_PLL_HALF>;
170		clock-names = "aic", "i2s", "ext", "pll half";
171
172		dmas = <&dmac 25 0xffffffff>, <&dmac 24 0xffffffff>;
173		dma-names = "rx", "tx";
174	};
175
176	codec: audio-codec@100200a4 {
177		compatible = "ingenic,jz4740-codec";
178		reg = <0x10020080 0x8>;
179
180		#sound-dai-cells = <0>;
181
182		clocks = <&cgu JZ4740_CLK_AIC>;
183		clock-names = "aic";
184	};
185
186	mmc: mmc@10021000 {
187		compatible = "ingenic,jz4740-mmc";
188		reg = <0x10021000 0x1000>;
189
190		clocks = <&cgu JZ4740_CLK_MMC>;
191		clock-names = "mmc";
192
193		interrupt-parent = <&intc>;
194		interrupts = <14>;
195
196		dmas = <&dmac 27 0xffffffff>, <&dmac 26 0xffffffff>;
197		dma-names = "rx", "tx";
198
199		cap-sd-highspeed;
200		cap-mmc-highspeed;
201		cap-sdio-irq;
202	};
203
204	uart0: serial@10030000 {
205		compatible = "ingenic,jz4740-uart";
206		reg = <0x10030000 0x100>;
207
208		interrupt-parent = <&intc>;
209		interrupts = <9>;
210
211		clocks = <&ext>, <&cgu JZ4740_CLK_UART0>;
212		clock-names = "baud", "module";
213	};
214
215	uart1: serial@10031000 {
216		compatible = "ingenic,jz4740-uart";
217		reg = <0x10031000 0x100>;
218
219		interrupt-parent = <&intc>;
220		interrupts = <8>;
221
222		clocks = <&ext>, <&cgu JZ4740_CLK_UART1>;
223		clock-names = "baud", "module";
224	};
225
226	adc: adc@10070000 {
227		compatible = "ingenic,jz4740-adc";
228		reg = <0x10070000 0x30>;
229		#io-channel-cells = <1>;
230
231		clocks = <&cgu JZ4740_CLK_ADC>;
232		clock-names = "adc";
233
234		interrupt-parent = <&intc>;
235		interrupts = <12>;
236	};
237
238	nemc: memory-controller@13010000 {
239		compatible = "ingenic,jz4740-nemc";
240		reg = <0x13010000 0x54>;
241		#address-cells = <2>;
242		#size-cells = <1>;
243		ranges = <1 0 0x18000000 0x4000000
244			  2 0 0x14000000 0x4000000
245			  3 0 0x0c000000 0x4000000
246			  4 0 0x08000000 0x4000000>;
247
248		clocks = <&cgu JZ4740_CLK_MCLK>;
249	};
250
251	ecc: ecc-controller@13010100 {
252		compatible = "ingenic,jz4740-ecc";
253		reg = <0x13010100 0x2C>;
254
255		clocks = <&cgu JZ4740_CLK_MCLK>;
256	};
257
258	dmac: dma-controller@13020000 {
259		compatible = "ingenic,jz4740-dma";
260		reg = <0x13020000 0xbc
261		       0x13020300 0x14>;
262		#dma-cells = <2>;
263
264		interrupt-parent = <&intc>;
265		interrupts = <20>;
266
267		clocks = <&cgu JZ4740_CLK_DMA>;
268	};
269
270	uhc: uhc@13030000 {
271		compatible = "ingenic,jz4740-ohci", "generic-ohci";
272		reg = <0x13030000 0x1000>;
273
274		clocks = <&cgu JZ4740_CLK_UHC>;
275		assigned-clocks = <&cgu JZ4740_CLK_UHC>;
276		assigned-clock-rates = <48000000>;
277
278		interrupt-parent = <&intc>;
279		interrupts = <3>;
280
281		status = "disabled";
282	};
283
284	udc: usb@13040000 {
285		compatible = "ingenic,jz4740-musb";
286		reg = <0x13040000 0x10000>;
287
288		interrupt-parent = <&intc>;
289		interrupts = <24>;
290		interrupt-names = "mc";
291
292		clocks = <&cgu JZ4740_CLK_UDC>;
293		clock-names = "udc";
294	};
295
296	lcd: lcd-controller@13050000 {
297		compatible = "ingenic,jz4740-lcd";
298		reg = <0x13050000 0x1000>;
299
300		interrupt-parent = <&intc>;
301		interrupts = <30>;
302
303		clocks = <&cgu JZ4740_CLK_LCD_PCLK>, <&cgu JZ4740_CLK_LCD>;
304		clock-names = "lcd_pclk", "lcd";
305	};
306};
307