1// SPDX-License-Identifier: GPL-2.0 2/dts-v1/; 3 4#include "jz4770.dtsi" 5#include <dt-bindings/clock/ingenic,tcu.h> 6 7/ { 8 compatible = "gcw,zero", "ingenic,jz4770"; 9 model = "GCW Zero"; 10 11 aliases { 12 serial0 = &uart0; 13 serial1 = &uart1; 14 serial2 = &uart2; 15 serial3 = &uart3; 16 }; 17 18 chosen { 19 stdout-path = "serial2:57600n8"; 20 }; 21 22 board { 23 compatible = "simple-bus"; 24 #address-cells = <1>; 25 #size-cells = <1>; 26 ranges; 27 28 otg_phy: otg-phy { 29 compatible = "usb-nop-xceiv"; 30 clocks = <&cgu JZ4770_CLK_OTG_PHY>; 31 clock-names = "main_clk"; 32 }; 33 }; 34}; 35 36&ext { 37 clock-frequency = <12000000>; 38}; 39 40&uart2 { 41 status = "okay"; 42}; 43 44&cgu { 45 /* Put high-speed peripherals under PLL1, such that we can change the 46 * PLL0 frequency on demand without having to suspend peripherals. 47 * We use a rate of 432 MHz, which is the least common multiple of 48 * 27 MHz (required by TV encoder) and 48 MHz (required by USB host). 49 */ 50 assigned-clocks = 51 <&cgu JZ4770_CLK_PLL1>, 52 <&cgu JZ4770_CLK_UHC>; 53 assigned-clock-parents = 54 <0>, 55 <&cgu JZ4770_CLK_PLL1>; 56 assigned-clock-rates = 57 <432000000>; 58}; 59 60&uhc { 61 /* The WiFi module is connected to the UHC. */ 62 status = "okay"; 63}; 64 65&tcu { 66 /* 750 kHz for the system timer and clocksource */ 67 assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER2>; 68 assigned-clock-rates = <750000>, <750000>; 69 70 /* PWM1 is in use, so reserve channel #2 for the clocksource */ 71 ingenic,pwm-channels-mask = <0xfa>; 72}; 73