1// SPDX-License-Identifier: GPL-2.0 2/dts-v1/; 3 4#include "jz4780.dtsi" 5#include <dt-bindings/clock/ingenic,tcu.h> 6#include <dt-bindings/gpio/gpio.h> 7#include <dt-bindings/input/input.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/regulator/active-semi,8865-regulator.h> 10 11/ { 12 compatible = "img,ci20", "ingenic,jz4780"; 13 14 aliases { 15 serial0 = &uart0; 16 serial1 = &uart1; 17 serial3 = &uart3; 18 serial4 = &uart4; 19 }; 20 21 chosen { 22 stdout-path = &uart4; 23 }; 24 25 memory { 26 device_type = "memory"; 27 reg = <0x0 0x10000000 28 0x30000000 0x30000000>; 29 }; 30 31 gpio-keys { 32 compatible = "gpio-keys"; 33 34 sw1 { 35 label = "ci20:sw1"; 36 linux,code = <KEY_F13>; 37 gpios = <&gpd 17 GPIO_ACTIVE_HIGH>; 38 wakeup-source; 39 }; 40 }; 41 42 leds { 43 compatible = "gpio-leds"; 44 45 led0 { 46 label = "ci20:red:led0"; 47 gpios = <&gpc 3 GPIO_ACTIVE_HIGH>; 48 linux,default-trigger = "none"; 49 }; 50 51 led1 { 52 label = "ci20:red:led1"; 53 gpios = <&gpc 2 GPIO_ACTIVE_HIGH>; 54 linux,default-trigger = "nand-disk"; 55 }; 56 57 led2 { 58 label = "ci20:red:led2"; 59 gpios = <&gpc 1 GPIO_ACTIVE_HIGH>; 60 linux,default-trigger = "cpu1"; 61 }; 62 63 led3 { 64 label = "ci20:red:led3"; 65 gpios = <&gpc 0 GPIO_ACTIVE_HIGH>; 66 linux,default-trigger = "cpu0"; 67 }; 68 }; 69 70 eth0_power: fixedregulator@0 { 71 compatible = "regulator-fixed"; 72 73 regulator-name = "eth0_power"; 74 regulator-min-microvolt = <3300000>; 75 regulator-max-microvolt = <3300000>; 76 77 gpio = <&gpb 25 GPIO_ACTIVE_LOW>; 78 enable-active-high; 79 }; 80 81 ir: ir { 82 compatible = "gpio-ir-receiver"; 83 gpios = <&gpe 3 GPIO_ACTIVE_LOW>; 84 }; 85 86 wlan0_power: fixedregulator@1 { 87 compatible = "regulator-fixed"; 88 89 regulator-name = "wlan0_power"; 90 91 gpio = <&gpb 19 GPIO_ACTIVE_LOW>; 92 enable-active-high; 93 }; 94 95 otg_power: fixedregulator@2 { 96 compatible = "regulator-fixed"; 97 98 regulator-name = "otg_power"; 99 regulator-min-microvolt = <5000000>; 100 regulator-max-microvolt = <5000000>; 101 102 gpio = <&gpf 14 GPIO_ACTIVE_LOW>; 103 enable-active-high; 104 }; 105}; 106 107&ext { 108 clock-frequency = <48000000>; 109}; 110 111&cgu { 112 /* 113 * Use the 32.768 kHz oscillator as the parent of the RTC for a higher 114 * precision. 115 */ 116 assigned-clocks = <&cgu JZ4780_CLK_OTGPHY>, <&cgu JZ4780_CLK_RTC>; 117 assigned-clock-parents = <0>, <&cgu JZ4780_CLK_RTCLK>; 118 assigned-clock-rates = <48000000>; 119}; 120 121&tcu { 122 /* 123 * 750 kHz for the system timers and clocksource, 124 * use channel #0 and #1 for the per cpu system timers, 125 * and use channel #2 for the clocksource. 126 * 127 * 3000 kHz for the OST timer to provide a higher 128 * precision clocksource. 129 */ 130 assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>, 131 <&tcu TCU_CLK_TIMER2>, <&tcu TCU_CLK_OST>; 132 assigned-clock-rates = <750000>, <750000>, <750000>, <3000000>; 133}; 134 135&mmc0 { 136 status = "okay"; 137 138 bus-width = <4>; 139 max-frequency = <50000000>; 140 141 pinctrl-names = "default"; 142 pinctrl-0 = <&pins_mmc0>; 143 144 cd-gpios = <&gpf 20 GPIO_ACTIVE_LOW>; 145}; 146 147&mmc1 { 148 status = "okay"; 149 150 bus-width = <4>; 151 max-frequency = <50000000>; 152 non-removable; 153 154 pinctrl-names = "default"; 155 pinctrl-0 = <&pins_mmc1>; 156 157 brcmf: wifi@1 { 158/* reg = <4>;*/ 159 compatible = "brcm,bcm4330-fmac"; 160 vcc-supply = <&wlan0_power>; 161 device-wakeup-gpios = <&gpd 9 GPIO_ACTIVE_HIGH>; 162 shutdown-gpios = <&gpf 7 GPIO_ACTIVE_LOW>; 163 }; 164}; 165 166&uart0 { 167 status = "okay"; 168 169 pinctrl-names = "default"; 170 pinctrl-0 = <&pins_uart0>; 171}; 172 173&uart1 { 174 status = "okay"; 175 176 pinctrl-names = "default"; 177 pinctrl-0 = <&pins_uart1>; 178}; 179 180&uart2 { 181 status = "okay"; 182 183 pinctrl-names = "default"; 184 pinctrl-0 = <&pins_uart2>; 185 uart-has-rtscts; 186 187 bluetooth { 188 compatible = "brcm,bcm4330-bt"; 189 reset-gpios = <&gpf 8 GPIO_ACTIVE_HIGH>; 190 vcc-supply = <&wlan0_power>; 191 device-wakeup-gpios = <&gpf 5 GPIO_ACTIVE_HIGH>; 192 host-wakeup-gpios = <&gpf 6 GPIO_ACTIVE_HIGH>; 193 shutdown-gpios = <&gpf 4 GPIO_ACTIVE_LOW>; 194 }; 195}; 196 197&uart3 { 198 status = "okay"; 199 200 pinctrl-names = "default"; 201 pinctrl-0 = <&pins_uart3>; 202}; 203 204&uart4 { 205 status = "okay"; 206 207 pinctrl-names = "default"; 208 pinctrl-0 = <&pins_uart4>; 209}; 210 211&i2c0 { 212 status = "okay"; 213 214 pinctrl-names = "default"; 215 pinctrl-0 = <&pins_i2c0>; 216 217 clock-frequency = <400000>; 218 219 act8600: act8600@5a { 220 compatible = "active-semi,act8600"; 221 reg = <0x5a>; 222 status = "okay"; 223 224 regulators { 225 vddcore: SUDCDC1 { 226 regulator-name = "DCDC_REG1"; 227 regulator-min-microvolt = <1100000>; 228 regulator-max-microvolt = <1100000>; 229 regulator-always-on; 230 }; 231 vddmem: SUDCDC2 { 232 regulator-name = "DCDC_REG2"; 233 regulator-min-microvolt = <1500000>; 234 regulator-max-microvolt = <1500000>; 235 regulator-always-on; 236 }; 237 vcc_33: SUDCDC3 { 238 regulator-name = "DCDC_REG3"; 239 regulator-min-microvolt = <3300000>; 240 regulator-max-microvolt = <3300000>; 241 regulator-always-on; 242 }; 243 vcc_50: SUDCDC4 { 244 regulator-name = "SUDCDC_REG4"; 245 regulator-min-microvolt = <5000000>; 246 regulator-max-microvolt = <5000000>; 247 regulator-always-on; 248 }; 249 vcc_25: LDO_REG5 { 250 regulator-name = "LDO_REG5"; 251 regulator-min-microvolt = <2500000>; 252 regulator-max-microvolt = <2500000>; 253 regulator-always-on; 254 }; 255 wifi_io: LDO_REG6 { 256 regulator-name = "LDO_REG6"; 257 regulator-min-microvolt = <2500000>; 258 regulator-max-microvolt = <2500000>; 259 regulator-always-on; 260 }; 261 vcc_28: LDO_REG7 { 262 regulator-name = "LDO_REG7"; 263 regulator-min-microvolt = <2800000>; 264 regulator-max-microvolt = <2800000>; 265 regulator-always-on; 266 }; 267 vcc_15: LDO_REG8 { 268 regulator-name = "LDO_REG8"; 269 regulator-min-microvolt = <1500000>; 270 regulator-max-microvolt = <1500000>; 271 regulator-always-on; 272 }; 273 vrtc_18: LDO_REG9 { 274 regulator-name = "LDO_REG9"; 275 /* Despite the datasheet stating 3.3V 276 * for REG9 and the driver expecting that, 277 * REG9 outputs 1.8V. 278 * Likely the CI20 uses a proprietary 279 * factory programmed chip variant. 280 * Since this is a simple on/off LDO the 281 * exact values do not matter. 282 */ 283 regulator-min-microvolt = <3300000>; 284 regulator-max-microvolt = <3300000>; 285 regulator-always-on; 286 }; 287 vcc_11: LDO_REG10 { 288 regulator-name = "LDO_REG10"; 289 regulator-min-microvolt = <1200000>; 290 regulator-max-microvolt = <1200000>; 291 regulator-always-on; 292 }; 293 }; 294 }; 295}; 296 297&i2c1 { 298 status = "okay"; 299 300 pinctrl-names = "default"; 301 pinctrl-0 = <&pins_i2c1>; 302 303}; 304 305&i2c2 { 306 status = "okay"; 307 308 pinctrl-names = "default"; 309 pinctrl-0 = <&pins_i2c2>; 310 311}; 312 313&i2c3 { 314 status = "okay"; 315 316 pinctrl-names = "default"; 317 pinctrl-0 = <&pins_i2c3>; 318 319}; 320 321&i2c4 { 322 status = "okay"; 323 324 pinctrl-names = "default"; 325 pinctrl-0 = <&pins_i2c4>; 326 327 clock-frequency = <400000>; 328 329 rtc@51 { 330 compatible = "nxp,pcf8563"; 331 reg = <0x51>; 332 333 interrupt-parent = <&gpf>; 334 interrupts = <30 IRQ_TYPE_LEVEL_LOW>; 335 }; 336}; 337 338&nemc { 339 status = "okay"; 340 341 nandc: nand-controller@1 { 342 compatible = "ingenic,jz4780-nand"; 343 reg = <1 0 0x1000000>; 344 345 #address-cells = <1>; 346 #size-cells = <0>; 347 348 ingenic,bch-controller = <&bch>; 349 350 ingenic,nemc-tAS = <10>; 351 ingenic,nemc-tAH = <5>; 352 ingenic,nemc-tBP = <10>; 353 ingenic,nemc-tAW = <15>; 354 ingenic,nemc-tSTRV = <100>; 355 356 /* 357 * Only CLE/ALE are needed for the devices that are connected, rather 358 * than the full address line set. 359 */ 360 pinctrl-names = "default"; 361 pinctrl-0 = <&pins_nemc>; 362 363 nand@1 { 364 reg = <1>; 365 366 nand-ecc-step-size = <1024>; 367 nand-ecc-strength = <24>; 368 nand-ecc-mode = "hw"; 369 nand-on-flash-bbt; 370 371 pinctrl-names = "default"; 372 pinctrl-0 = <&pins_nemc_cs1>; 373 374 partitions { 375 compatible = "fixed-partitions"; 376 #address-cells = <2>; 377 #size-cells = <2>; 378 379 partition@0 { 380 label = "u-boot-spl"; 381 reg = <0x0 0x0 0x0 0x800000>; 382 }; 383 384 partition@800000 { 385 label = "u-boot"; 386 reg = <0x0 0x800000 0x0 0x200000>; 387 }; 388 389 partition@a00000 { 390 label = "u-boot-env"; 391 reg = <0x0 0xa00000 0x0 0x200000>; 392 }; 393 394 partition@c00000 { 395 label = "boot"; 396 reg = <0x0 0xc00000 0x0 0x4000000>; 397 }; 398 399 partition@4c00000 { 400 label = "system"; 401 reg = <0x0 0x4c00000 0x1 0xfb400000>; 402 }; 403 }; 404 }; 405 }; 406 407 dm9000@6 { 408 compatible = "davicom,dm9000"; 409 davicom,no-eeprom; 410 411 pinctrl-names = "default"; 412 pinctrl-0 = <&pins_nemc_cs6>; 413 414 reg = <6 0 1 /* addr */ 415 6 2 1>; /* data */ 416 417 ingenic,nemc-tAS = <15>; 418 ingenic,nemc-tAH = <10>; 419 ingenic,nemc-tBP = <20>; 420 ingenic,nemc-tAW = <50>; 421 ingenic,nemc-tSTRV = <100>; 422 423 reset-gpios = <&gpf 12 GPIO_ACTIVE_HIGH>; 424 vcc-supply = <ð0_power>; 425 426 interrupt-parent = <&gpe>; 427 interrupts = <19 4>; 428 429 nvmem-cells = <ð0_addr>; 430 nvmem-cell-names = "mac-address"; 431 }; 432}; 433 434&bch { 435 status = "okay"; 436}; 437 438&otg_phy { 439 status = "okay"; 440 441 vcc-supply = <&otg_power>; 442}; 443 444&otg { 445 status = "okay"; 446}; 447 448&pinctrl { 449 pins_uart0: uart0 { 450 function = "uart0"; 451 groups = "uart0-data"; 452 bias-disable; 453 }; 454 455 pins_uart1: uart1 { 456 function = "uart1"; 457 groups = "uart1-data"; 458 bias-disable; 459 }; 460 461 pins_uart2: uart2 { 462 function = "uart2"; 463 groups = "uart2-data", "uart2-hwflow"; 464 bias-disable; 465 }; 466 467 pins_uart3: uart3 { 468 function = "uart3"; 469 groups = "uart3-data", "uart3-hwflow"; 470 bias-disable; 471 }; 472 473 pins_uart4: uart4 { 474 function = "uart4"; 475 groups = "uart4-data"; 476 bias-disable; 477 }; 478 479 pins_i2c0: i2c0 { 480 function = "i2c0"; 481 groups = "i2c0-data"; 482 bias-disable; 483 }; 484 485 pins_i2c1: i2c1 { 486 function = "i2c1"; 487 groups = "i2c1-data"; 488 bias-disable; 489 }; 490 491 pins_i2c2: i2c2 { 492 function = "i2c2"; 493 groups = "i2c2-data"; 494 bias-disable; 495 }; 496 497 pins_i2c3: i2c3 { 498 function = "i2c3"; 499 groups = "i2c3-data"; 500 bias-disable; 501 }; 502 503 pins_i2c4: i2c4 { 504 function = "i2c4"; 505 groups = "i2c4-data-e"; 506 bias-disable; 507 }; 508 509 pins_nemc: nemc { 510 function = "nemc"; 511 groups = "nemc-data", "nemc-cle-ale", "nemc-rd-we", "nemc-frd-fwe"; 512 bias-disable; 513 }; 514 515 pins_nemc_cs1: nemc-cs1 { 516 function = "nemc-cs1"; 517 groups = "nemc-cs1"; 518 bias-disable; 519 }; 520 521 pins_nemc_cs6: nemc-cs6 { 522 function = "nemc-cs6"; 523 groups = "nemc-cs6"; 524 bias-disable; 525 }; 526 527 pins_mmc0: mmc0 { 528 function = "mmc0"; 529 groups = "mmc0-1bit-e", "mmc0-4bit-e"; 530 bias-disable; 531 }; 532 533 pins_mmc1: mmc1 { 534 function = "mmc1"; 535 groups = "mmc1-1bit-d", "mmc1-4bit-d"; 536 bias-disable; 537 }; 538}; 539