1/* OCTEON 3XXX DTS common parts. */ 2 3/dts-v1/; 4 5/ { 6 compatible = "cavium,octeon-3860"; 7 #address-cells = <2>; 8 #size-cells = <2>; 9 interrupt-parent = <&ciu>; 10 11 soc@0 { 12 compatible = "simple-bus"; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 ranges; /* Direct mapping */ 16 17 ciu: interrupt-controller@1070000000000 { 18 compatible = "cavium,octeon-3860-ciu"; 19 interrupt-controller; 20 /* Interrupts are specified by two parts: 21 * 1) Controller register (0 or 1) 22 * 2) Bit within the register (0..63) 23 */ 24 #interrupt-cells = <2>; 25 reg = <0x10700 0x00000000 0x0 0x7000>; 26 }; 27 28 gpio: gpio-controller@1070000000800 { 29 #gpio-cells = <2>; 30 compatible = "cavium,octeon-3860-gpio"; 31 reg = <0x10700 0x00000800 0x0 0x100>; 32 gpio-controller; 33 /* Interrupts are specified by two parts: 34 * 1) GPIO pin number (0..15) 35 * 2) Triggering (1 - edge rising 36 * 2 - edge falling 37 * 4 - level active high 38 * 8 - level active low) 39 */ 40 interrupt-controller; 41 #interrupt-cells = <2>; 42 /* The GPIO pin connect to 16 consecutive CUI bits */ 43 interrupts = <0 16>, <0 17>, <0 18>, <0 19>, 44 <0 20>, <0 21>, <0 22>, <0 23>, 45 <0 24>, <0 25>, <0 26>, <0 27>, 46 <0 28>, <0 29>, <0 30>, <0 31>; 47 }; 48 49 smi0: mdio@1180000001800 { 50 compatible = "cavium,octeon-3860-mdio"; 51 #address-cells = <1>; 52 #size-cells = <0>; 53 reg = <0x11800 0x00001800 0x0 0x40>; 54 }; 55 56 pip: pip@11800a0000000 { 57 compatible = "cavium,octeon-3860-pip"; 58 #address-cells = <1>; 59 #size-cells = <0>; 60 reg = <0x11800 0xa0000000 0x0 0x2000>; 61 62 interface@0 { 63 compatible = "cavium,octeon-3860-pip-interface"; 64 #address-cells = <1>; 65 #size-cells = <0>; 66 reg = <0>; /* interface */ 67 68 ethernet@0 { 69 compatible = "cavium,octeon-3860-pip-port"; 70 reg = <0x0>; /* Port */ 71 local-mac-address = [ 00 00 00 00 00 00 ]; 72 }; 73 ethernet@1 { 74 compatible = "cavium,octeon-3860-pip-port"; 75 reg = <0x1>; /* Port */ 76 local-mac-address = [ 00 00 00 00 00 00 ]; 77 }; 78 ethernet@2 { 79 compatible = "cavium,octeon-3860-pip-port"; 80 reg = <0x2>; /* Port */ 81 local-mac-address = [ 00 00 00 00 00 00 ]; 82 }; 83 }; 84 85 interface@1 { 86 compatible = "cavium,octeon-3860-pip-interface"; 87 #address-cells = <1>; 88 #size-cells = <0>; 89 reg = <1>; /* interface */ 90 }; 91 }; 92 93 twsi0: i2c@1180000001000 { 94 #address-cells = <1>; 95 #size-cells = <0>; 96 compatible = "cavium,octeon-3860-twsi"; 97 reg = <0x11800 0x00001000 0x0 0x200>; 98 interrupts = <0 45>; 99 clock-frequency = <100000>; 100 }; 101 102 uart0: serial@1180000000800 { 103 compatible = "cavium,octeon-3860-uart","ns16550"; 104 reg = <0x11800 0x00000800 0x0 0x400>; 105 clock-frequency = <0>; 106 current-speed = <115200>; 107 reg-shift = <3>; 108 interrupts = <0 34>; 109 }; 110 111 bootbus: bootbus@1180000000000 { 112 compatible = "cavium,octeon-3860-bootbus"; 113 reg = <0x11800 0x00000000 0x0 0x200>; 114 /* The chip select number and offset */ 115 #address-cells = <2>; 116 /* The size of the chip select region */ 117 #size-cells = <1>; 118 ranges = <0 0 0x0 0x1f400000 0xc00000>, 119 <1 0 0x10000 0x30000000 0>, 120 <2 0 0x10000 0x40000000 0>, 121 <3 0 0x10000 0x50000000 0>, 122 <4 0 0x0 0x1d020000 0x10000>, 123 <5 0 0x0 0x1d040000 0x10000>, 124 <6 0 0x0 0x1d050000 0x10000>, 125 <7 0 0x10000 0x90000000 0>; 126 127 cavium,cs-config@0 { 128 compatible = "cavium,octeon-3860-bootbus-config"; 129 cavium,cs-index = <0>; 130 cavium,t-adr = <20>; 131 cavium,t-ce = <60>; 132 cavium,t-oe = <60>; 133 cavium,t-we = <45>; 134 cavium,t-rd-hld = <35>; 135 cavium,t-wr-hld = <45>; 136 cavium,t-pause = <0>; 137 cavium,t-wait = <0>; 138 cavium,t-page = <35>; 139 cavium,t-rd-dly = <0>; 140 141 cavium,pages = <0>; 142 cavium,bus-width = <8>; 143 }; 144 cavium,cs-config@4 { 145 compatible = "cavium,octeon-3860-bootbus-config"; 146 cavium,cs-index = <4>; 147 cavium,t-adr = <320>; 148 cavium,t-ce = <320>; 149 cavium,t-oe = <320>; 150 cavium,t-we = <320>; 151 cavium,t-rd-hld = <320>; 152 cavium,t-wr-hld = <320>; 153 cavium,t-pause = <320>; 154 cavium,t-wait = <320>; 155 cavium,t-page = <320>; 156 cavium,t-rd-dly = <0>; 157 158 cavium,pages = <0>; 159 cavium,bus-width = <8>; 160 }; 161 cavium,cs-config@5 { 162 compatible = "cavium,octeon-3860-bootbus-config"; 163 cavium,cs-index = <5>; 164 cavium,t-adr = <5>; 165 cavium,t-ce = <300>; 166 cavium,t-oe = <125>; 167 cavium,t-we = <150>; 168 cavium,t-rd-hld = <100>; 169 cavium,t-wr-hld = <30>; 170 cavium,t-pause = <0>; 171 cavium,t-wait = <30>; 172 cavium,t-page = <320>; 173 cavium,t-rd-dly = <0>; 174 175 cavium,pages = <0>; 176 cavium,bus-width = <16>; 177 }; 178 cavium,cs-config@6 { 179 compatible = "cavium,octeon-3860-bootbus-config"; 180 cavium,cs-index = <6>; 181 cavium,t-adr = <5>; 182 cavium,t-ce = <300>; 183 cavium,t-oe = <270>; 184 cavium,t-we = <150>; 185 cavium,t-rd-hld = <100>; 186 cavium,t-wr-hld = <70>; 187 cavium,t-pause = <0>; 188 cavium,t-wait = <0>; 189 cavium,t-page = <320>; 190 cavium,t-rd-dly = <0>; 191 192 cavium,pages = <0>; 193 cavium,wait-mode; 194 cavium,bus-width = <16>; 195 }; 196 197 flash0: nor@0,0 { 198 compatible = "cfi-flash"; 199 reg = <0 0 0x800000>; 200 #address-cells = <1>; 201 #size-cells = <1>; 202 }; 203 }; 204 205 dma0: dma-engine@1180000000100 { 206 compatible = "cavium,octeon-5750-bootbus-dma"; 207 reg = <0x11800 0x00000100 0x0 0x8>; 208 interrupts = <0 63>; 209 }; 210 211 dma1: dma-engine@1180000000108 { 212 compatible = "cavium,octeon-5750-bootbus-dma"; 213 reg = <0x11800 0x00000108 0x0 0x8>; 214 interrupts = <0 63>; 215 }; 216 217 usbn: usbn@1180068000000 { 218 compatible = "cavium,octeon-5750-usbn"; 219 reg = <0x11800 0x68000000 0x0 0x1000>; 220 ranges; /* Direct mapping */ 221 #address-cells = <2>; 222 #size-cells = <2>; 223 224 usbc@16f0010000000 { 225 compatible = "cavium,octeon-5750-usbc"; 226 reg = <0x16f00 0x10000000 0x0 0x80000>; 227 interrupts = <0 56>; 228 }; 229 }; 230 }; 231}; 232