1// SPDX-License-Identifier: GPL-2.0
2/*
3 * OCTEON 3XXX, 5XXX, 63XX device tree skeleton.
4 *
5 * This device tree is pruned and patched by early boot code before
6 * use.	 Because of this, it contains a super-set of the available
7 * devices and properties.
8 */
9
10/include/ "octeon_3xxx.dtsi"
11
12/ {
13	soc@0 {
14		smi0: mdio@1180000001800 {
15			phy0: ethernet-phy@0 {
16				compatible = "marvell,88e1118";
17				marvell,reg-init =
18					/* Fix rx and tx clock transition timing */
19					<2 0x15 0xffcf 0>, /* Reg 2,21 Clear bits 4, 5 */
20					/* Adjust LED drive. */
21					<3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
22					/* irq, blink-activity, blink-link */
23					<3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */
24				reg = <0>;
25			};
26
27			phy1: ethernet-phy@1 {
28				compatible = "marvell,88e1118";
29				marvell,reg-init =
30					/* Fix rx and tx clock transition timing */
31					<2 0x15 0xffcf 0>, /* Reg 2,21 Clear bits 4, 5 */
32					/* Adjust LED drive. */
33					<3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
34					/* irq, blink-activity, blink-link */
35					<3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */
36				reg = <1>;
37			};
38
39			phy2: ethernet-phy@2 {
40				reg = <2>;
41				compatible = "marvell,88e1149r";
42				marvell,reg-init = <3 0x10 0 0x5777>,
43					<3 0x11 0 0x00aa>,
44					<3 0x12 0 0x4105>,
45					<3 0x13 0 0x0a60>;
46			};
47			phy3: ethernet-phy@3 {
48				reg = <3>;
49				compatible = "marvell,88e1149r";
50				marvell,reg-init = <3 0x10 0 0x5777>,
51					<3 0x11 0 0x00aa>,
52					<3 0x12 0 0x4105>,
53					<3 0x13 0 0x0a60>;
54			};
55			phy4: ethernet-phy@4 {
56				reg = <4>;
57				compatible = "marvell,88e1149r";
58				marvell,reg-init = <3 0x10 0 0x5777>,
59					<3 0x11 0 0x00aa>,
60					<3 0x12 0 0x4105>,
61					<3 0x13 0 0x0a60>;
62			};
63			phy5: ethernet-phy@5 {
64				reg = <5>;
65				compatible = "marvell,88e1149r";
66				marvell,reg-init = <3 0x10 0 0x5777>,
67					<3 0x11 0 0x00aa>,
68					<3 0x12 0 0x4105>,
69					<3 0x13 0 0x0a60>;
70			};
71
72			phy6: ethernet-phy@6 {
73				reg = <6>;
74				compatible = "marvell,88e1149r";
75				marvell,reg-init = <3 0x10 0 0x5777>,
76					<3 0x11 0 0x00aa>,
77					<3 0x12 0 0x4105>,
78					<3 0x13 0 0x0a60>;
79			};
80			phy7: ethernet-phy@7 {
81				reg = <7>;
82				compatible = "marvell,88e1149r";
83				marvell,reg-init = <3 0x10 0 0x5777>,
84					<3 0x11 0 0x00aa>,
85					<3 0x12 0 0x4105>,
86					<3 0x13 0 0x0a60>;
87			};
88			phy8: ethernet-phy@8 {
89				reg = <8>;
90				compatible = "marvell,88e1149r";
91				marvell,reg-init = <3 0x10 0 0x5777>,
92					<3 0x11 0 0x00aa>,
93					<3 0x12 0 0x4105>,
94					<3 0x13 0 0x0a60>;
95			};
96			phy9: ethernet-phy@9 {
97				reg = <9>;
98				compatible = "marvell,88e1149r";
99				marvell,reg-init = <3 0x10 0 0x5777>,
100					<3 0x11 0 0x00aa>,
101					<3 0x12 0 0x4105>,
102					<3 0x13 0 0x0a60>;
103			};
104		};
105
106		smi1: mdio@1180000001900 {
107			compatible = "cavium,octeon-3860-mdio";
108			#address-cells = <1>;
109			#size-cells = <0>;
110			reg = <0x11800 0x00001900 0x0 0x40>;
111
112			phy100: ethernet-phy@1 {
113				reg = <1>;
114				compatible = "marvell,88e1149r";
115				marvell,reg-init = <3 0x10 0 0x5777>,
116					<3 0x11 0 0x00aa>,
117					<3 0x12 0 0x4105>,
118					<3 0x13 0 0x0a60>;
119				interrupt-parent = <&gpio>;
120				interrupts = <12 8>; /* Pin 12, active low */
121			};
122			phy101: ethernet-phy@2 {
123				reg = <2>;
124				compatible = "marvell,88e1149r";
125				marvell,reg-init = <3 0x10 0 0x5777>,
126					<3 0x11 0 0x00aa>,
127					<3 0x12 0 0x4105>,
128					<3 0x13 0 0x0a60>;
129				interrupt-parent = <&gpio>;
130				interrupts = <12 8>; /* Pin 12, active low */
131			};
132			phy102: ethernet-phy@3 {
133				reg = <3>;
134				compatible = "marvell,88e1149r";
135				marvell,reg-init = <3 0x10 0 0x5777>,
136					<3 0x11 0 0x00aa>,
137					<3 0x12 0 0x4105>,
138					<3 0x13 0 0x0a60>;
139				interrupt-parent = <&gpio>;
140				interrupts = <12 8>; /* Pin 12, active low */
141			};
142			phy103: ethernet-phy@4 {
143				reg = <4>;
144				compatible = "marvell,88e1149r";
145				marvell,reg-init = <3 0x10 0 0x5777>,
146					<3 0x11 0 0x00aa>,
147					<3 0x12 0 0x4105>,
148					<3 0x13 0 0x0a60>;
149				interrupt-parent = <&gpio>;
150				interrupts = <12 8>; /* Pin 12, active low */
151			};
152		};
153
154		mix0: ethernet@1070000100000 {
155			compatible = "cavium,octeon-5750-mix";
156			reg = <0x10700 0x00100000 0x0 0x100>, /* MIX */
157			      <0x11800 0xE0000000 0x0 0x300>, /* AGL */
158			      <0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED  */
159			      <0x11800 0xE0002000 0x0 0x8>;   /* AGL_PRT_CTL */
160			cell-index = <0>;
161			interrupts = <0 62>, <1 46>;
162			local-mac-address = [ 00 00 00 00 00 00 ];
163			phy-handle = <&phy0>;
164		};
165
166		mix1: ethernet@1070000100800 {
167			compatible = "cavium,octeon-5750-mix";
168			reg = <0x10700 0x00100800 0x0 0x100>, /* MIX */
169			      <0x11800 0xE0000800 0x0 0x300>, /* AGL */
170			      <0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED  */
171			      <0x11800 0xE0002008 0x0 0x8>;   /* AGL_PRT_CTL */
172			cell-index = <1>;
173			interrupts = <1 18>, < 1 46>;
174			local-mac-address = [ 00 00 00 00 00 00 ];
175			phy-handle = <&phy1>;
176		};
177
178		pip: pip@11800a0000000 {
179			interface@0 {
180				ethernet@0 {
181					phy-handle = <&phy2>;
182					cavium,alt-phy-handle = <&phy100>;
183				};
184				ethernet@1 {
185					phy-handle = <&phy3>;
186					cavium,alt-phy-handle = <&phy101>;
187				};
188				ethernet@2 {
189					phy-handle = <&phy4>;
190					cavium,alt-phy-handle = <&phy102>;
191				};
192				ethernet@3 {
193					compatible = "cavium,octeon-3860-pip-port";
194					reg = <0x3>; /* Port */
195					local-mac-address = [ 00 00 00 00 00 00 ];
196					phy-handle = <&phy5>;
197					cavium,alt-phy-handle = <&phy103>;
198				};
199				ethernet@4 {
200					compatible = "cavium,octeon-3860-pip-port";
201					reg = <0x4>; /* Port */
202					local-mac-address = [ 00 00 00 00 00 00 ];
203				};
204				ethernet@5 {
205					compatible = "cavium,octeon-3860-pip-port";
206					reg = <0x5>; /* Port */
207					local-mac-address = [ 00 00 00 00 00 00 ];
208				};
209				ethernet@6 {
210					compatible = "cavium,octeon-3860-pip-port";
211					reg = <0x6>; /* Port */
212					local-mac-address = [ 00 00 00 00 00 00 ];
213				};
214				ethernet@7 {
215					compatible = "cavium,octeon-3860-pip-port";
216					reg = <0x7>; /* Port */
217					local-mac-address = [ 00 00 00 00 00 00 ];
218				};
219				ethernet@8 {
220					compatible = "cavium,octeon-3860-pip-port";
221					reg = <0x8>; /* Port */
222					local-mac-address = [ 00 00 00 00 00 00 ];
223				};
224				ethernet@9 {
225					compatible = "cavium,octeon-3860-pip-port";
226					reg = <0x9>; /* Port */
227					local-mac-address = [ 00 00 00 00 00 00 ];
228				};
229				ethernet@a {
230					compatible = "cavium,octeon-3860-pip-port";
231					reg = <0xa>; /* Port */
232					local-mac-address = [ 00 00 00 00 00 00 ];
233				};
234				ethernet@b {
235					compatible = "cavium,octeon-3860-pip-port";
236					reg = <0xb>; /* Port */
237					local-mac-address = [ 00 00 00 00 00 00 ];
238				};
239				ethernet@c {
240					compatible = "cavium,octeon-3860-pip-port";
241					reg = <0xc>; /* Port */
242					local-mac-address = [ 00 00 00 00 00 00 ];
243				};
244				ethernet@d {
245					compatible = "cavium,octeon-3860-pip-port";
246					reg = <0xd>; /* Port */
247					local-mac-address = [ 00 00 00 00 00 00 ];
248				};
249				ethernet@e {
250					compatible = "cavium,octeon-3860-pip-port";
251					reg = <0xe>; /* Port */
252					local-mac-address = [ 00 00 00 00 00 00 ];
253				};
254				ethernet@f {
255					compatible = "cavium,octeon-3860-pip-port";
256					reg = <0xf>; /* Port */
257					local-mac-address = [ 00 00 00 00 00 00 ];
258				};
259			};
260
261			interface@1 {
262				ethernet@0 {
263					compatible = "cavium,octeon-3860-pip-port";
264					reg = <0x0>; /* Port */
265					local-mac-address = [ 00 00 00 00 00 00 ];
266					phy-handle = <&phy6>;
267				};
268				ethernet@1 {
269					compatible = "cavium,octeon-3860-pip-port";
270					reg = <0x1>; /* Port */
271					local-mac-address = [ 00 00 00 00 00 00 ];
272					phy-handle = <&phy7>;
273				};
274				ethernet@2 {
275					compatible = "cavium,octeon-3860-pip-port";
276					reg = <0x2>; /* Port */
277					local-mac-address = [ 00 00 00 00 00 00 ];
278					phy-handle = <&phy8>;
279				};
280				ethernet@3 {
281					compatible = "cavium,octeon-3860-pip-port";
282					reg = <0x3>; /* Port */
283					local-mac-address = [ 00 00 00 00 00 00 ];
284					phy-handle = <&phy9>;
285				};
286			};
287		};
288
289		twsi0: i2c@1180000001000 {
290			rtc@68 {
291				compatible = "dallas,ds1337";
292				reg = <0x68>;
293			};
294			tmp@4c {
295				compatible = "ti,tmp421";
296				reg = <0x4c>;
297			};
298		};
299
300		twsi1: i2c@1180000001200 {
301			#address-cells = <1>;
302			#size-cells = <0>;
303			compatible = "cavium,octeon-3860-twsi";
304			reg = <0x11800 0x00001200 0x0 0x200>;
305			interrupts = <0 59>;
306			clock-frequency = <100000>;
307		};
308
309		uart1: serial@1180000000c00 {
310			compatible = "cavium,octeon-3860-uart","ns16550";
311			reg = <0x11800 0x00000c00 0x0 0x400>;
312			clock-frequency = <0>;
313			current-speed = <115200>;
314			reg-shift = <3>;
315			interrupts = <0 35>;
316		};
317
318		uart2: serial@1180000000400 {
319			compatible = "cavium,octeon-3860-uart","ns16550";
320			reg = <0x11800 0x00000400 0x0 0x400>;
321			clock-frequency = <0>;
322			current-speed = <115200>;
323			reg-shift = <3>;
324			interrupts = <1 16>;
325		};
326
327		bootbus: bootbus@1180000000000 {
328			led0: led-display@4,0 {
329				compatible = "avago,hdsp-253x";
330				reg = <4 0x20 0x20>, <4 0 0x20>;
331			};
332
333			cf0: compact-flash@5,0 {
334				compatible = "cavium,ebt3000-compact-flash";
335				reg = <5 0 0x10000>, <6 0 0x10000>;
336				cavium,bus-width = <16>;
337				cavium,true-ide;
338				cavium,dma-engine-handle = <&dma0>;
339			};
340		};
341
342		uctl: uctl@118006f000000 {
343			compatible = "cavium,octeon-6335-uctl";
344			reg = <0x11800 0x6f000000 0x0 0x100>;
345			ranges; /* Direct mapping */
346			#address-cells = <2>;
347			#size-cells = <2>;
348			/* 12MHz, 24MHz and 48MHz allowed */
349			refclk-frequency = <12000000>;
350			/* Either "crystal" or "external" */
351			refclk-type = "crystal";
352
353			ehci@16f0000000000 {
354				compatible = "cavium,octeon-6335-ehci","usb-ehci";
355				reg = <0x16f00 0x00000000 0x0 0x100>;
356				interrupts = <0 56>;
357				big-endian-regs;
358			};
359			ohci@16f0000000400 {
360				compatible = "cavium,octeon-6335-ohci","usb-ohci";
361				reg = <0x16f00 0x00000400 0x0 0x100>;
362				interrupts = <0 56>;
363				big-endian-regs;
364			};
365		};
366
367		usbn: usbn@1180068000000 {
368			/* 12MHz, 24MHz and 48MHz allowed */
369			refclk-frequency = <12000000>;
370			/* Either "crystal" or "external" */
371			refclk-type = "crystal";
372		};
373	};
374
375	aliases {
376		mix0 = &mix0;
377		mix1 = &mix1;
378		pip = &pip;
379		smi0 = &smi0;
380		smi1 = &smi1;
381		twsi0 = &twsi0;
382		twsi1 = &twsi1;
383		uart0 = &uart0;
384		uart1 = &uart1;
385		uart2 = &uart2;
386		flash0 = &flash0;
387		cf0 = &cf0;
388		uctl = &uctl;
389		usbn = &usbn;
390		led0 = &led0;
391	};
392 };
393